| Message ID | 20210806054904.534315-2-joel@jms.id.au |
|---|---|
| State | New |
| Headers | show |
| Series | net: Add LiteETH network driver | expand |
On Fri, 06 Aug 2021 15:19:03 +0930, Joel Stanley wrote: > LiteETH is a small footprint and configurable Ethernet core for FPGA > based system on chips. > > Signed-off-by: Joel Stanley <joel@jms.id.au> > --- > .../bindings/net/litex,liteeth.yaml | 62 +++++++++++++++++++ > 1 file changed, 62 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/litex,liteeth.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/net/litex,liteeth.example.dt.yaml: example-0: ethernet@8020000:reg:0: [134352896, 256, 134350848, 256, 134414336, 8192] is too long From schema: /usr/local/lib/python3.8/dist-packages/dtschema/schemas/reg.yaml /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/net/litex,liteeth.example.dt.yaml: ethernet@8020000: reg: [[134352896, 256, 134350848, 256, 134414336, 8192]] is too short From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/net/litex,liteeth.yaml doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/1514186 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
On Fri, Aug 06, 2021 at 03:19:03PM +0930, Joel Stanley wrote: > LiteETH is a small footprint and configurable Ethernet core for FPGA > based system on chips. > > Signed-off-by: Joel Stanley <joel@jms.id.au> > --- > .../bindings/net/litex,liteeth.yaml | 62 +++++++++++++++++++ > 1 file changed, 62 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/litex,liteeth.yaml > > diff --git a/Documentation/devicetree/bindings/net/litex,liteeth.yaml b/Documentation/devicetree/bindings/net/litex,liteeth.yaml > new file mode 100644 > index 000000000000..e2a837dbfdaa > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/litex,liteeth.yaml > @@ -0,0 +1,62 @@ > +# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/net/litex,liteeth.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: LiteX LiteETH ethernet device > + > +maintainers: > + - Joel Stanley <joel@jms.id.au> > + > +description: | > + LiteETH is a small footprint and configurable Ethernet core for FPGA based > + system on chips. > + > + The hardware source is Open Source and can be found on at > + https://github.com/enjoy-digital/liteeth/. > + > +properties: > + compatible: > + const: litex,liteeth > + > + reg: > + minItems: 3 > + items: > + - description: MAC registers > + - description: MDIO registers > + - description: Packet buffer Hi Joel How configurable is the synthesis? Can the MDIO bus be left out? You can have only the MDIO bus and no MAC? I've not looked at the driver yet, but if the MDIO bus has its own address space, you could consider making it a standalone device. Somebody including two or more LiteETH blocks could then have one shared MDIO bus. That is a supported Linux architecture. > + > + interrupts: > + maxItems: 1 > + > + rx-fifo-depth: > + description: Receive FIFO size, in units of 2048 bytes > + > + tx-fifo-depth: > + description: Transmit FIFO size, in units of 2048 bytes > + > + mac-address: > + description: MAC address to use > + > +required: > + - compatible > + - reg > + - interrupts > + > +additionalProperties: false > + > +examples: > + - | > + mac: ethernet@8020000 { > + compatible = "litex,liteeth"; > + reg = <0x8021000 0x100 > + 0x8020800 0x100 > + 0x8030000 0x2000>; > + rx-fifo-depth = <2>; > + tx-fifo-depth = <2>; > + interrupts = <0x11 0x1>; > + }; You would normally expect to see some MDIO properties here, a link to the standard MDIO yaml, etc. Andrew
On Sat, 7 Aug 2021 at 19:05, Andrew Lunn <andrew@lunn.ch> wrote: > > On Fri, Aug 06, 2021 at 03:19:03PM +0930, Joel Stanley wrote: > > LiteETH is a small footprint and configurable Ethernet core for FPGA > > based system on chips. > > > > Signed-off-by: Joel Stanley <joel@jms.id.au> > > --- > > .../bindings/net/litex,liteeth.yaml | 62 +++++++++++++++++++ > > 1 file changed, 62 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/net/litex,liteeth.yaml > > > > diff --git a/Documentation/devicetree/bindings/net/litex,liteeth.yaml b/Documentation/devicetree/bindings/net/litex,liteeth.yaml > > new file mode 100644 > > index 000000000000..e2a837dbfdaa > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/net/litex,liteeth.yaml > > @@ -0,0 +1,62 @@ > > +# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/net/litex,liteeth.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: LiteX LiteETH ethernet device > > + > > +maintainers: > > + - Joel Stanley <joel@jms.id.au> > > + > > +description: | > > + LiteETH is a small footprint and configurable Ethernet core for FPGA based > > + system on chips. > > + > > + The hardware source is Open Source and can be found on at > > + https://github.com/enjoy-digital/liteeth/. > > + > > +properties: > > + compatible: > > + const: litex,liteeth > > + > > + reg: > > + minItems: 3 > > + items: > > + - description: MAC registers > > + - description: MDIO registers > > + - description: Packet buffer > > Hi Joel > > How configurable is the synthesis? Can the MDIO bus be left out? You > can have only the MDIO bus and no MAC? > > I've not looked at the driver yet, but if the MDIO bus has its own > address space, you could consider making it a standalone > device. Somebody including two or more LiteETH blocks could then have > one shared MDIO bus. That is a supported Linux architecture. It's currently integrated as one device. If you instatined two blocks, you would end up with two mdio controllers, each inside those two liteeth blocks. Obviously being software someone could change that. We've had a few discussions about the infinite possibilities of a soft SoC and what that means for adding driver support to mainline. I think having some basic driver support is useful, particularly as we then get close review as Jakub provided. The liteeth block has seen a lot of use under Linux by risc-v (vexriscv), powerpc (microwatt), and openrisc (mor1k) designs. The microwatt and or1k designs have mainline support, making them easy to test. This driver will support the normal configurations of those platforms. As the soft core project evolves, we can revisit what goes in mainline, how flexible that driver support needs to be, and how best to manage that. > > > + > > + interrupts: > > + maxItems: 1 > > + > > + rx-fifo-depth: > > + description: Receive FIFO size, in units of 2048 bytes > > + > > + tx-fifo-depth: > > + description: Transmit FIFO size, in units of 2048 bytes > > + > > + mac-address: > > + description: MAC address to use > > + > > +required: > > + - compatible > > + - reg > > + - interrupts > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + mac: ethernet@8020000 { > > + compatible = "litex,liteeth"; > > + reg = <0x8021000 0x100 > > + 0x8020800 0x100 > > + 0x8030000 0x2000>; > > + rx-fifo-depth = <2>; > > + tx-fifo-depth = <2>; > > + interrupts = <0x11 0x1>; > > + }; > > You would normally expect to see some MDIO properties here, a link to > the standard MDIO yaml, etc. Do you have a favourite example that I could follow?
> > Hi Joel > > > > How configurable is the synthesis? Can the MDIO bus be left out? You > > can have only the MDIO bus and no MAC? > > > > I've not looked at the driver yet, but if the MDIO bus has its own > > address space, you could consider making it a standalone > > device. Somebody including two or more LiteETH blocks could then have > > one shared MDIO bus. That is a supported Linux architecture. > > It's currently integrated as one device. If you instatined two blocks, > you would end up with two mdio controllers, each inside those two > liteeth blocks. O.K. So at the moment, that is the default architecture, and the driver should then support it. But since there appears to be a clean address space split, the Linux MDIO driver could still be separate. But it might depend on the reset, since the register is in the MDIO address space. So again, we need to understand what that reset is about. > Obviously being software someone could change that. We've had a few > discussions about the infinite possibilities of a soft SoC and what > that means for adding driver support to mainline. Has any thought been given to making the hardware somehow enumerable/self describing? A register containing features which have been synthesised? There could be a bit indicating is the MDIO bus master is present, etc. > As the soft core project evolves, we can revisit what goes in > mainline, how flexible that driver support needs to be, and how best > to manage that. We can do that, but we have to keep backwards compatibility in mind. We cannot break older synthesised IP blobs because a new feature has come along and the driver has changed. It is best to put some thought into that now, how forward/backward compatibility will work. A revision register, a self description register, something which helps the software driver identify what the 'hardware' is. Andrew > > > > > > + > > > + interrupts: > > > + maxItems: 1 > > > + > > > + rx-fifo-depth: > > > + description: Receive FIFO size, in units of 2048 bytes > > > + > > > + tx-fifo-depth: > > > + description: Transmit FIFO size, in units of 2048 bytes > > > + > > > + mac-address: > > > + description: MAC address to use > > > + > > > +required: > > > + - compatible > > > + - reg > > > + - interrupts > > > + > > > +additionalProperties: false > > > + > > > +examples: > > > + - | > > > + mac: ethernet@8020000 { > > > + compatible = "litex,liteeth"; > > > + reg = <0x8021000 0x100 > > > + 0x8020800 0x100 > > > + 0x8030000 0x2000>; > > > + rx-fifo-depth = <2>; > > > + tx-fifo-depth = <2>; > > > + interrupts = <0x11 0x1>; > > > + }; > > > > You would normally expect to see some MDIO properties here, a link to > > the standard MDIO yaml, etc. > > Do you have a favourite example that I could follow? Documentation/devicetree/bindings/net/mdio.yaml describes all the standard properties. Picking a file at random: Documentation/devicetree/bindings/net/socionext,uniphier-ave4.yaml
diff --git a/Documentation/devicetree/bindings/net/litex,liteeth.yaml b/Documentation/devicetree/bindings/net/litex,liteeth.yaml new file mode 100644 index 000000000000..e2a837dbfdaa --- /dev/null +++ b/Documentation/devicetree/bindings/net/litex,liteeth.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/litex,liteeth.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LiteX LiteETH ethernet device + +maintainers: + - Joel Stanley <joel@jms.id.au> + +description: | + LiteETH is a small footprint and configurable Ethernet core for FPGA based + system on chips. + + The hardware source is Open Source and can be found on at + https://github.com/enjoy-digital/liteeth/. + +properties: + compatible: + const: litex,liteeth + + reg: + minItems: 3 + items: + - description: MAC registers + - description: MDIO registers + - description: Packet buffer + + interrupts: + maxItems: 1 + + rx-fifo-depth: + description: Receive FIFO size, in units of 2048 bytes + + tx-fifo-depth: + description: Transmit FIFO size, in units of 2048 bytes + + mac-address: + description: MAC address to use + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + mac: ethernet@8020000 { + compatible = "litex,liteeth"; + reg = <0x8021000 0x100 + 0x8020800 0x100 + 0x8030000 0x2000>; + rx-fifo-depth = <2>; + tx-fifo-depth = <2>; + interrupts = <0x11 0x1>; + }; +... + +# vim: set ts=2 sw=2 sts=2 tw=80 et cc=80 ft=yaml :
LiteETH is a small footprint and configurable Ethernet core for FPGA based system on chips. Signed-off-by: Joel Stanley <joel@jms.id.au> --- .../bindings/net/litex,liteeth.yaml | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/litex,liteeth.yaml -- 2.32.0