| Message ID | 20210717001638.1292554-1-linus.walleij@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [1/2] bus: ixp4xx: Add DT bindings for the IXP4xx expansion bus | expand |
On Sat, 17 Jul 2021 02:16:37 +0200, Linus Walleij wrote: > This adds device tree bindings for the IXP4xx expansion bus controller. > > Cc: Marc Zyngier <maz@kernel.org> > Cc: devicetree@vger.kernel.org > Signed-off-by: Linus Walleij <linus.walleij@linaro.org> > --- > ...intel,ixp4xx-expansion-bus-controller.yaml | 151 ++++++++++++++++++ > 1 file changed, 151 insertions(+) > create mode 100644 Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.example.dt.yaml: serial@1,0: compatible: 'oneOf' conditional failed, one must be fixed: ['exar,xr16l2551', 'ns8250'] is too long Additional items are not allowed ('ns8250' was unexpected) ['exar,xr16l2551', 'ns8250'] is too short 'ns8250' was expected 'ns16450' was expected 'ns16550' was expected 'ns16550a' was expected 'ns16850' was expected 'aspeed,ast2400-vuart' was expected 'aspeed,ast2500-vuart' was expected 'intel,xscale-uart' was expected 'mrvl,pxa-uart' was expected 'nuvoton,wpcm450-uart' was expected 'nuvoton,npcm750-uart' was expected 'nvidia,tegra20-uart' was expected 'nxp,lpc3220-uart' was expected 'exar,xr16l2551' is not one of ['altr,16550-FIFO32', 'altr,16550-FIFO64', 'altr,16550-FIFO128', 'fsl,16550-FIFO64', 'fsl,ns16550', 'andestech,uart16550', 'nxp,lpc1850-uart', 'opencores,uart16550-rtlsvn105', 'ti,da830-uart'] 'exar,xr16l2551' is not one of ['ns16750', 'cavium,octeon-3860-uart', 'xlnx,xps-uart16550-2.00.b', 'ralink,rt2880-uart'] 'exar,xr16l2551' is not one of ['ralink,mt7620a-uart', 'ralink,rt3052-uart', 'ralink,rt3883-uart'] 'exar,xr16l2551' is not one of ['mediatek,mt7622-btif', 'mediatek,mt7623-btif'] 'mrvl,mmp-uart' was expected 'exar,xr16l2551' is not one of ['nvidia,tegra30-uart', 'nvidia,tegra114-uart', 'nvidia,tegra124-uart', 'nvidia,tegra186-uart', 'nvidia,tegra194-uart', 'nvidia,tegra210-uart'] 'ns8250' is not one of ['ns16550', 'ns16550a'] 'ralink,rt2880-uart' was expected 'mediatek,mtk-btif' was expected From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/serial/8250.yaml Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.example.dt.yaml:0:0: /example-0/bus@50000000/serial@1,0: failed to match any schema with compatible: ['exar,xr16l2551', 'ns8250'] \ndoc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/1506323 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
On Mon, Jul 19, 2021 at 3:47 PM Rob Herring <robh@kernel.org> wrote: > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.example.dt.yaml: serial@1,0: compatible: 'oneOf' conditional failed, one must be fixed: > ['exar,xr16l2551', 'ns8250'] is too long > Additional items are not allowed ('ns8250' was unexpected) > ['exar,xr16l2551', 'ns8250'] is too short This is because the patch adding these compatibles was sent separately so it can be merged into the tty subsystem. So pretty much false alarm, but the bot can't know everything. Yours, Linus Walleij
On Sat, Jul 17, 2021 at 02:16:37AM +0200, Linus Walleij wrote: > This adds device tree bindings for the IXP4xx expansion bus controller. > > Cc: Marc Zyngier <maz@kernel.org> > Cc: devicetree@vger.kernel.org > Signed-off-by: Linus Walleij <linus.walleij@linaro.org> > --- > ...intel,ixp4xx-expansion-bus-controller.yaml | 151 ++++++++++++++++++ > 1 file changed, 151 insertions(+) > create mode 100644 Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml > > diff --git a/Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml b/Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml > new file mode 100644 > index 000000000000..0875b653c35c > --- /dev/null > +++ b/Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml > @@ -0,0 +1,151 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/bus/intel,ixp4xx-expansion-bus-controller.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Intel IXP4xx Expansion Bus Controller > + > +description: | > + The IXP4xx expansion bus controller handles access to devices on the > + memory-mapped expansion bus on the Intel IXP4xx family of system on chips, > + including IXP42x, IXP43x, IXP45x and IXP46x. > + > +maintainers: > + - Linus Walleij <linus.walleij@linaro.org> > + > +properties: > + $nodename: > + pattern: '^bus@[0-9a-f]+$' > + > + compatible: > + enum: > + - intel,ixp42x-expansion-bus-controller > + - intel,ixp43x-expansion-bus-controller > + - intel,ixp45x-expansion-bus-controller > + - intel,ixp46x-expansion-bus-controller > + > + reg: > + description: Control registers for the expansion bus, these are not > + inside the memory range handled by the expansion bus. > + maxItems: 1 > + > + "#address-cells": > + description: | > + The first cell is the chip select numer. > + The second cell is the address offset within the bank. > + const: 2 > + > + "#size-cells": > + const: 1 > + > + ranges: true > + dma-ranges: true > + > +patternProperties: > + "^.*@[0-7],[0-9a-f]+$": > + description: Devices attached to chip selects are represented as > + subnodes. > + type: object > + > + properties: > + intel,ixp4xx-eb-t1: > + description: Address timing, extend address phase with n cycles. > + $ref: /schemas/types.yaml#/definitions/uint32 > + maximum: 3 > + > + intel,ixp4xx-eb-t2: > + description: Setup chip select timing, extend setup phase with n cycles. > + $ref: /schemas/types.yaml#/definitions/uint32 > + maximum: 3 > + > + intel,ixp4xx-eb-t3: > + description: Strobe timing, extend strobe phase with n cycles. > + $ref: /schemas/types.yaml#/definitions/uint32 > + maximum: 15 > + > + intel,ixp4xx-eb-t4: > + description: Hold timing, extend hold phase with n cycles. > + $ref: /schemas/types.yaml#/definitions/uint32 > + maximum: 3 > + > + intel,ixp4xx-eb-t5: > + description: Recovery timing, extend recovery phase with n cycles. > + $ref: /schemas/types.yaml#/definitions/uint32 > + maximum: 15 > + > + intel,ixp4xx-eb-cycle-type: > + description: The type of cycles to use on the expansion bus for this > + chip select. 0 = Intel cycles, 1 = Motorola cycles, 2 = HPI cycles. > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [0, 1, 2] > + > + intel,ixp4xx-eb-byte-access-on-halfword: > + description: Allow byte read access on half word devices. > + $ref: /schemas/types.yaml#/definitions/flag > + > + intel,ixp4xx-eb-hpi-hrdy-pol-high: > + description: Set HPI HRDY polarity to active high when using HPI. > + $ref: /schemas/types.yaml#/definitions/flag > + > + intel,ixp4xx-eb-mux-address-and-data: > + description: Multiplex address and data on the data bus. > + $ref: /schemas/types.yaml#/definitions/flag > + > + intel,ixp4xx-eb-ahb-split-transfers: > + description: Enable AHB split transfers. > + $ref: /schemas/types.yaml#/definitions/flag > + > + intel,ixp4xx-eb-write-enable: > + description: Enable write cycles. > + $ref: /schemas/types.yaml#/definitions/flag > + > + intel,ixp4xx-eb-byte-access: > + description: Expansion bus uses only 8 bits. The default is to use > + 16 bits. > + $ref: /schemas/types.yaml#/definitions/flag > + > + unevaluatedProperties: false This will cause failures when implemented. The problem is this won't allow any other child node properties as this schema and the device schema are evaluated independently. The only way I see to solve this is the child node schemas have to include some 'bus properties' schema which includes all possible bus controller properties. There's been a recent patch set doing this for SPI. At least here, I think the number of different child devices on parallel expansion buses are limited. So spliting this to 2 schema files would be the first step. Minimally, just drop unevaluatedProperties. > + > +required: > + - compatible > + - reg > + - "#address-cells" > + - "#size-cells" > + - ranges > + - dma-ranges > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/irq.h> > + bus@50000000 { > + compatible = "intel,ixp42x-expansion-bus-controller"; > + reg = <0xc4000000 0x28>; > + #address-cells = <2>; > + #size-cells = <1>; > + ranges = <0 0x0 0x50000000 0x01000000>, > + <1 0x0 0x51000000 0x01000000>; > + dma-ranges = <0 0x0 0x50000000 0x01000000>, > + <1 0x0 0x51000000 0x01000000>; > + flash@0,0 { > + compatible = "intel,ixp4xx-flash", "cfi-flash"; > + bank-width = <2>; > + reg = <0 0x00000000 0x1000000>; > + intel,ixp4xx-eb-t3 = <3>; > + intel,ixp4xx-eb-byte-access-on-halfword; > + intel,ixp4xx-eb-write-enable; > + }; > + serial@1,0 { > + compatible = "exar,xr16l2551", "ns8250"; > + reg = <1 0x00000000 0x10>; > + interrupt-parent = <&gpio0>; > + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; > + clock-frequency = <1843200>; > + intel,ixp4xx-eb-t3 = <3>; > + intel,ixp4xx-eb-cycle-type = <1>; > + intel,ixp4xx-eb-write-enable; > + intel,ixp4xx-eb-byte-access; > + }; > + }; > -- > 2.31.1 > >
On Mon, Jul 19, 2021 at 5:18 PM Rob Herring <robh@kernel.org> wrote: > > +patternProperties: > > + "^.*@[0-7],[0-9a-f]+$": > > + description: Devices attached to chip selects are represented as > > + subnodes. > > + type: object > > + > > + properties: > > + intel,ixp4xx-eb-t1: > > + description: Address timing, extend address phase with n cycles. > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + maximum: 3 (...) > > + unevaluatedProperties: false > > This will cause failures when implemented. The problem is this won't > allow any other child node properties as this schema and the device > schema are evaluated independently. The only way I see to solve this is > the child node schemas have to include some 'bus properties' schema > which includes all possible bus controller properties. There's been a > recent patch set doing this for SPI. At least here, I think the number > of different child devices on parallel expansion buses are limited. > > So spliting this to 2 schema files would be the first step. Minimally, > just drop unevaluatedProperties. SPI upstream simply uses additionalProperties: true is that acceptable for now? Yours, Linus Walleij
On Mon, Jul 19, 2021 at 4:49 PM Linus Walleij <linus.walleij@linaro.org> wrote: > > On Mon, Jul 19, 2021 at 5:18 PM Rob Herring <robh@kernel.org> wrote: > > > > +patternProperties: > > > + "^.*@[0-7],[0-9a-f]+$": > > > + description: Devices attached to chip selects are represented as > > > + subnodes. > > > + type: object > > > + > > > + properties: > > > + intel,ixp4xx-eb-t1: > > > + description: Address timing, extend address phase with n cycles. > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > > + maximum: 3 > > (...) > > > > + unevaluatedProperties: false > > > > This will cause failures when implemented. The problem is this won't > > allow any other child node properties as this schema and the device > > schema are evaluated independently. The only way I see to solve this is > > the child node schemas have to include some 'bus properties' schema > > which includes all possible bus controller properties. There's been a > > recent patch set doing this for SPI. At least here, I think the number > > of different child devices on parallel expansion buses are limited. > > > > So spliting this to 2 schema files would be the first step. Minimally, > > just drop unevaluatedProperties. > > SPI upstream simply uses > > additionalProperties: true > > is that acceptable for now? Yes. (That is the default) Rob
diff --git a/Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml b/Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml new file mode 100644 index 000000000000..0875b653c35c --- /dev/null +++ b/Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml @@ -0,0 +1,151 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/intel,ixp4xx-expansion-bus-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel IXP4xx Expansion Bus Controller + +description: | + The IXP4xx expansion bus controller handles access to devices on the + memory-mapped expansion bus on the Intel IXP4xx family of system on chips, + including IXP42x, IXP43x, IXP45x and IXP46x. + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +properties: + $nodename: + pattern: '^bus@[0-9a-f]+$' + + compatible: + enum: + - intel,ixp42x-expansion-bus-controller + - intel,ixp43x-expansion-bus-controller + - intel,ixp45x-expansion-bus-controller + - intel,ixp46x-expansion-bus-controller + + reg: + description: Control registers for the expansion bus, these are not + inside the memory range handled by the expansion bus. + maxItems: 1 + + "#address-cells": + description: | + The first cell is the chip select numer. + The second cell is the address offset within the bank. + const: 2 + + "#size-cells": + const: 1 + + ranges: true + dma-ranges: true + +patternProperties: + "^.*@[0-7],[0-9a-f]+$": + description: Devices attached to chip selects are represented as + subnodes. + type: object + + properties: + intel,ixp4xx-eb-t1: + description: Address timing, extend address phase with n cycles. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 3 + + intel,ixp4xx-eb-t2: + description: Setup chip select timing, extend setup phase with n cycles. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 3 + + intel,ixp4xx-eb-t3: + description: Strobe timing, extend strobe phase with n cycles. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + + intel,ixp4xx-eb-t4: + description: Hold timing, extend hold phase with n cycles. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 3 + + intel,ixp4xx-eb-t5: + description: Recovery timing, extend recovery phase with n cycles. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + + intel,ixp4xx-eb-cycle-type: + description: The type of cycles to use on the expansion bus for this + chip select. 0 = Intel cycles, 1 = Motorola cycles, 2 = HPI cycles. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + + intel,ixp4xx-eb-byte-access-on-halfword: + description: Allow byte read access on half word devices. + $ref: /schemas/types.yaml#/definitions/flag + + intel,ixp4xx-eb-hpi-hrdy-pol-high: + description: Set HPI HRDY polarity to active high when using HPI. + $ref: /schemas/types.yaml#/definitions/flag + + intel,ixp4xx-eb-mux-address-and-data: + description: Multiplex address and data on the data bus. + $ref: /schemas/types.yaml#/definitions/flag + + intel,ixp4xx-eb-ahb-split-transfers: + description: Enable AHB split transfers. + $ref: /schemas/types.yaml#/definitions/flag + + intel,ixp4xx-eb-write-enable: + description: Enable write cycles. + $ref: /schemas/types.yaml#/definitions/flag + + intel,ixp4xx-eb-byte-access: + description: Expansion bus uses only 8 bits. The default is to use + 16 bits. + $ref: /schemas/types.yaml#/definitions/flag + + unevaluatedProperties: false + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + - dma-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + bus@50000000 { + compatible = "intel,ixp42x-expansion-bus-controller"; + reg = <0xc4000000 0x28>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0x0 0x50000000 0x01000000>, + <1 0x0 0x51000000 0x01000000>; + dma-ranges = <0 0x0 0x50000000 0x01000000>, + <1 0x0 0x51000000 0x01000000>; + flash@0,0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + reg = <0 0x00000000 0x1000000>; + intel,ixp4xx-eb-t3 = <3>; + intel,ixp4xx-eb-byte-access-on-halfword; + intel,ixp4xx-eb-write-enable; + }; + serial@1,0 { + compatible = "exar,xr16l2551", "ns8250"; + reg = <1 0x00000000 0x10>; + interrupt-parent = <&gpio0>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + clock-frequency = <1843200>; + intel,ixp4xx-eb-t3 = <3>; + intel,ixp4xx-eb-cycle-type = <1>; + intel,ixp4xx-eb-write-enable; + intel,ixp4xx-eb-byte-access; + }; + };
This adds device tree bindings for the IXP4xx expansion bus controller. Cc: Marc Zyngier <maz@kernel.org> Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org> --- ...intel,ixp4xx-expansion-bus-controller.yaml | 151 ++++++++++++++++++ 1 file changed, 151 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml -- 2.31.1