diff mbox series

[05/17] target/riscv: Use gpr_{src, dst} and tcg_constant_tl in gen_grevi

Message ID 20210709042608.883256-6-richard.henderson@linaro.org
State New
Headers show
Series target/riscv: Use tcg_constant_* | expand

Commit Message

Richard Henderson July 9, 2021, 4:25 a.m. UTC 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/riscv/translate.c | 17 +++++------------
 1 file changed, 5 insertions(+), 12 deletions(-)

-- 
2.25.1

Comments

Alistair Francis July 13, 2021, 4:12 a.m. UTC | #1 
On Fri, Jul 9, 2021 at 2:47 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Reviewed-by: Alistair Francis <alistair.francis@wdc.com>


Alistair

> ---

>  target/riscv/translate.c | 17 +++++------------

>  1 file changed, 5 insertions(+), 12 deletions(-)

>

> diff --git a/target/riscv/translate.c b/target/riscv/translate.c

> index 7dedfd548b..6ad40e43b0 100644

> --- a/target/riscv/translate.c

> +++ b/target/riscv/translate.c

> @@ -620,23 +620,16 @@ static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)

>

>  static bool gen_grevi(DisasContext *ctx, arg_grevi *a)

>  {

> -    TCGv source1 = tcg_temp_new();

> -    TCGv source2;

> -

> -    gen_get_gpr(source1, a->rs1);

> +    TCGv dest = gpr_dst(ctx, a->rd);

> +    TCGv src1 = gpr_src(ctx, a->rs1);

>

>      if (a->shamt == (TARGET_LONG_BITS - 8)) {

>          /* rev8, byte swaps */

> -        tcg_gen_bswap_tl(source1, source1);

> +        tcg_gen_bswap_tl(dest, src1);

>      } else {

> -        source2 = tcg_temp_new();

> -        tcg_gen_movi_tl(source2, a->shamt);

> -        gen_helper_grev(source1, source1, source2);

> -        tcg_temp_free(source2);

> +        TCGv src2 = tcg_constant_tl(a->shamt);

> +        gen_helper_grev(dest, src1, src2);

>      }

> -

> -    gen_set_gpr(a->rd, source1);

> -    tcg_temp_free(source1);

>      return true;

>  }

>

> --

> 2.25.1

>

>
diff mbox series

Patch

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 7dedfd548b..6ad40e43b0 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -620,23 +620,16 @@  static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
 
 static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
 {
-    TCGv source1 = tcg_temp_new();
-    TCGv source2;
-
-    gen_get_gpr(source1, a->rs1);
+    TCGv dest = gpr_dst(ctx, a->rd);
+    TCGv src1 = gpr_src(ctx, a->rs1);
 
     if (a->shamt == (TARGET_LONG_BITS - 8)) {
         /* rev8, byte swaps */
-        tcg_gen_bswap_tl(source1, source1);
+        tcg_gen_bswap_tl(dest, src1);
     } else {
-        source2 = tcg_temp_new();
-        tcg_gen_movi_tl(source2, a->shamt);
-        gen_helper_grev(source1, source1, source2);
-        tcg_temp_free(source2);
+        TCGv src2 = tcg_constant_tl(a->shamt);
+        gen_helper_grev(dest, src1, src2);
     }
-
-    gen_set_gpr(a->rd, source1);
-    tcg_temp_free(source1);
     return true;
 }