diff mbox series

[3/4] target/openrisc: Cache constant 0 in DisasContext

Message ID 20210708213754.830485-4-richard.henderson@linaro.org
State New
Headers show
Series target/openrisc: Use tcg_constant_* | expand

Commit Message

Richard Henderson July 8, 2021, 9:37 p.m. UTC 
We are virtually certain to have fetched constant 0 once, at the
beginning of the TB, so we might as well use it elsewhere.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/openrisc/translate.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

-- 
2.25.1

Comments

Philippe Mathieu-Daudé July 9, 2021, 4:22 p.m. UTC | #1 
On 7/8/21 11:37 PM, Richard Henderson wrote:
> We are virtually certain to have fetched constant 0 once, at the

> beginning of the TB, so we might as well use it elsewhere.

> 

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>  target/openrisc/translate.c | 12 ++++++------

>  1 file changed, 6 insertions(+), 6 deletions(-)


Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Stafford Horne July 9, 2021, 8:58 p.m. UTC | #2 
On Thu, Jul 08, 2021 at 02:37:53PM -0700, Richard Henderson wrote:
> We are virtually certain to have fetched constant 0 once, at the

> beginning of the TB, so we might as well use it elsewhere.

> 

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Reviewed-by: Stafford Horne <shorne@gmail.com>
diff mbox series

Patch

diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 96df513fd3..3d86bdffaa 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -53,6 +53,8 @@  typedef struct DisasContext {
 
     /* The temporary corresponding to register 0 for this compilation.  */
     TCGv R0;
+    /* The constant zero. */
+    TCGv zero;
 } DisasContext;
 
 static inline bool is_user(DisasContext *dc)
@@ -537,10 +539,8 @@  static bool trans_l_extbz(DisasContext *dc, arg_da *a)
 
 static bool trans_l_cmov(DisasContext *dc, arg_dab *a)
 {
-    TCGv zero = tcg_constant_tl(0);
-
     check_r0_write(dc, a->d);
-    tcg_gen_movcond_tl(TCG_COND_NE, cpu_R(dc, a->d), cpu_sr_f, zero,
+    tcg_gen_movcond_tl(TCG_COND_NE, cpu_R(dc, a->d), cpu_sr_f, dc->zero,
                        cpu_R(dc, a->a), cpu_R(dc, a->b));
     return true;
 }
@@ -631,9 +631,8 @@  static void do_bf(DisasContext *dc, arg_l_bf *a, TCGCond cond)
     target_ulong tmp_pc = dc->base.pc_next + a->n * 4;
     TCGv t_next = tcg_constant_tl(dc->base.pc_next + 8);
     TCGv t_true = tcg_constant_tl(tmp_pc);
-    TCGv t_zero = tcg_constant_tl(0);
 
-    tcg_gen_movcond_tl(cond, jmp_pc, cpu_sr_f, t_zero, t_true, t_next);
+    tcg_gen_movcond_tl(cond, jmp_pc, cpu_sr_f, dc->zero, t_true, t_next);
     dc->delayed_branch = 2;
 }
 
@@ -1595,8 +1594,9 @@  static void openrisc_tr_tb_start(DisasContextBase *db, CPUState *cs)
 
     /* Allow the TCG optimizer to see that R0 == 0,
        when it's true, which is the common case.  */
+    dc->zero = tcg_constant_tl(0);
     if (dc->tb_flags & TB_FLAGS_R0_0) {
-        dc->R0 = tcg_constant_tl(0);
+        dc->R0 = dc->zero;
     } else {
         dc->R0 = cpu_regs[0];
     }