| Message ID | 20210701232728.23591-1-digetx@gmail.com |
|---|---|
| Headers | show |
| Series | NVIDIA Tegra power management patches for 5.15 | expand |
On Fri, 2 Jul 2021 at 01:28, Dmitry Osipenko <digetx@gmail.com> wrote: > > Hello, > > This series continues the work on enabling voltage scaling of the core > power domain for NVIDIA Tegra SoCs. All the previous grounding work around > improving OPP API and adding the initial core power domain driver is now > landing into 5.14 kernel and already available in linux-next. > > The biggest challenge left so far is the power management of the PLLs > and system clocks which don't have a dedicated hardware unit. I made a lot > of changes around it by going back to a variant where individual device > drivers are responsible for the power management in oppose to a recent > variant where the most of power management was done by the clk controller > driver. This allowed to drop the need of having a special lockdep > annotation for the power domain's mutex, which Ulf Hansson didn't like > previously. We don't have situations of a nested GENPD accesses anymore. > It also allowed to minimize the clk patch a lot. Now clk driver manages > power of the internal clocks only. > > This series enables a full power management for Tegra20 and Tegra30 SoCs. > It doesn't include all the device-tree binding patches. I'll try to split > this series into a smaller parts that could be applied individually. For > now I want to get a feedback at least on the first six patches. > > Example /sys/kernel/debug/pm_genpd/pm_genpd_summary from Tegra20 Acer A500: > > domain status children performance > /device runtime status > ---------------------------------------------------------------------------------------------- > mpe off-0 0 > /devices/soc0/50000000.host1x/54040000.mpe suspended 0 > vdec off-0 0 > /devices/soc0/6001a000.vde suspended 0 > venc off-0 0 > /devices/soc0/50000000.host1x/54080000.vi suspended 0 > /devices/soc0/50000000.host1x/54100000.isp suspended 0 > 3d off-0 0 > /devices/soc0/50000000.host1x/54180000.gr3d suspended 0 > core-domain on 1100000 > 3d, venc, vdec, mpe > /devices/soc0/50000000.host1x active 1100000 > /devices/soc0/50000000.host1x/540c0000.epp suspended 0 > /devices/soc0/50000000.host1x/54140000.gr2d suspended 0 > /devices/soc0/50000000.host1x/54280000.hdmi suspended 0 > /devices/soc0/c5000000.usb active 1100000 > /devices/soc0/c5008000.usb active 1100000 > /devices/soc0/c8000000.mmc active 1000000 > /devices/soc0/c8000400.mmc active 1000000 > /devices/soc0/c8000600.mmc active 1000000 > /devices/soc0/7000f400.memory-controller active 1000000 > /devices/platform/tegra_clk_sclk active 950000 > /devices/soc0/50000000.host1x/54200000.dc active 950000 > /devices/soc0/50000000.host1x/54240000.dc suspended 0 > > > Example /sys/kernel/debug/pm_genpd/pm_genpd_summary from Tegra30 Nexus 7: > > domain status children performance > /device runtime status > ---------------------------------------------------------------------------------------------- > heg on 1000000 > /devices/soc0/50000000.host1x active 1000000 > /devices/soc0/50000000.host1x/540c0000.epp suspended 0 > /devices/soc0/50000000.host1x/54140000.gr2d suspended 0 > mpe off-0 0 > /devices/soc0/50000000.host1x/54040000.mpe suspended 0 > vdec off-0 0 > /devices/soc0/6001a000.vde suspended 0 > venc off-0 0 > /devices/soc0/50000000.host1x/54080000.vi suspended 0 > /devices/soc0/50000000.host1x/54100000.isp suspended 0 > 3d1 off-0 0 > /devices/genpd:1:54180000.gr3d suspended 0 > 3d0 off-0 0 > /devices/genpd:0:54180000.gr3d suspended 0 > core-domain on 1000000 > 3d0, 3d1, venc, vdec, mpe, heg > /devices/soc0/7d000000.usb active 1000000 > /devices/soc0/78000400.mmc active 950000 > /devices/soc0/7000f400.memory-controller active 1000000 > /devices/soc0/7000a000.pwm active 1000000 > /devices/platform/tegra_clk_pll_c active 1000000 > /devices/platform/tegra_clk_pll_e suspended 0 > /devices/platform/tegra_clk_pll_m active 1000000 > /devices/platform/tegra_clk_sclk active 1000000 > /devices/soc0/7000f800.fuse suspended 0 > /devices/soc0/50000000.host1x/54240000.dc suspended 0 > /devices/soc0/50000000.host1x/54200000.dc active 1000000 > > Dmitry Osipenko (37): > soc/tegra: pmc: Temporarily disable PMC state syncing > soc/tegra: pmc: Implement attach_dev() of power domain drivers > soc/tegra: Don't print error message when OPPs not available > soc/tegra: Add devm_tegra_core_dev_init_opp_table_simple() > dt-bindings: clock: tegra-car: Document new tegra-clocks node > clk: tegra: Support runtime PM and power domain > dt-bindings: host1x: Document OPP and power domain properties > dt-bindings: host1x: Document Memory Client resets of Host1x, GR2D and > GR3D > gpu: host1x: Add host1x_channel_stop() > gpu: host1x: Add runtime PM support > gpu: host1x: Add stub driver for MPE, VI, EPP and ISP > drm/tegra: dc: Support OPP and SoC core voltage scaling > drm/tegra: hdmi: Add OPP support > drm/tegra: gr2d: Support OPP and power management > drm/tegra: gr3d: Support OPP and power management > drm/tegra: vic: Stop channel before suspending > usb: chipidea: tegra: Add runtime PM support > bus: tegra-gmi: Add runtime PM support > pwm: tegra: Add runtime PM and OPP support > mmc: sdhci-tegra: Add runtime PM and OPP support > mtd: rawnand: tegra: Add runtime PM support > soc/tegra: fuse: Clear fuse->clk on driver probe failure > soc/tegra: fuse: Add runtime PM support > soc/tegra: fuse: Enable fuse clock on suspend > clk: tegra: Remove CLK_IS_CRITICAL flag from fuse clock > spi: tegra20-slink: Improve runtime PM usage > spi: tegra20-slink: Add OPP support > memory: tegra20-emc: Add minimal runtime PM support > memory: tegra30-emc: Add minimal runtime PM support > media: dt: bindings: tegra-vde: Convert to schema > media: dt: bindings: tegra-vde: Document OPP and power domain > media: staging: tegra-vde: Support generic power domain > ARM: tegra: Add OPP tables and power domains to Tegra20 device-trees > ARM: tegra: Add OPP tables and power domains to Tegra30 device-trees > ARM: tegra: Add Memory Client resets to Tegra20 GR2D, GR3D and Host1x > ARM: tegra: Add Memory Client resets to Tegra30 GR2D, GR3D and Host1x > soc/tegra: pmc: Enable core domain support on Tegra20 and Tegra30 > > .../bindings/clock/nvidia,tegra20-car.yaml | 51 + > .../display/tegra/nvidia,tegra20-host1x.txt | 53 + > .../bindings/media/nvidia,tegra-vde.txt | 64 - > .../bindings/media/nvidia,tegra-vde.yaml | 119 ++ > .../boot/dts/tegra20-acer-a500-picasso.dts | 1 + > arch/arm/boot/dts/tegra20-colibri.dtsi | 3 +- > arch/arm/boot/dts/tegra20-harmony.dts | 3 +- > arch/arm/boot/dts/tegra20-paz00.dts | 1 + > .../arm/boot/dts/tegra20-peripherals-opp.dtsi | 941 +++++++++++ > arch/arm/boot/dts/tegra20-seaboard.dts | 3 +- > arch/arm/boot/dts/tegra20-tamonten.dtsi | 3 +- > arch/arm/boot/dts/tegra20-trimslice.dts | 9 + > arch/arm/boot/dts/tegra20-ventana.dts | 1 + > arch/arm/boot/dts/tegra20.dtsi | 115 +- > .../tegra30-asus-nexus7-grouper-common.dtsi | 1 + > arch/arm/boot/dts/tegra30-beaver.dts | 1 + > arch/arm/boot/dts/tegra30-cardhu.dtsi | 1 + > arch/arm/boot/dts/tegra30-colibri.dtsi | 17 +- > arch/arm/boot/dts/tegra30-ouya.dts | 1 + > .../arm/boot/dts/tegra30-peripherals-opp.dtsi | 1412 +++++++++++++++++ > arch/arm/boot/dts/tegra30.dtsi | 170 +- > drivers/bus/tegra-gmi.c | 44 +- > drivers/clk/tegra/Makefile | 1 + > drivers/clk/tegra/clk-device.c | 222 +++ > drivers/clk/tegra/clk-pll.c | 2 +- > drivers/clk/tegra/clk-super.c | 2 +- > drivers/clk/tegra/clk-tegra-periph.c | 6 +- > drivers/clk/tegra/clk-tegra20.c | 39 +- > drivers/clk/tegra/clk-tegra30.c | 70 +- > drivers/clk/tegra/clk.c | 66 + > drivers/clk/tegra/clk.h | 2 + > drivers/gpu/drm/tegra/dc.c | 69 + > drivers/gpu/drm/tegra/dc.h | 2 + > drivers/gpu/drm/tegra/gr2d.c | 156 +- > drivers/gpu/drm/tegra/gr3d.c | 401 ++++- > drivers/gpu/drm/tegra/hdmi.c | 9 +- > drivers/gpu/drm/tegra/vic.c | 15 + > drivers/gpu/host1x/channel.c | 8 + > drivers/gpu/host1x/debug.c | 15 + > drivers/gpu/host1x/dev.c | 184 ++- > drivers/gpu/host1x/dev.h | 3 +- > drivers/gpu/host1x/hw/channel_hw.c | 44 +- > drivers/gpu/host1x/intr.c | 3 - > drivers/gpu/host1x/syncpt.c | 5 +- > drivers/memory/tegra/tegra20-emc.c | 31 + > drivers/memory/tegra/tegra30-emc.c | 31 + > drivers/mmc/host/sdhci-tegra.c | 81 +- > drivers/mtd/nand/raw/tegra_nand.c | 44 +- > drivers/pwm/pwm-tegra.c | 104 +- > drivers/soc/tegra/common.c | 4 +- > drivers/soc/tegra/fuse/fuse-tegra.c | 62 + > drivers/soc/tegra/fuse/fuse-tegra20.c | 10 +- > drivers/soc/tegra/fuse/fuse-tegra30.c | 10 +- > drivers/soc/tegra/fuse/fuse.h | 2 + > drivers/soc/tegra/pmc.c | 164 ++ > drivers/spi/spi-tegra20-slink.c | 76 +- > drivers/staging/media/tegra-vde/vde.c | 59 +- > drivers/usb/chipidea/ci_hdrc_tegra.c | 50 +- > include/linux/host1x.h | 1 + > include/soc/tegra/common.h | 13 + > 60 files changed, 4710 insertions(+), 370 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt > create mode 100644 Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml > create mode 100644 drivers/clk/tegra/clk-device.c > Dmitry, I am happy to help to review this, but unfortunately(?) I am moving into holiday mode for a couple of weeks, very soon. I will do my best to move forward with the review, but please be patient. Kind regards Uffe
09.07.2021 16:01, Ulf Hansson пишет: ... > > Dmitry, I am happy to help to review this, but unfortunately(?) I am > moving into holiday mode for a couple of weeks, very soon. I will do > my best to move forward with the review, but please be patient. Thank you for letting me know, have a good holidays!
02.07.2021 02:26, Dmitry Osipenko пишет: > Disable PMC state syncing in order to ensure that we won't break older > kernels once device-trees will be updated with the addition of the power > domains. Previously this was unnecessary because the plan was to make clk > device that will attach to the domain for each clock, but the plan changed > and now we're going make a better GENPD implementation that will require > to update each device driver with the runtime PM and OPP support before > we could safely enable the state syncing. > > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- > drivers/soc/tegra/pmc.c | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c > index ea62f84d1c8b..f63dfb2ca3f9 100644 > --- a/drivers/soc/tegra/pmc.c > +++ b/drivers/soc/tegra/pmc.c > @@ -360,6 +360,7 @@ struct tegra_pmc_soc { > unsigned int num_pmc_clks; > bool has_blink_output; > bool has_usb_sleepwalk; > + bool supports_core_domain; > }; > > /** > @@ -3029,6 +3030,7 @@ static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, > } > > static const struct tegra_pmc_soc tegra20_pmc_soc = { > + .supports_core_domain = false, > .num_powergates = ARRAY_SIZE(tegra20_powergates), > .powergates = tegra20_powergates, > .num_cpu_powergates = 0, > @@ -3089,6 +3091,7 @@ static const char * const tegra30_reset_sources[] = { > }; > > static const struct tegra_pmc_soc tegra30_pmc_soc = { > + .supports_core_domain = false, > .num_powergates = ARRAY_SIZE(tegra30_powergates), > .powergates = tegra30_powergates, > .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), > @@ -3145,6 +3148,7 @@ static const u8 tegra114_cpu_powergates[] = { > }; > > static const struct tegra_pmc_soc tegra114_pmc_soc = { > + .supports_core_domain = false, > .num_powergates = ARRAY_SIZE(tegra114_powergates), > .powergates = tegra114_powergates, > .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), > @@ -3261,6 +3265,7 @@ static const struct pinctrl_pin_desc tegra124_pin_descs[] = { > }; > > static const struct tegra_pmc_soc tegra124_pmc_soc = { > + .supports_core_domain = false, > .num_powergates = ARRAY_SIZE(tegra124_powergates), > .powergates = tegra124_powergates, > .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), > @@ -3386,6 +3391,7 @@ static const struct tegra_wake_event tegra210_wake_events[] = { > }; > > static const struct tegra_pmc_soc tegra210_pmc_soc = { > + .supports_core_domain = false, > .num_powergates = ARRAY_SIZE(tegra210_powergates), > .powergates = tegra210_powergates, > .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates), > @@ -3543,6 +3549,7 @@ static const struct tegra_wake_event tegra186_wake_events[] = { > }; > > static const struct tegra_pmc_soc tegra186_pmc_soc = { > + .supports_core_domain = false, > .num_powergates = 0, > .powergates = NULL, > .num_cpu_powergates = 0, > @@ -3677,6 +3684,7 @@ static const struct tegra_wake_event tegra194_wake_events[] = { > }; > > static const struct tegra_pmc_soc tegra194_pmc_soc = { > + .supports_core_domain = false, > .num_powergates = 0, > .powergates = NULL, > .num_cpu_powergates = 0, > @@ -3745,6 +3753,7 @@ static const char * const tegra234_reset_sources[] = { > }; > > static const struct tegra_pmc_soc tegra234_pmc_soc = { > + .supports_core_domain = false, > .num_powergates = 0, > .powergates = NULL, > .num_cpu_powergates = 0, > @@ -3791,6 +3800,14 @@ static void tegra_pmc_sync_state(struct device *dev) > { > int err; > > + /* > + * Newer device-trees have power domains, but we need to prepare all > + * device drivers with runtime PM and OPP support first, otherwise > + * state syncing is unsafe. > + */ > + if (!pmc->soc->supports_core_domain) > + return; > + > /* > * Older device-trees don't have core PD, and thus, there are > * no dependencies that will block the state syncing. We shouldn't > Thierry, could you please take this patch for 5.15? It should ease further applying of the rest of the patches, thanks.
Hello, This series continues the work on enabling voltage scaling of the core power domain for NVIDIA Tegra SoCs. All the previous grounding work around improving OPP API and adding the initial core power domain driver is now landing into 5.14 kernel and already available in linux-next. The biggest challenge left so far is the power management of the PLLs and system clocks which don't have a dedicated hardware unit. I made a lot of changes around it by going back to a variant where individual device drivers are responsible for the power management in oppose to a recent variant where the most of power management was done by the clk controller driver. This allowed to drop the need of having a special lockdep annotation for the power domain's mutex, which Ulf Hansson didn't like previously. We don't have situations of a nested GENPD accesses anymore. It also allowed to minimize the clk patch a lot. Now clk driver manages power of the internal clocks only. This series enables a full power management for Tegra20 and Tegra30 SoCs. It doesn't include all the device-tree binding patches. I'll try to split this series into a smaller parts that could be applied individually. For now I want to get a feedback at least on the first six patches. Example /sys/kernel/debug/pm_genpd/pm_genpd_summary from Tegra20 Acer A500: domain status children performance /device runtime status ---------------------------------------------------------------------------------------------- mpe off-0 0 /devices/soc0/50000000.host1x/54040000.mpe suspended 0 vdec off-0 0 /devices/soc0/6001a000.vde suspended 0 venc off-0 0 /devices/soc0/50000000.host1x/54080000.vi suspended 0 /devices/soc0/50000000.host1x/54100000.isp suspended 0 3d off-0 0 /devices/soc0/50000000.host1x/54180000.gr3d suspended 0 core-domain on 1100000 3d, venc, vdec, mpe /devices/soc0/50000000.host1x active 1100000 /devices/soc0/50000000.host1x/540c0000.epp suspended 0 /devices/soc0/50000000.host1x/54140000.gr2d suspended 0 /devices/soc0/50000000.host1x/54280000.hdmi suspended 0 /devices/soc0/c5000000.usb active 1100000 /devices/soc0/c5008000.usb active 1100000 /devices/soc0/c8000000.mmc active 1000000 /devices/soc0/c8000400.mmc active 1000000 /devices/soc0/c8000600.mmc active 1000000 /devices/soc0/7000f400.memory-controller active 1000000 /devices/platform/tegra_clk_sclk active 950000 /devices/soc0/50000000.host1x/54200000.dc active 950000 /devices/soc0/50000000.host1x/54240000.dc suspended 0 Example /sys/kernel/debug/pm_genpd/pm_genpd_summary from Tegra30 Nexus 7: domain status children performance /device runtime status ---------------------------------------------------------------------------------------------- heg on 1000000 /devices/soc0/50000000.host1x active 1000000 /devices/soc0/50000000.host1x/540c0000.epp suspended 0 /devices/soc0/50000000.host1x/54140000.gr2d suspended 0 mpe off-0 0 /devices/soc0/50000000.host1x/54040000.mpe suspended 0 vdec off-0 0 /devices/soc0/6001a000.vde suspended 0 venc off-0 0 /devices/soc0/50000000.host1x/54080000.vi suspended 0 /devices/soc0/50000000.host1x/54100000.isp suspended 0 3d1 off-0 0 /devices/genpd:1:54180000.gr3d suspended 0 3d0 off-0 0 /devices/genpd:0:54180000.gr3d suspended 0 core-domain on 1000000 3d0, 3d1, venc, vdec, mpe, heg /devices/soc0/7d000000.usb active 1000000 /devices/soc0/78000400.mmc active 950000 /devices/soc0/7000f400.memory-controller active 1000000 /devices/soc0/7000a000.pwm active 1000000 /devices/platform/tegra_clk_pll_c active 1000000 /devices/platform/tegra_clk_pll_e suspended 0 /devices/platform/tegra_clk_pll_m active 1000000 /devices/platform/tegra_clk_sclk active 1000000 /devices/soc0/7000f800.fuse suspended 0 /devices/soc0/50000000.host1x/54240000.dc suspended 0 /devices/soc0/50000000.host1x/54200000.dc active 1000000 Dmitry Osipenko (37): soc/tegra: pmc: Temporarily disable PMC state syncing soc/tegra: pmc: Implement attach_dev() of power domain drivers soc/tegra: Don't print error message when OPPs not available soc/tegra: Add devm_tegra_core_dev_init_opp_table_simple() dt-bindings: clock: tegra-car: Document new tegra-clocks node clk: tegra: Support runtime PM and power domain dt-bindings: host1x: Document OPP and power domain properties dt-bindings: host1x: Document Memory Client resets of Host1x, GR2D and GR3D gpu: host1x: Add host1x_channel_stop() gpu: host1x: Add runtime PM support gpu: host1x: Add stub driver for MPE, VI, EPP and ISP drm/tegra: dc: Support OPP and SoC core voltage scaling drm/tegra: hdmi: Add OPP support drm/tegra: gr2d: Support OPP and power management drm/tegra: gr3d: Support OPP and power management drm/tegra: vic: Stop channel before suspending usb: chipidea: tegra: Add runtime PM support bus: tegra-gmi: Add runtime PM support pwm: tegra: Add runtime PM and OPP support mmc: sdhci-tegra: Add runtime PM and OPP support mtd: rawnand: tegra: Add runtime PM support soc/tegra: fuse: Clear fuse->clk on driver probe failure soc/tegra: fuse: Add runtime PM support soc/tegra: fuse: Enable fuse clock on suspend clk: tegra: Remove CLK_IS_CRITICAL flag from fuse clock spi: tegra20-slink: Improve runtime PM usage spi: tegra20-slink: Add OPP support memory: tegra20-emc: Add minimal runtime PM support memory: tegra30-emc: Add minimal runtime PM support media: dt: bindings: tegra-vde: Convert to schema media: dt: bindings: tegra-vde: Document OPP and power domain media: staging: tegra-vde: Support generic power domain ARM: tegra: Add OPP tables and power domains to Tegra20 device-trees ARM: tegra: Add OPP tables and power domains to Tegra30 device-trees ARM: tegra: Add Memory Client resets to Tegra20 GR2D, GR3D and Host1x ARM: tegra: Add Memory Client resets to Tegra30 GR2D, GR3D and Host1x soc/tegra: pmc: Enable core domain support on Tegra20 and Tegra30 .../bindings/clock/nvidia,tegra20-car.yaml | 51 + .../display/tegra/nvidia,tegra20-host1x.txt | 53 + .../bindings/media/nvidia,tegra-vde.txt | 64 - .../bindings/media/nvidia,tegra-vde.yaml | 119 ++ .../boot/dts/tegra20-acer-a500-picasso.dts | 1 + arch/arm/boot/dts/tegra20-colibri.dtsi | 3 +- arch/arm/boot/dts/tegra20-harmony.dts | 3 +- arch/arm/boot/dts/tegra20-paz00.dts | 1 + .../arm/boot/dts/tegra20-peripherals-opp.dtsi | 941 +++++++++++ arch/arm/boot/dts/tegra20-seaboard.dts | 3 +- arch/arm/boot/dts/tegra20-tamonten.dtsi | 3 +- arch/arm/boot/dts/tegra20-trimslice.dts | 9 + arch/arm/boot/dts/tegra20-ventana.dts | 1 + arch/arm/boot/dts/tegra20.dtsi | 115 +- .../tegra30-asus-nexus7-grouper-common.dtsi | 1 + arch/arm/boot/dts/tegra30-beaver.dts | 1 + arch/arm/boot/dts/tegra30-cardhu.dtsi | 1 + arch/arm/boot/dts/tegra30-colibri.dtsi | 17 +- arch/arm/boot/dts/tegra30-ouya.dts | 1 + .../arm/boot/dts/tegra30-peripherals-opp.dtsi | 1412 +++++++++++++++++ arch/arm/boot/dts/tegra30.dtsi | 170 +- drivers/bus/tegra-gmi.c | 44 +- drivers/clk/tegra/Makefile | 1 + drivers/clk/tegra/clk-device.c | 222 +++ drivers/clk/tegra/clk-pll.c | 2 +- drivers/clk/tegra/clk-super.c | 2 +- drivers/clk/tegra/clk-tegra-periph.c | 6 +- drivers/clk/tegra/clk-tegra20.c | 39 +- drivers/clk/tegra/clk-tegra30.c | 70 +- drivers/clk/tegra/clk.c | 66 + drivers/clk/tegra/clk.h | 2 + drivers/gpu/drm/tegra/dc.c | 69 + drivers/gpu/drm/tegra/dc.h | 2 + drivers/gpu/drm/tegra/gr2d.c | 156 +- drivers/gpu/drm/tegra/gr3d.c | 401 ++++- drivers/gpu/drm/tegra/hdmi.c | 9 +- drivers/gpu/drm/tegra/vic.c | 15 + drivers/gpu/host1x/channel.c | 8 + drivers/gpu/host1x/debug.c | 15 + drivers/gpu/host1x/dev.c | 184 ++- drivers/gpu/host1x/dev.h | 3 +- drivers/gpu/host1x/hw/channel_hw.c | 44 +- drivers/gpu/host1x/intr.c | 3 - drivers/gpu/host1x/syncpt.c | 5 +- drivers/memory/tegra/tegra20-emc.c | 31 + drivers/memory/tegra/tegra30-emc.c | 31 + drivers/mmc/host/sdhci-tegra.c | 81 +- drivers/mtd/nand/raw/tegra_nand.c | 44 +- drivers/pwm/pwm-tegra.c | 104 +- drivers/soc/tegra/common.c | 4 +- drivers/soc/tegra/fuse/fuse-tegra.c | 62 + drivers/soc/tegra/fuse/fuse-tegra20.c | 10 +- drivers/soc/tegra/fuse/fuse-tegra30.c | 10 +- drivers/soc/tegra/fuse/fuse.h | 2 + drivers/soc/tegra/pmc.c | 164 ++ drivers/spi/spi-tegra20-slink.c | 76 +- drivers/staging/media/tegra-vde/vde.c | 59 +- drivers/usb/chipidea/ci_hdrc_tegra.c | 50 +- include/linux/host1x.h | 1 + include/soc/tegra/common.h | 13 + 60 files changed, 4710 insertions(+), 370 deletions(-) delete mode 100644 Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt create mode 100644 Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml create mode 100644 drivers/clk/tegra/clk-device.c