| Message ID | 20210607061041.2654568-1-ping.bai@nxp.com |
|---|---|
| State | Accepted |
| Commit | 41af189bb38b2692ab5398222f54568719729198 |
| Headers | show |
| Series | [v2,1/2] dt-bindings: pinctrl: imx8ulp: Add pinctrl binding | expand |
> From: Jacky Bai <ping.bai@nxp.com> > Sent: Monday, June 7, 2021 2:11 PM > Subject: [PATCH v2 2/2] pinctrl: imx8ulp: Add pinctrl driver support > > From: Anson Huang <Anson.Huang@nxp.com> > > Add i.MX8ULP pinctrl driver support. > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Regards Aisheng
> From: Jacky Bai <ping.bai@nxp.com> > Sent: Monday, June 7, 2021 2:11 PM > > Add pinctrl binding doc for i.MX8ULP > > Signed-off-by: Jacky Bai <ping.bai@nxp.com> > Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Regards Aisheng
On Mon, Jun 7, 2021 at 8:00 AM Jacky Bai <ping.bai@nxp.com> wrote: > Add pinctrl binding doc for i.MX8ULP > > Signed-off-by: Jacky Bai <ping.bai@nxp.com> > Reviewed-by: Rob Herring <robh@kernel.org> Patch applied! Yours, Linus Walleij
On Mon, Jun 7, 2021 at 8:00 AM Jacky Bai <ping.bai@nxp.com> wrote: > From: Anson Huang <Anson.Huang@nxp.com> > > Add i.MX8ULP pinctrl driver support. > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > Signed-off-by: Jacky Bai <ping.bai@nxp.com> Patch applied! BTW does "ULP" in the name mean "ultra low power" as usual? Yours, Linus Walleij
Hi Linus, On Fri, Jul 23, 2021 at 1:05 PM Linus Walleij <linus.walleij@linaro.org> wrote: > Patch applied! > > BTW does "ULP" in the name mean "ultra low power" as usual? Yes, this is correct: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-8-processors/i-mx-8ulp-applications-processor-family:i.MX8ULP Thanks
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml new file mode 100644 index 000000000000..86622c4f374b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,imx8ulp-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale IMX8ULP IOMUX Controller + +maintainers: + - Jacky Bai <ping.bai@nxp.com> + +description: + Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory + for common binding part and usage. + +properties: + compatible: + const: fsl,imx8ulp-iomuxc1 + + reg: + maxItems: 1 + +# Client device subnode's properties +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + description: + each entry consists of 5 integers and represents the mux and config + setting for one pin. The first 4 integers <mux_config_reg input_reg + mux_mode input_val> are specified using a PIN_FUNC_ID macro, which can + be found in <arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h>. The last + integer CONFIG is the pad setting value like pull-up on this pin. Please + refer to i.MX8ULP Reference Manual for detailed CONFIG settings. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "mux_config_reg" indicates the offset of mux register. + - description: | + "input_reg" indicates the offset of select input register. + - description: | + "mux_mode" indicates the mux value to be applied. + - description: | + "input_val" indicates the select input value to be applied. + - description: | + "pad_setting" indicates the pad configuration value to be applied. + + required: + - fsl,pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + # Pinmux controller node + - | + iomuxc: pinctrl@298c0000 { + compatible = "fsl,imx8ulp-iomuxc1"; + reg = <0x298c0000 0x10000>; + + pinctrl_lpuart5: lpuart5grp { + fsl,pins = + <0x0138 0x08F0 0x4 0x3 0x3>, + <0x013C 0x08EC 0x4 0x3 0x3>; + }; + }; + +...