| Message ID | 20210603221758.10305-1-prabhakar.mahadev-lad.rj@bp.renesas.com |
|---|---|
| Headers | show |
| Series | Add new Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK support | expand |
Hi Prabhakar, Thanks for the patch. > Subject: [PATCH v2 11/12] arm64: dts: renesas: Add initial DTSI for > RZ/G2{L,LC} SoC's > > Add initial DTSI for RZ/G2{L,LC} SoC's. > > File structure: > r9a07g044.dtsi => RZ/G2L family SoC common parts r9a07g044l1.dtsi => > Specific to RZ/G2L (R9A07G044L single cortex A55) SoC > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 119 +++++++++++++++++++ > arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi | 25 ++++ > 2 files changed, 144 insertions(+) > create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044.dtsi > create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi > > diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > new file mode 100644 > index 000000000000..b2dbf6543d98 > --- /dev/null > +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > @@ -0,0 +1,119 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +/* > + * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts > + * > + * Copyright (C) 2021 Renesas Electronics Corp. > + */ > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/clock/r9a07g044-cpg.h> > + > +/ { > + compatible = "renesas,r9a07g044"; > + #address-cells = <2>; > + #size-cells = <2>; > + > + extal_clk: extal { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + /* This value must be overridden by the board */ > + clock-frequency = <0>; > + }; > + > + psci { > + compatible = "arm,psci-1.0", "arm,psci-0.2"; > + method = "smc"; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + core1 { > + cpu = <&cpu1>; > + }; > + }; > + }; > + > + cpu0: cpu@0 { > + compatible = "arm,cortex-a55"; > + reg = <0>; > + device_type = "cpu"; > + next-level-cache = <&L3_CA55>; > + enable-method = "psci"; > + }; > + > + cpu1: cpu@100 { > + compatible = "arm,cortex-a55"; > + reg = <0x100>; > + device_type = "cpu"; > + next-level-cache = <&L3_CA55>; > + enable-method = "psci"; > + }; > + > + L3_CA55: cache-controller-0 { > + compatible = "cache"; > + cache-unified; > + cache-size = <0x40000>; > + }; > + }; > + > + soc: soc { > + compatible = "simple-bus"; > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + scif0: serial@1004b800 { > + compatible = "renesas,scif-r9a07g044"; > + reg = <0 0x1004b800 0 0x400>; > + interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "eri", "rxi", "txi", > + "bri", "dri", "tei"; > + clocks = <&cpg CPG_MOD R9A07G044_CLK_SCIF0>; > + clock-names = "fck"; > + power-domains = <&cpg>; > + resets = <&cpg R9A07G044_CLK_SCIF0>; > + status = "disabled"; > + }; > + > + cpg: clock-controller@11010000 { > + compatible = "renesas,r9a07g044-cpg"; > + reg = <0 0x11010000 0 0x10000>; What about WDTOVF_RST(0xB10) and WDTRST_SEL(0xB14) registers, this registers to be handled by WDT driver. Unfortunately it is in CPG block. So do we need to map the entire CPG registers or up to 0xB00? Geert, Prabhakar: Any thoughts? Cheers, Biju > + clocks = <&extal_clk>; > + clock-names = "extal"; > + #clock-cells = <2>; > + #reset-cells = <1>; > + #power-domain-cells = <0>; > + }; > + > + gic: interrupt-controller@11900000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + #address-cells = <0>; > + interrupt-controller; > + reg = <0x0 0x11900000 0 0x40000>, > + <0x0 0x11940000 0 0x60000>; > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) > | IRQ_TYPE_LEVEL_LOW)>, > + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | > IRQ_TYPE_LEVEL_LOW)>, > + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | > IRQ_TYPE_LEVEL_LOW)>, > + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | > IRQ_TYPE_LEVEL_LOW)>; > + }; > +}; > diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi > b/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi > new file mode 100644 > index 000000000000..02f6da806696 > --- /dev/null > +++ b/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi > @@ -0,0 +1,25 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +/* > + * Device Tree Source for the RZ/G2L R9A07G044L1 common parts > + * > + * Copyright (C) 2021 Renesas Electronics Corp. > + */ > + > +/dts-v1/; > +#include "r9a07g044.dtsi" > + > +/ { > + compatible = "renesas,r9a07g044l1", "renesas,r9a07g044"; > + > + cpus { > + /delete-node/ cpu-map; > + /delete-node/ cpu@100; > + }; > + > + timer { > + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) > | IRQ_TYPE_LEVEL_LOW)>, > + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | > IRQ_TYPE_LEVEL_LOW)>, > + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | > IRQ_TYPE_LEVEL_LOW)>, > + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | > IRQ_TYPE_LEVEL_LOW)>; > + }; > +}; > -- > 2.17.1
Hi Geert, On Thu, Jun 3, 2021 at 11:18 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > Hi All, > > This patch series adds initial support for Renesas RZ/G2L SoC and > Renesas RZ/G2L SMARC EVK. > > Initial patches enables minimal peripherals on Renesas RZ/G2L > SMARC EVK and booted via initramfs. > * Documentation for RZ/G2{L,LC,UL} SoC variants > * SoC identification support > * CPG core support > * Minimal SoC DTSi > * Minimal DTS for SMARC EVK > > Changes for v2: > * Included type-2 RZ/G2Ul SoC in binding doc > * Added single entry for SMARC EVK "renesas,smarc-evk" > * Renamed ARCH_R9A07G044L to ARCH_R9A07G044 and > dropped ARCH_R9A07G044LC config > * Dropped SoC identification changes will post them as > separate patch. > * Updated comment in sh-sci.c > * Binding documentation patch for serial driver has been > accepted so dropped the patch from this series > * Incorporated changes requested by Geert for CPG core > * Fixed dtbs_check errors > * Dropped 'clock-names'/'clocks'/'power-domains'/'resets' > properties from GIC node and will include them in a separate > patch along with arm,gic-v3.yaml binding updates > * Included ACK's from Rob > > Patches are based on top of [1] master branch. > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git/ > > Cheers, > Prabhakar > > Biju Das (1): > serial: sh-sci: Add support for RZ/G2L SoC > > Lad Prabhakar (11): > dt-bindings: arm: renesas: Document Renesas RZ/G2UL SoC > dt-bindings: arm: renesas: Document Renesas RZ/G2{L,LC} SoC variants > dt-bindings: arm: renesas: Document SMARC EVK > soc: renesas: Add ARCH_R9A07G044 for the new RZ/G2L SoC's > arm64: defconfig: Enable ARCH_R9A07G044 > clk: renesas: Define RZ/G2L CPG Clock Definitions > dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver > clk: renesas: Add CPG core wrapper for RZ/G2L SoC > clk: renesas: Add support for R9A07G044 SoC > arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's > arm64: dts: renesas: Add initial device tree for RZ/G2L SMARC EVK > Biju pointed out USB/ADC isn't working with the current implementation on upstream kernel, I'll have to re-structure to accommodate this use-case. I'll send a v3 fixing the issue. Sorry for the inconvenience. Cheers, Prabhakar > .../devicetree/bindings/arm/renesas.yaml | 18 + > .../bindings/clock/renesas,rzg2l-cpg.yaml | 80 ++ > arch/arm64/boot/dts/renesas/Makefile | 2 + > arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 119 +++ > arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi | 25 + > .../boot/dts/renesas/r9a07g044l2-smarc.dts | 21 + > arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 27 + > arch/arm64/configs/defconfig | 1 + > drivers/clk/renesas/Kconfig | 9 + > drivers/clk/renesas/Makefile | 2 + > drivers/clk/renesas/r9a07g044-cpg.c | 372 +++++++ > drivers/clk/renesas/renesas-rzg2l-cpg.c | 979 ++++++++++++++++++ > drivers/clk/renesas/renesas-rzg2l-cpg.h | 217 ++++ > drivers/soc/renesas/Kconfig | 5 + > drivers/tty/serial/sh-sci.c | 12 +- > drivers/tty/serial/sh-sci.h | 1 + > include/dt-bindings/clock/r9a07g044-cpg.h | 89 ++ > 17 files changed, 1978 insertions(+), 1 deletion(-) > create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml > create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044.dtsi > create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi > create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts > create mode 100644 arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi > create mode 100644 drivers/clk/renesas/r9a07g044-cpg.c > create mode 100644 drivers/clk/renesas/renesas-rzg2l-cpg.c > create mode 100644 drivers/clk/renesas/renesas-rzg2l-cpg.h > create mode 100644 include/dt-bindings/clock/r9a07g044-cpg.h > > -- > 2.17.1 >
Hi Geert, Thanks for the feedback. > Subject: Re: [PATCH v2 11/12] arm64: dts: renesas: Add initial DTSI for > RZ/G2{L,LC} SoC's > > Hi Biju, > > On Fri, Jun 4, 2021 at 3:55 PM Biju Das <biju.das.jz@bp.renesas.com> > wrote: > > > Subject: [PATCH v2 11/12] arm64: dts: renesas: Add initial DTSI for > > > RZ/G2{L,LC} SoC's > > > > > > Add initial DTSI for RZ/G2{L,LC} SoC's. > > > > > > File structure: > > > r9a07g044.dtsi => RZ/G2L family SoC common parts r9a07g044l1.dtsi > > > => Specific to RZ/G2L (R9A07G044L single cortex A55) SoC > > > > > > Signed-off-by: Lad Prabhakar > > > <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > > > --- /dev/null > > > +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > > > > + cpg: clock-controller@11010000 { > > > + compatible = "renesas,r9a07g044-cpg"; > > > + reg = <0 0x11010000 0 0x10000>; > > > > What about WDTOVF_RST(0xB10) and WDTRST_SEL(0xB14) registers, this > registers to be handled by WDT driver. > > Unfortunately it is in CPG block. > > > > So do we need to map the entire CPG registers or up to 0xB00? > > > > Geert, Prabhakar: Any thoughts? > > As the registers are part of the CPG block, I think they should be covered > by the CPG node. You can handle them in the CPG driver, through functions > called from the WDT driver (cfr. rcar_rst_read_mode_pins()). Got it. Similar case for WDTCTRL register to stop watchdog. This register is in SYSC block. So we need to handle this register in SYSC driver. Cheers, Biju > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux- > m68k.org > > In personal conversations with technical people, I call myself a hacker. > But when I'm talking to journalists I just say "programmer" or something > like that. > -- Linus Torvalds
Hi All, This patch series adds initial support for Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK. Initial patches enables minimal peripherals on Renesas RZ/G2L SMARC EVK and booted via initramfs. * Documentation for RZ/G2{L,LC,UL} SoC variants * SoC identification support * CPG core support * Minimal SoC DTSi * Minimal DTS for SMARC EVK Changes for v2: * Included type-2 RZ/G2Ul SoC in binding doc * Added single entry for SMARC EVK "renesas,smarc-evk" * Renamed ARCH_R9A07G044L to ARCH_R9A07G044 and dropped ARCH_R9A07G044LC config * Dropped SoC identification changes will post them as separate patch. * Updated comment in sh-sci.c * Binding documentation patch for serial driver has been accepted so dropped the patch from this series * Incorporated changes requested by Geert for CPG core * Fixed dtbs_check errors * Dropped 'clock-names'/'clocks'/'power-domains'/'resets' properties from GIC node and will include them in a separate patch along with arm,gic-v3.yaml binding updates * Included ACK's from Rob Patches are based on top of [1] master branch. [1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git/ Cheers, Prabhakar Biju Das (1): serial: sh-sci: Add support for RZ/G2L SoC Lad Prabhakar (11): dt-bindings: arm: renesas: Document Renesas RZ/G2UL SoC dt-bindings: arm: renesas: Document Renesas RZ/G2{L,LC} SoC variants dt-bindings: arm: renesas: Document SMARC EVK soc: renesas: Add ARCH_R9A07G044 for the new RZ/G2L SoC's arm64: defconfig: Enable ARCH_R9A07G044 clk: renesas: Define RZ/G2L CPG Clock Definitions dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver clk: renesas: Add CPG core wrapper for RZ/G2L SoC clk: renesas: Add support for R9A07G044 SoC arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's arm64: dts: renesas: Add initial device tree for RZ/G2L SMARC EVK .../devicetree/bindings/arm/renesas.yaml | 18 + .../bindings/clock/renesas,rzg2l-cpg.yaml | 80 ++ arch/arm64/boot/dts/renesas/Makefile | 2 + arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 119 +++ arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi | 25 + .../boot/dts/renesas/r9a07g044l2-smarc.dts | 21 + arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 27 + arch/arm64/configs/defconfig | 1 + drivers/clk/renesas/Kconfig | 9 + drivers/clk/renesas/Makefile | 2 + drivers/clk/renesas/r9a07g044-cpg.c | 372 +++++++ drivers/clk/renesas/renesas-rzg2l-cpg.c | 979 ++++++++++++++++++ drivers/clk/renesas/renesas-rzg2l-cpg.h | 217 ++++ drivers/soc/renesas/Kconfig | 5 + drivers/tty/serial/sh-sci.c | 12 +- drivers/tty/serial/sh-sci.h | 1 + include/dt-bindings/clock/r9a07g044-cpg.h | 89 ++ 17 files changed, 1978 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts create mode 100644 arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi create mode 100644 drivers/clk/renesas/r9a07g044-cpg.c create mode 100644 drivers/clk/renesas/renesas-rzg2l-cpg.c create mode 100644 drivers/clk/renesas/renesas-rzg2l-cpg.h create mode 100644 include/dt-bindings/clock/r9a07g044-cpg.h