| Message ID | 20210601062338.1969040-1-ping.bai@nxp.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [1/2] dt-bindings: pinctrl: imx8ulp: Add pinctrl binding | expand |
Hi Jacky, On Tue, Jun 1, 2021 at 3:13 AM Jacky Bai <ping.bai@nxp.com> wrote: > + pinctrl_lpuart5: lpuart5grp { > + fsl,pins = > + <0x0138 0x08F0 0x4 0x3 0x3>, > + <0x013C 0x08EC 0x4 0x3 0x3>; This is hard to read. Can't we use the pinctrl defines here instead?
> Subject: Re: [PATCH 1/2] dt-bindings: pinctrl: imx8ulp: Add pinctrl binding > > Hi Jacky, > > On Tue, Jun 1, 2021 at 3:13 AM Jacky Bai <ping.bai@nxp.com> wrote: > > > + pinctrl_lpuart5: lpuart5grp { > > + fsl,pins = > > + <0x0138 0x08F0 0x4 0x3 0x3>, > > + <0x013C 0x08EC 0x4 0x3 0x3>; > > This is hard to read. Can't we use the pinctrl defines here instead? Sure, I will update in v2. BR Jacky Bai
> Subject: Re: [PATCH 2/2] pinctrl: imx8ulp: Add pinctrl driver support > > Hi Jacky, > > On Tue, Jun 1, 2021 at 3:13 AM Jacky Bai <ping.bai@nxp.com> wrote: > > > + pin_reg = &ipctl->pin_regs[offset]; > > + if (pin_reg->mux_reg == -1) > > Can this condition happen? Seems not, I will remove in V2. > > > + return -EINVAL; > > > +static const struct of_device_id imx8ulp_pinctrl_of_match[] = { > > + { .compatible = "fsl,imx8ulp-iomuxc1", }, > > In the bindings doc patch it is documented "fsl,imx8ulp-iomuxc", so there is > a mismatch between the driver and the binding doc. Sorry, it is a typo in binding doc, will fix in V2. BR Jacky Bai
On Tue, 01 Jun 2021 14:23:37 +0800, Jacky Bai wrote: > Add pinctrl binding doc for i.MX8ULP > > Signed-off-by: Jacky Bai <ping.bai@nxp.com> > --- > .../bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml | 79 +++++++++++++++++++ > 1 file changed, 79 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml new file mode 100644 index 000000000000..594c61c34dad --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,imx8ulp-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale IMX8MP IOMUX Controller + +maintainers: + - Jacky Bai <ping.bai@nxp.com> + +description: + Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory + for common binding part and usage. + +properties: + compatible: + const: fsl,imx8ulp-iomuxc + + reg: + maxItems: 1 + +# Client device subnode's properties +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + description: + each entry consists of 5 integers and represents the mux and config + setting for one pin. The first 4 integers <mux_config_reg input_reg + mux_mode input_val> are specified using a PIN_FUNC_ID macro, which can + be found in <arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h>. The last + integer CONFIG is the pad setting value like pull-up on this pin. Please + refer to i.MX8ULP Reference Manual for detailed CONFIG settings. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "mux_config_reg" indicates the offset of mux register. + - description: | + "input_reg" indicates the offset of select input register. + - description: | + "mux_mode" indicates the mux value to be applied. + - description: | + "input_val" indicates the select input value to be applied. + - description: | + "pad_setting" indicates the pad configuration value to be applied. + + required: + - fsl,pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + # Pinmux controller node + - | + iomuxc: pinctrl@298c0000 { + compatible = "fsl,imx8ulp-iomuxc"; + reg = <0x298c0000 0x10000>; + + pinctrl_lpuart5: lpuart5grp { + fsl,pins = + <0x0138 0x08F0 0x4 0x3 0x3>, + <0x013C 0x08EC 0x4 0x3 0x3>; + }; + }; + +...
Add pinctrl binding doc for i.MX8ULP Signed-off-by: Jacky Bai <ping.bai@nxp.com> --- .../bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml | 79 +++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml