| Message ID | 20210603115032.2470-1-michael.wei.hong.sit@intel.com |
|---|---|
| Headers | show |
| Series | Enable 2.5Gbps speed for stmmac | expand |
Hi, On Thu, Jun 03, 2021 at 07:50:29PM +0800, Michael Sit Wei Hong wrote: > Intel mGbE supports 2.5Gbps link speed by overclocking the clock rate > by 2.5 times to support 2.5Gbps link speed. In this mode, the serdes/PHY > operates at a serial baud rate of 3.125 Gbps and the PCS data path and > GMII interface of the MAC operate at 312.5 MHz instead of 125 MHz. > This is configured in the BIOS during boot up. The kernel driver is not able > access to modify the clock rate for 1Gbps/2.5G mode on the fly. The way to > determine the current 1G/2.5G mode is by reading a dedicated adhoc > register through mdio bus. How does this interact with Vladimir's "Convert xpcs to phylink_pcs_ops" series? Is there an inter-dependency between these, or a preferred order that they should be applied? Thanks.
On Thu, Jun 03, 2021 at 01:43:09PM +0000, Sit, Michael Wei Hong wrote: > Vladimir, > > > -----Original Message----- > > From: Vladimir Oltean <olteanv@gmail.com> > > Sent: Thursday, June 3, 2021 9:28 PM > > To: Russell King (Oracle) <linux@armlinux.org.uk> > > Cc: Sit, Michael Wei Hong <michael.wei.hong.sit@intel.com>; > > Jose.Abreu@synopsys.com; andrew@lunn.ch; > > hkallweit1@gmail.com; kuba@kernel.org; > > netdev@vger.kernel.org; peppe.cavallaro@st.com; > > alexandre.torgue@foss.st.com; davem@davemloft.net; > > mcoquelin.stm32@gmail.com; Voon, Weifeng > > <weifeng.voon@intel.com>; Ong, Boon Leong > > <boon.leong.ong@intel.com>; Tan, Tee Min > > <tee.min.tan@intel.com>; vee.khee.wong@linux.intel.com; > > Wong, Vee Khee <vee.khee.wong@intel.com>; linux-stm32@st- > > md-mailman.stormreply.com; linux-arm- > > kernel@lists.infradead.org; linux-kernel@vger.kernel.org > > Subject: Re: [RESEND PATCH net-next v4 0/3] Enable 2.5Gbps > > speed for stmmac > > > > Michael, > > > > On Thu, Jun 03, 2021 at 02:08:51PM +0100, Russell King (Oracle) > > wrote: > > > Hi, > > > > > > On Thu, Jun 03, 2021 at 07:50:29PM +0800, Michael Sit Wei Hong > > wrote: > > > > Intel mGbE supports 2.5Gbps link speed by overclocking the > > clock > > > > rate by 2.5 times to support 2.5Gbps link speed. In this mode, > > the > > > > serdes/PHY operates at a serial baud rate of 3.125 Gbps and > > the PCS > > > > data path and GMII interface of the MAC operate at 312.5 > > MHz instead of 125 MHz. > > > > This is configured in the BIOS during boot up. The kernel > > driver is > > > > not able access to modify the clock rate for 1Gbps/2.5G mode > > on the > > > > fly. The way to determine the current 1G/2.5G mode is by > > reading a > > > > dedicated adhoc register through mdio bus. > > > > > > How does this interact with Vladimir's "Convert xpcs to > > phylink_pcs_ops" > > > series? Is there an inter-dependency between these, or a > > preferred > > > order that they should be applied? > > > > > > Thanks. > > > > My preferred order would be for my series to go in first, if > > possible, because I don't have hardware readily available to test, > > and VK already has tested my patches a few times until they > > reached a stable state. > > > > I went through your patches and I think rebasing on top of my > > phylink_pcs_ops conversion should be easy. > > > > Thanks. > Sure! I am okay to let you merge your codes and rebase my changes later on > Do let me know when I can start rebasing and send in the next revision Well, you are already copied to my patches, so you should get the notification email at the same time as I would. https://patchwork.kernel.org/project/netdevbpf/cover/20210602162019.2201925-1-olteanv@gmail.com/
> @@ -7002,6 +7006,9 @@ int stmmac_dvr_probe(struct device *device, > } > } > > + if (priv->plat->speed_mode_2500) > + pri*v->plat->speed_mode_2500(ndev, priv->plat->bsp_priv); > + > if (priv->plat->mdio_bus_data->has_xpcs) { > ret = stmmac_xpcs_setup(priv->mii); > if (ret) > > With the current placement, there seems to be indeed no way for the > platform-level code to set plat->phy_interface after the MDIO bus has > probed but before the XPCS has probed. > > I wonder whether it might be possible to probe the XPCS completely > outside of stmmac_dvr_probe(); once that function ends you should have > all knowledge necessary to set plat->phy_interface all within the > Intel platform code. An additional benefit if you do this is that you > no longer need the has_xpcs variable - Intel is the only one setting > it right now, as far as I can see. What do you think? Hi Vladimir, I still think that stmmac_dvr_probe() the suitable place to probe the XPCS together with MDIO and PHY setup. In addition, XPCS also need to be probed before stmmac_open()as there is an checking of XPCS AN mode at the very beginning of the function. The has_xpcs variable is introduced in the very first commits in the XPCS design. Although currently Intel is the only one using it, it is beneficial for any future system that pair stmmac with xpcs. Weifeng