diff mbox series

serial: sh-sci: Fix off-by-one error in FIFO threshold register setting

Message ID 5eff320aef92ffb33d00e57979fd3603bbb4a70f.1620648218.git.geert+renesas@glider.be
State New
Headers show
Series serial: sh-sci: Fix off-by-one error in FIFO threshold register setting | expand

Commit Message

Geert Uytterhoeven May 10, 2021, 12:07 p.m. UTC
The Receive FIFO Data Count Trigger field (RTRG[6:0]) in the Receive
FIFO Data Count Trigger Register (HSRTRGR) of HSCIF can only hold values
ranging from 0-127.  As the FIFO size is equal to 128 on HSCIF, the user
can write an out-of-range value, touching reserved bits.

Fix this by limiting the trigger value to the FIFO size minus one.
Reverse the order of the checks, to avoid rx_trig becoming zero if the
FIFO size is one.

Note that this change has no impact on other SCIF variants, as their
maximum supported trigger value is lower than the FIFO size anyway, and
the code below takes care of enforcing these limits.

Reported-by: Linh Phung <linh.phung.jy@renesas.com>
Fixes: a380ed461f66d1b8 ("serial: sh-sci: implement FIFO threshold register setting")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Compile-tested only.

The BSP contains a different patch[1], which masks the value to write by
0x7f.  This is IMHO incorrect, as it would set the trigger value to zero
when 128 is requested.

[1] "serial: sh-sci: Using mask when writing to HSRTRGR"
    https://github.com/renesas-rcar/linux-bsp/commit/9915223f41c7d680aaaed12971601dc038ce76a3
---
 drivers/tty/serial/sh-sci.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Wolfram Sang May 11, 2021, 8:55 a.m. UTC | #1
On Mon, May 10, 2021 at 02:07:55PM +0200, Geert Uytterhoeven wrote:
> The Receive FIFO Data Count Trigger field (RTRG[6:0]) in the Receive
> FIFO Data Count Trigger Register (HSRTRGR) of HSCIF can only hold values
> ranging from 0-127.  As the FIFO size is equal to 128 on HSCIF, the user
> can write an out-of-range value, touching reserved bits.
> 
> Fix this by limiting the trigger value to the FIFO size minus one.
> Reverse the order of the checks, to avoid rx_trig becoming zero if the
> FIFO size is one.
> 
> Note that this change has no impact on other SCIF variants, as their
> maximum supported trigger value is lower than the FIFO size anyway, and
> the code below takes care of enforcing these limits.
> 
> Reported-by: Linh Phung <linh.phung.jy@renesas.com>
> Fixes: a380ed461f66d1b8 ("serial: sh-sci: implement FIFO threshold register setting")
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> Compile-tested only.
> 
> The BSP contains a different patch[1], which masks the value to write by
> 0x7f.  This is IMHO incorrect, as it would set the trigger value to zero
> when 128 is requested.

Makes also sense to me to have the trigger at fifosize-1 to have one
spare byte to handle latencies.

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Ulrich Hecht May 11, 2021, 10:07 a.m. UTC | #2
> On 05/10/2021 2:07 PM Geert Uytterhoeven <geert+renesas@glider.be> wrote:
> 
>  
> The Receive FIFO Data Count Trigger field (RTRG[6:0]) in the Receive
> FIFO Data Count Trigger Register (HSRTRGR) of HSCIF can only hold values
> ranging from 0-127.  As the FIFO size is equal to 128 on HSCIF, the user
> can write an out-of-range value, touching reserved bits.
> 
> Fix this by limiting the trigger value to the FIFO size minus one.
> Reverse the order of the checks, to avoid rx_trig becoming zero if the
> FIFO size is one.
> 
> Note that this change has no impact on other SCIF variants, as their
> maximum supported trigger value is lower than the FIFO size anyway, and
> the code below takes care of enforcing these limits.
> 
> Reported-by: Linh Phung <linh.phung.jy@renesas.com>
> Fixes: a380ed461f66d1b8 ("serial: sh-sci: implement FIFO threshold register setting")
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> Compile-tested only.
> 
> The BSP contains a different patch[1], which masks the value to write by
> 0x7f.  This is IMHO incorrect, as it would set the trigger value to zero
> when 128 is requested.
> 
> [1] "serial: sh-sci: Using mask when writing to HSRTRGR"
>     https://github.com/renesas-rcar/linux-bsp/commit/9915223f41c7d680aaaed12971601dc038ce76a3
> ---
>  drivers/tty/serial/sh-sci.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
> index ef37fdf37612f82f..4baf1316ea729931 100644
> --- a/drivers/tty/serial/sh-sci.c
> +++ b/drivers/tty/serial/sh-sci.c
> @@ -1023,10 +1023,10 @@ static int scif_set_rtrg(struct uart_port *port, int rx_trig)
>  {
>  	unsigned int bits;
>  
> +	if (rx_trig >= port->fifosize)
> +		rx_trig = port->fifosize - 1;
>  	if (rx_trig < 1)
>  		rx_trig = 1;
> -	if (rx_trig >= port->fifosize)
> -		rx_trig = port->fifosize;
>  
>  	/* HSCIF can be set to an arbitrary level. */
>  	if (sci_getreg(port, HSRTRGR)->size) {
> -- 
> 2.25.1

Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>

CU
Uli
diff mbox series

Patch

diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index ef37fdf37612f82f..4baf1316ea729931 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -1023,10 +1023,10 @@  static int scif_set_rtrg(struct uart_port *port, int rx_trig)
 {
 	unsigned int bits;
 
+	if (rx_trig >= port->fifosize)
+		rx_trig = port->fifosize - 1;
 	if (rx_trig < 1)
 		rx_trig = 1;
-	if (rx_trig >= port->fifosize)
-		rx_trig = port->fifosize;
 
 	/* HSCIF can be set to an arbitrary level. */
 	if (sci_getreg(port, HSRTRGR)->size) {