| Message ID | 20210510213634.600866-1-linus.walleij@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [1/3] crypto: ixp4xx: convert to platform driver | expand |
Le Mon, May 10, 2021 at 11:36:32PM +0200, Linus Walleij a écrit : > From: Arnd Bergmann <arnd@arndb.de> > > The ixp4xx_crypto driver traditionally registers a bare platform > device without attaching it to a driver, and detects the hardware > at module init time by reading an SoC specific hardware register. > > Change this to the conventional method of registering the platform > device from the platform code itself when the device is present, > turning the module_init/module_exit functions into probe/release > driver callbacks. > > This enables compile-testing as well as potentially having ixp4xx > coexist with other ARMv5 platforms in the same kernel in the future. > > Signed-off-by: Arnd Bergmann <arnd@arndb.de> > Signed-off-by: Linus Walleij <linus.walleij@linaro.org> > --- > Herbert, David: I am looking for an ACK to take this > into the ARM SoC tree as we want to change more stuff in > the machine at the same time that we want to resolve > there. > --- > arch/arm/mach-ixp4xx/common.c | 26 ++++++++++++++++++++++++ > drivers/crypto/Kconfig | 3 ++- > drivers/crypto/ixp4xx_crypto.c | 37 ++++++++++++---------------------- > 3 files changed, 41 insertions(+), 25 deletions(-) > Hello With minor editing I successfully added this series on top of my fix series https://lore.kernel.org/patchwork/cover/1421865/ With the following patch, I successfully booted my epbx100 board and the crypto driver loaded. --- a/arch/arm/boot/dts/intel-ixp4xx.dtsi +++ b/arch/arm/boot/dts/intel-ixp4xx.dtsi @@ -61,9 +61,16 @@ timer@c8005000 { interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; }; - npe@c8006000 { + npe: npe@c8006000 { compatible = "intel,ixp4xx-network-processing-engine"; reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>; + + crypto { + compatible = "intel,ixp4xx-crypto"; + intel,npe-handle = <&npe 2>; + queue-rx = <&qmgr 30>; + queue-txready = <&qmgr 29>; + }; }; }; }; So you could add Tested-by: Corentin Labbe <clabbe@baylibre.com> Thanks
On Mon, 10 May 2021 23:36:33 +0200, Linus Walleij wrote: > This adds device tree bindings for the ixp4xx crypto engine. > > Cc: devicetree@vger.kernel.org > Signed-off-by: Linus Walleij <linus.walleij@linaro.org> > --- > Herbert, David: This can be applied separately once we are > happy with the bindings, alternatively it can be merged > with the support code into ARM SoC. > --- > .../bindings/crypto/intel,ixp4xx-crypto.yaml | 59 +++++++++++++++++++ > 1 file changed, 59 insertions(+) > create mode 100644 Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.example.dt.yaml: npe@c8006000: 'crypto' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml See https://patchwork.ozlabs.org/patch/1476741 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
On Mon, May 10, 2021 at 11:36:33PM +0200, Linus Walleij wrote: > This adds device tree bindings for the ixp4xx crypto engine. > > Cc: devicetree@vger.kernel.org > Signed-off-by: Linus Walleij <linus.walleij@linaro.org> > --- > Herbert, David: This can be applied separately once we are > happy with the bindings, alternatively it can be merged > with the support code into ARM SoC. > --- > .../bindings/crypto/intel,ixp4xx-crypto.yaml | 59 +++++++++++++++++++ > 1 file changed, 59 insertions(+) > create mode 100644 Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml > > diff --git a/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml b/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml > new file mode 100644 > index 000000000000..28d75f4f9a76 > --- /dev/null > +++ b/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml > @@ -0,0 +1,59 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +# Copyright 2018 Linaro Ltd. > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Intel IXP4xx cryptographic engine > + > +maintainers: > + - Linus Walleij <linus.walleij@linaro.org> > + > +description: | > + The Intel IXP4xx cryptographic engine makes use of the IXP4xx NPE > + (Network Processing Engine). Since it is not a device on its own > + it is defined as a subnode of the NPE, if crypto support is > + available on the platform. > + > +properties: > + compatible: > + const: intel,ixp4xx-crypto > + > + intel,npe-handle: > + $ref: '/schemas/types.yaml#/definitions/phandle-array' > + maxItems: 1 > + description: phandle to the NPE this ethernet instance is using > + and the instance to use in the second cell > + > + queue-rx: > + $ref: '/schemas/types.yaml#/definitions/phandle-array' > + maxItems: 1 > + description: phandle to the RX queue on the NPE > + > + queue-txready: > + $ref: '/schemas/types.yaml#/definitions/phandle-array' > + maxItems: 1 > + description: phandle to the TX READY queue on the NPE > + > +required: > + - compatible > + - intel,npe-handle > + - queue-rx > + - queue-txready > + > +additionalProperties: false > + > +examples: > + - | > + npe: npe@c8006000 { > + compatible = "intel,ixp4xx-network-processing-engine"; > + reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>; > + > + crypto { The parent schema needs to define 'crypto' and have a ref to this schema. I'd put the example there rather than piecemeal. > + compatible = "intel,ixp4xx-crypto"; > + intel,npe-handle = <&npe 2>; A bit redundant to have a phandle to the parent. > + queue-rx = <&qmgr 30>; > + queue-txready = <&qmgr 29>; > + }; > + }; > -- > 2.30.2 >
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index 000f672a94c9..007a44412e24 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c @@ -233,12 +233,38 @@ static struct platform_device *ixp46x_devices[] __initdata = { unsigned long ixp4xx_exp_bus_size; EXPORT_SYMBOL(ixp4xx_exp_bus_size); +static struct platform_device_info ixp_dev_info __initdata = { + .name = "ixp4xx_crypto", + .id = 0, + .dma_mask = DMA_BIT_MASK(32), +}; + +static int __init ixp_crypto_register(void) +{ + struct platform_device *pdev; + + if (!(~(*IXP4XX_EXP_CFG2) & (IXP4XX_FEATURE_HASH | + IXP4XX_FEATURE_AES | IXP4XX_FEATURE_DES))) { + printk(KERN_ERR "ixp_crypto: No HW crypto available\n"); + return -ENODEV; + } + + pdev = platform_device_register_full(&ixp_dev_info); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + + return 0; +} + void __init ixp4xx_sys_init(void) { ixp4xx_exp_bus_size = SZ_16M; platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices)); + if (IS_ENABLED(CONFIG_CRYPTO_DEV_IXP4XX)) + ixp_crypto_register(); + if (cpu_is_ixp46x()) { int region; diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 9a4c275a1335..aa389e741876 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -324,7 +324,8 @@ config CRYPTO_DEV_TALITOS2 config CRYPTO_DEV_IXP4XX tristate "Driver for IXP4xx crypto hardware acceleration" - depends on ARCH_IXP4XX && IXP4XX_QMGR && IXP4XX_NPE + depends on IXP4XX_QMGR && IXP4XX_NPE + depends on ARCH_IXP4XX || COMPILE_TEST select CRYPTO_LIB_DES select CRYPTO_AEAD select CRYPTO_AUTHENC diff --git a/drivers/crypto/ixp4xx_crypto.c b/drivers/crypto/ixp4xx_crypto.c index 0616e369522e..879b93927e2a 100644 --- a/drivers/crypto/ixp4xx_crypto.c +++ b/drivers/crypto/ixp4xx_crypto.c @@ -224,8 +224,6 @@ static dma_addr_t crypt_phys; static int support_aes = 1; -#define DRIVER_NAME "ixp4xx_crypto" - static struct platform_device *pdev; static inline dma_addr_t crypt_virt2phys(struct crypt_ctl *virt) @@ -432,11 +430,6 @@ static int init_ixp_crypto(struct device *dev) int ret = -ENODEV; u32 msg[2] = { 0, 0 }; - if (! ( ~(*IXP4XX_EXP_CFG2) & (IXP4XX_FEATURE_HASH | - IXP4XX_FEATURE_AES | IXP4XX_FEATURE_DES))) { - printk(KERN_ERR "ixp_crypto: No HW crypto available\n"); - return ret; - } npe_c = npe_request(NPE_ID); if (!npe_c) return ret; @@ -1364,26 +1357,17 @@ static struct ixp_aead_alg ixp4xx_aeads[] = { #define IXP_POSTFIX "-ixp4xx" -static const struct platform_device_info ixp_dev_info __initdata = { - .name = DRIVER_NAME, - .id = 0, - .dma_mask = DMA_BIT_MASK(32), -}; - -static int __init ixp_module_init(void) +static int ixp_crypto_probe(struct platform_device *_pdev) { int num = ARRAY_SIZE(ixp4xx_algos); int i, err; - pdev = platform_device_register_full(&ixp_dev_info); - if (IS_ERR(pdev)) - return PTR_ERR(pdev); + pdev = _pdev; err = init_ixp_crypto(&pdev->dev); - if (err) { - platform_device_unregister(pdev); + if (err) return err; - } + for (i=0; i< num; i++) { struct skcipher_alg *cra = &ixp4xx_algos[i].crypto; @@ -1456,7 +1440,7 @@ static int __init ixp_module_init(void) return 0; } -static void __exit ixp_module_exit(void) +static int ixp_crypto_remove(struct platform_device *pdev) { int num = ARRAY_SIZE(ixp4xx_algos); int i; @@ -1471,11 +1455,16 @@ static void __exit ixp_module_exit(void) crypto_unregister_skcipher(&ixp4xx_algos[i].crypto); } release_ixp_crypto(&pdev->dev); - platform_device_unregister(pdev); + + return 0; } -module_init(ixp_module_init); -module_exit(ixp_module_exit); +static struct platform_driver ixp_crypto_driver = { + .probe = ixp_crypto_probe, + .remove = ixp_crypto_remove, + .driver = { .name = "ixp4xx_crypto" }, +}; +module_platform_driver(ixp_crypto_driver); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Christian Hohnstaedt <chohnstaedt@innominate.com>");