| Message ID | 20210506145829.198823-3-ulf.hansson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | mmc: core: Implement support for cache ctrl for SD cards | expand |
On Thu, May 6, 2021 at 4:58 PM Ulf Hansson <ulf.hansson@linaro.org> wrote: > In SD spec v6.x the SD function extension registers for performance > enhancements were introduced. As a part of this an optional internal cache > on the SD card, can be used to improve performance. > > The let the SD card use the cache, the host needs to enable it and manage > flushing of the cache, so let's add support for this. > > Note that for an SD card supporting the cache it's mandatory for it, to > also support the poweroff notification feature. According to the SD spec, > if the cache has been enabled and a poweroff notification is sent to the > card, that implicitly also means that the card should flush its internal > cache. Therefore, dealing with cache flushing for REQ_OP_FLUSH block > requests is sufficient. > > Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (...) > + /* > + * Set the Flush Cache bit in the performance enhancement register at > + * 261 bytes offset. > + */ > + fno = card->ext_perf.fno; > + page = card->ext_perf.page; > + offset = card->ext_perf.offset + 261; 261 looks a bit magic, can we add a define of some sort? I guess it has a name in the spec? > + err = sd_write_ext_reg(card, fno, page, offset, 0x1); > + if (err) { > + pr_warn("%s: error %d writing Cache Flush bit\n", > + mmc_hostname(host), err); > + goto out; > + } So this offset contains a single bit. > + if (reg_buf[0] & 0x1) > + err = -ETIMEDOUT; And that same bit is checked here. Is it always going to be one bit only or do we want to #include <linux/bits.h> #define SD_CACHE_FLUSH_FLAG BIT(0) Does it have a name in the spec we can use? > + /* > + * Set the Cache Enable bit in the performance enhancement register at > + * 260 bytes offset. > + */ > + err = sd_write_ext_reg(card, card->ext_perf.fno, card->ext_perf.page, > + card->ext_perf.offset + 260, 0x1); Same here we want to #define 260 to something symbolic, And here some define for BIT(0) as well. At least with BIT(0) in the call to sd_write_ext_reg() rather than 0x1 if I can say something. With the above nitpicking fixed up (I trust you): Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Yours, Linus Walleij
> +static int sd_enable_cache(struct mmc_card *card) > +{ > + u8 *reg_buf; > + int err; > + > + reg_buf = kzalloc(512, GFP_KERNEL); > + if (!reg_buf) > + return -ENOMEM; > + > + /* > + * Set the Cache Enable bit in the performance enhancement register at > + * 260 bytes offset. > + */ > + err = sd_write_ext_reg(card, card->ext_perf.fno, card->ext_perf.page, > + card->ext_perf.offset + 260, 0x1); > + if (err) { > + pr_warn("%s: error %d writing Cache Enable bit\n", > + mmc_hostname(card->host), err); > + goto out; > + } > + > + err = mmc_poll_for_busy(card, > SD_WRITE_EXTR_SINGLE_TIMEOUT_MS, false, > + MMC_BUSY_EXTR_SINGLE); I think 1sec is for flush cache, but I guess it makes sense to use it here as well. > + if (!err) > + card->ext_perf.feature_enabled |= SD_EXT_PERF_CACHE; Maybe If (err) card->ext_perf.feature_enabled &= ~SD_EXT_PERF_CACHE; and move to out: to catch the sd_write_ext_reg err ? > + > +out: > + kfree(reg_buf); > + return err; > +} > + > /* > * Handle the detection and initialisation of a card. > * > @@ -1442,6 +1531,13 @@ static int mmc_sd_init_card(struct mmc_host > *host, u32 ocr, > goto free_card; > } > > + /* Enable internal SD cache if supported. */ > + if (card->ext_perf.feature_support & SD_EXT_PERF_CACHE) { > + err = sd_enable_cache(card); > + if (err) > + goto free_card; If cache enablement failed, is it worthwhile to bail out? Maybe disabling the cache with the appropriate message is enough? > + } > + > if (host->cqe_ops && !host->cqe_enabled) { > err = host->cqe_ops->cqe_enable(host, card); > if (!err) { > @@ -1694,6 +1790,8 @@ static const struct mmc_bus_ops mmc_sd_ops = { > .alive = mmc_sd_alive, > .shutdown = mmc_sd_suspend, > .hw_reset = mmc_sd_hw_reset, > + .cache_enabled = sd_cache_enabled, > + .flush_cache = sd_flush_cache, > }; I would expect 2 more patches in this series: - flush cache on power down - cache disablement events? Thanks, Avri
> > + if (!err) > > + card->ext_perf.feature_enabled |= SD_EXT_PERF_CACHE; > Maybe > If (err) > card->ext_perf.feature_enabled &= ~SD_EXT_PERF_CACHE; > > and move to out: to catch the sd_write_ext_reg err ? Please ignore - got mixed up with card->ext_perf.feature_support... Sorry, Avri > > > + > > +out: > > + kfree(reg_buf); > > + return err; > > +} > > + > > /* > > * Handle the detection and initialisation of a card. > > * > > @@ -1442,6 +1531,13 @@ static int mmc_sd_init_card(struct mmc_host > > *host, u32 ocr, > > goto free_card; > > } > > > > + /* Enable internal SD cache if supported. */ > > + if (card->ext_perf.feature_support & SD_EXT_PERF_CACHE) { > > + err = sd_enable_cache(card); > > + if (err) > > + goto free_card; > If cache enablement failed, is it worthwhile to bail out? > Maybe disabling the cache with the appropriate message is enough? > > > + } > > + > > if (host->cqe_ops && !host->cqe_enabled) { > > err = host->cqe_ops->cqe_enable(host, card); > > if (!err) { > > @@ -1694,6 +1790,8 @@ static const struct mmc_bus_ops mmc_sd_ops = > { > > .alive = mmc_sd_alive, > > .shutdown = mmc_sd_suspend, > > .hw_reset = mmc_sd_hw_reset, > > + .cache_enabled = sd_cache_enabled, > > + .flush_cache = sd_flush_cache, > > }; > > I would expect 2 more patches in this series: > - flush cache on power down > - cache disablement events? > > Thanks, > Avri
On Sun, 9 May 2021 at 21:01, Linus Walleij <linus.walleij@linaro.org> wrote: > > On Thu, May 6, 2021 at 4:58 PM Ulf Hansson <ulf.hansson@linaro.org> wrote: > > > In SD spec v6.x the SD function extension registers for performance > > enhancements were introduced. As a part of this an optional internal cache > > on the SD card, can be used to improve performance. > > > > The let the SD card use the cache, the host needs to enable it and manage > > flushing of the cache, so let's add support for this. > > > > Note that for an SD card supporting the cache it's mandatory for it, to > > also support the poweroff notification feature. According to the SD spec, > > if the cache has been enabled and a poweroff notification is sent to the > > card, that implicitly also means that the card should flush its internal > > cache. Therefore, dealing with cache flushing for REQ_OP_FLUSH block > > requests is sufficient. > > > > Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> > (...) > > > + /* > > + * Set the Flush Cache bit in the performance enhancement register at > > + * 261 bytes offset. > > + */ > > + fno = card->ext_perf.fno; > > + page = card->ext_perf.page; > > + offset = card->ext_perf.offset + 261; > > 261 looks a bit magic, can we add a define of some sort? We could, but I am not sure it really improves things. At least it would not be consistent with the way we treat other magic numbers. I think it's better to look into this as wider cleanup instead. > I guess it has a name in the spec? It's called the "Power Management Setting Register". > > > + err = sd_write_ext_reg(card, fno, page, offset, 0x1); > > + if (err) { > > + pr_warn("%s: error %d writing Cache Flush bit\n", > > + mmc_hostname(host), err); > > + goto out; > > + } > > So this offset contains a single bit. > > > + if (reg_buf[0] & 0x1) > > + err = -ETIMEDOUT; > > And that same bit is checked here. Correct. > > Is it always going to be one bit only or do we want to > > #include <linux/bits.h> > #define SD_CACHE_FLUSH_FLAG BIT(0) > > Does it have a name in the spec we can use? Well, it just says "Cache Flush" bit. It seems to be one bit always for these features. The remaining bits in the same byte are unused/reserved. Each feature has at least one dedicated byte, so there are no bytes being shared between features. > > > + /* > > + * Set the Cache Enable bit in the performance enhancement register at > > + * 260 bytes offset. > > + */ > > + err = sd_write_ext_reg(card, card->ext_perf.fno, card->ext_perf.page, > > + card->ext_perf.offset + 260, 0x1); > > Same here we want to #define 260 to something symbolic, > > And here some define for BIT(0) as well. At least with BIT(0) > in the call to sd_write_ext_reg() rather than 0x1 if I can say > something. The conversion to BIT(0) in the argument is clearly an improvement. I do that change when applying, but leave the defines for the other magics to be considered as a future cleanup. > > With the above nitpicking fixed up (I trust you): > Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Thanks! Kind regards Uffe
On Mon, 10 May 2021 at 11:10, Avri Altman <Avri.Altman@wdc.com> wrote: > > > +static int sd_enable_cache(struct mmc_card *card) > > +{ > > + u8 *reg_buf; > > + int err; > > + > > + reg_buf = kzalloc(512, GFP_KERNEL); > > + if (!reg_buf) > > + return -ENOMEM; > > + > > + /* > > + * Set the Cache Enable bit in the performance enhancement register at > > + * 260 bytes offset. > > + */ > > + err = sd_write_ext_reg(card, card->ext_perf.fno, card->ext_perf.page, > > + card->ext_perf.offset + 260, 0x1); > > + if (err) { > > + pr_warn("%s: error %d writing Cache Enable bit\n", > > + mmc_hostname(card->host), err); > > + goto out; > > + } > > + > > + err = mmc_poll_for_busy(card, > > SD_WRITE_EXTR_SINGLE_TIMEOUT_MS, false, > > + MMC_BUSY_EXTR_SINGLE); > I think 1sec is for flush cache, but I guess it makes sense to use it here as well. The spec talks about generic busy signaling time for CMD49 of one second. That's why I added this here. > > > + if (!err) > > + card->ext_perf.feature_enabled |= SD_EXT_PERF_CACHE; > Maybe > If (err) > card->ext_perf.feature_enabled &= ~SD_EXT_PERF_CACHE; > > and move to out: to catch the sd_write_ext_reg err ? > > > + > > +out: > > + kfree(reg_buf); > > + return err; > > +} > > + > > /* > > * Handle the detection and initialisation of a card. > > * > > @@ -1442,6 +1531,13 @@ static int mmc_sd_init_card(struct mmc_host > > *host, u32 ocr, > > goto free_card; > > } > > > > + /* Enable internal SD cache if supported. */ > > + if (card->ext_perf.feature_support & SD_EXT_PERF_CACHE) { > > + err = sd_enable_cache(card); > > + if (err) > > + goto free_card; > If cache enablement failed, is it worthwhile to bail out? > Maybe disabling the cache with the appropriate message is enough? Right, good point. Let me also think about how we best reset the .feature_enabled field after a power cycle. Theoretically we could fail to enable a feature after the system has resumed, but then we would still have the correspond bits set. > > > + } > > + > > if (host->cqe_ops && !host->cqe_enabled) { > > err = host->cqe_ops->cqe_enable(host, card); > > if (!err) { > > @@ -1694,6 +1790,8 @@ static const struct mmc_bus_ops mmc_sd_ops = { > > .alive = mmc_sd_alive, > > .shutdown = mmc_sd_suspend, > > .hw_reset = mmc_sd_hw_reset, > > + .cache_enabled = sd_cache_enabled, > > + .flush_cache = sd_flush_cache, > > }; > > I would expect 2 more patches in this series: > - flush cache on power down According to the spec that should not be needed, because that should be managed internally in the SD card when we send a poweroff notification. Did I get that wrong? Do you prefer to send a flush cache as well before the poweroff notification? > - cache disablement events? This I don't know about. Can you elaborate? > > Thanks, > Avri Kind regards Uffe
> > I would expect 2 more patches in this series: > > - flush cache on power down > > According to the spec that should not be needed, because that should > be managed internally in the SD card when we send a poweroff > notification. > > Did I get that wrong? Do you prefer to send a flush cache as well > before the poweroff notification? > > > - cache disablement events? > > This I don't know about. Can you elaborate? As for the above 2 questions - I asked internally - it may take a while for people to get back to me. Let's leave it for now. Thanks, Avri > > > > > Thanks, > > Avri > > Kind regards > Uffe
diff --git a/drivers/mmc/core/mmc_ops.c b/drivers/mmc/core/mmc_ops.c index af423acc4c88..3c58f6d0f482 100644 --- a/drivers/mmc/core/mmc_ops.c +++ b/drivers/mmc/core/mmc_ops.c @@ -456,6 +456,7 @@ static int mmc_busy_cb(void *cb_data, bool *busy) err = R1_STATUS(status) ? -EIO : 0; break; case MMC_BUSY_HPI: + case MMC_BUSY_EXTR_SINGLE: break; default: err = -EINVAL; diff --git a/drivers/mmc/core/mmc_ops.h b/drivers/mmc/core/mmc_ops.h index c3c1d9c2577e..41ab4f573a31 100644 --- a/drivers/mmc/core/mmc_ops.h +++ b/drivers/mmc/core/mmc_ops.h @@ -14,6 +14,7 @@ enum mmc_busy_cmd { MMC_BUSY_CMD6, MMC_BUSY_ERASE, MMC_BUSY_HPI, + MMC_BUSY_EXTR_SINGLE, }; struct mmc_host; diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c index 760aa86bd54d..773444853607 100644 --- a/drivers/mmc/core/sd.c +++ b/drivers/mmc/core/sd.c @@ -67,6 +67,7 @@ static const unsigned int sd_au_size[] = { }) #define SD_POWEROFF_NOTIFY_TIMEOUT_MS 2000 +#define SD_WRITE_EXTR_SINGLE_TIMEOUT_MS 1000 struct sd_busy_data { struct mmc_card *card; @@ -1287,6 +1288,94 @@ static int sd_read_ext_regs(struct mmc_card *card) return err; } +static bool sd_cache_enabled(struct mmc_host *host) +{ + return host->card->ext_perf.feature_enabled & SD_EXT_PERF_CACHE; +} + +static int sd_flush_cache(struct mmc_host *host) +{ + struct mmc_card *card = host->card; + u8 *reg_buf, fno, page; + u16 offset; + int err; + + if (!sd_cache_enabled(host)) + return 0; + + reg_buf = kzalloc(512, GFP_KERNEL); + if (!reg_buf) + return -ENOMEM; + + /* + * Set the Flush Cache bit in the performance enhancement register at + * 261 bytes offset. + */ + fno = card->ext_perf.fno; + page = card->ext_perf.page; + offset = card->ext_perf.offset + 261; + + err = sd_write_ext_reg(card, fno, page, offset, 0x1); + if (err) { + pr_warn("%s: error %d writing Cache Flush bit\n", + mmc_hostname(host), err); + goto out; + } + + err = mmc_poll_for_busy(card, SD_WRITE_EXTR_SINGLE_TIMEOUT_MS, false, + MMC_BUSY_EXTR_SINGLE); + if (err) + goto out; + + /* + * Read the Flush Cache bit. The card shall reset it, to confirm that + * it's has completed the flushing of the cache. + */ + err = sd_read_ext_reg(card, fno, page, offset, 1, reg_buf); + if (err) { + pr_warn("%s: error %d reading Cache Flush bit\n", + mmc_hostname(host), err); + goto out; + } + + if (reg_buf[0] & 0x1) + err = -ETIMEDOUT; +out: + kfree(reg_buf); + return err; +} + +static int sd_enable_cache(struct mmc_card *card) +{ + u8 *reg_buf; + int err; + + reg_buf = kzalloc(512, GFP_KERNEL); + if (!reg_buf) + return -ENOMEM; + + /* + * Set the Cache Enable bit in the performance enhancement register at + * 260 bytes offset. + */ + err = sd_write_ext_reg(card, card->ext_perf.fno, card->ext_perf.page, + card->ext_perf.offset + 260, 0x1); + if (err) { + pr_warn("%s: error %d writing Cache Enable bit\n", + mmc_hostname(card->host), err); + goto out; + } + + err = mmc_poll_for_busy(card, SD_WRITE_EXTR_SINGLE_TIMEOUT_MS, false, + MMC_BUSY_EXTR_SINGLE); + if (!err) + card->ext_perf.feature_enabled |= SD_EXT_PERF_CACHE; + +out: + kfree(reg_buf); + return err; +} + /* * Handle the detection and initialisation of a card. * @@ -1442,6 +1531,13 @@ static int mmc_sd_init_card(struct mmc_host *host, u32 ocr, goto free_card; } + /* Enable internal SD cache if supported. */ + if (card->ext_perf.feature_support & SD_EXT_PERF_CACHE) { + err = sd_enable_cache(card); + if (err) + goto free_card; + } + if (host->cqe_ops && !host->cqe_enabled) { err = host->cqe_ops->cqe_enable(host, card); if (!err) { @@ -1694,6 +1790,8 @@ static const struct mmc_bus_ops mmc_sd_ops = { .alive = mmc_sd_alive, .shutdown = mmc_sd_suspend, .hw_reset = mmc_sd_hw_reset, + .cache_enabled = sd_cache_enabled, + .flush_cache = sd_flush_cache, }; /* diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h index 2867af0635f8..74e6c0624d27 100644 --- a/include/linux/mmc/card.h +++ b/include/linux/mmc/card.h @@ -196,6 +196,7 @@ struct sd_ext_reg { u8 page; u16 offset; u8 rev; + u8 feature_enabled; u8 feature_support; /* Power Management Function. */ #define SD_EXT_POWER_OFF_NOTIFY (1<<0)
In SD spec v6.x the SD function extension registers for performance enhancements were introduced. As a part of this an optional internal cache on the SD card, can be used to improve performance. The let the SD card use the cache, the host needs to enable it and manage flushing of the cache, so let's add support for this. Note that for an SD card supporting the cache it's mandatory for it, to also support the poweroff notification feature. According to the SD spec, if the cache has been enabled and a poweroff notification is sent to the card, that implicitly also means that the card should flush its internal cache. Therefore, dealing with cache flushing for REQ_OP_FLUSH block requests is sufficient. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> --- drivers/mmc/core/mmc_ops.c | 1 + drivers/mmc/core/mmc_ops.h | 1 + drivers/mmc/core/sd.c | 98 ++++++++++++++++++++++++++++++++++++++ include/linux/mmc/card.h | 1 + 4 files changed, 101 insertions(+) -- 2.25.1