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[v5,00/31] target/arm: enforce alignment

Message ID 20210419202257.161730-1-richard.henderson@linaro.org
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Series target/arm: enforce alignment | expand

Message

Richard Henderson April 19, 2021, 8:22 p.m. UTC 
Based-on: 20210416183106.1516563-1-richard.henderson@linaro.org
("[PATCH v5 for-6.1 0/9] target/arm mte fixes")

Changes for v5:
  * Address review issues.
  * Use cpu_abort in assert_hflags_rebuild_correctly

The only patch lacking review is the new one:
07-target-arm-Use-cpu_abort-in-assert_hflags_rebuild.patch


r~


Richard Henderson (31):
  target/arm: Fix decode of align in VLDST_single
  target/arm: Rename TBFLAG_A32, SCTLR_B
  target/arm: Rename TBFLAG_ANY, PSTATE_SS
  target/arm: Add wrapper macros for accessing tbflags
  target/arm: Introduce CPUARMTBFlags
  target/arm: Move mode specific TB flags to tb->cs_base
  target/arm: Use cpu_abort in assert_hflags_rebuild_correctly
  target/arm: Move TBFLAG_AM32 bits to the top
  target/arm: Move TBFLAG_ANY bits to the bottom
  target/arm: Add ALIGN_MEM to TBFLAG_ANY
  target/arm: Adjust gen_aa32_{ld,st}_i32 for align+endianness
  target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64
  target/arm: Fix SCTLR_B test for TCGv_i64 load/store
  target/arm: Adjust gen_aa32_{ld,st}_i64 for align+endianness
  target/arm: Enforce word alignment for LDRD/STRD
  target/arm: Enforce alignment for LDA/LDAH/STL/STLH
  target/arm: Enforce alignment for LDM/STM
  target/arm: Enforce alignment for RFE
  target/arm: Enforce alignment for SRS
  target/arm: Enforce alignment for VLDM/VSTM
  target/arm: Enforce alignment for VLDR/VSTR
  target/arm: Enforce alignment for VLDn (all lanes)
  target/arm: Enforce alignment for VLDn/VSTn (multiple)
  target/arm: Enforce alignment for VLDn/VSTn (single)
  target/arm: Use finalize_memop for aa64 gpr load/store
  target/arm: Use finalize_memop for aa64 fpr load/store
  target/arm: Enforce alignment for aa64 load-acq/store-rel
  target/arm: Use MemOp for size + endian in aa64 vector ld/st
  target/arm: Enforce alignment for aa64 vector LDn/STn (multiple)
  target/arm: Enforce alignment for aa64 vector LDn/STn (single)
  target/arm: Enforce alignment for sve LD1R

 target/arm/cpu.h                | 105 ++++++++-----
 target/arm/translate.h          |  38 +++++
 target/arm/neon-ls.decode       |   4 +-
 target/arm/helper-a64.c         |   2 +-
 target/arm/helper.c             | 163 ++++++++++----------
 target/arm/translate-a64.c      | 214 +++++++++++++-------------
 target/arm/translate-sve.c      |   2 +-
 target/arm/translate.c          | 258 +++++++++++++++++---------------
 target/arm/translate-neon.c.inc | 117 ++++++++++++---
 target/arm/translate-vfp.c.inc  |  20 +--
 10 files changed, 556 insertions(+), 367 deletions(-)

-- 
2.25.1

Comments

Peter Maydell April 20, 2021, 10:27 a.m. UTC | #1 
On Mon, 19 Apr 2021 at 21:24, Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> Based-on: 20210416183106.1516563-1-richard.henderson@linaro.org

> ("[PATCH v5 for-6.1 0/9] target/arm mte fixes")

>

> Changes for v5:

>   * Address review issues.

>   * Use cpu_abort in assert_hflags_rebuild_correctly

>

> The only patch lacking review is the new one:

> 07-target-arm-Use-cpu_abort-in-assert_hflags_rebuild.patch


I've applied all except for patch 7 to target-arm.next for 6.1.

thanks
-- PMM