| Message ID | 20210329194602.17049-5-digetx@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | NVIDIA Tegra memory improvements | expand |
On 29/03/2021 21:46, Dmitry Osipenko wrote: > Convert Tegra20 Memory Controller binding to schema. > > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Thanks for the patch! Please see a comment below. > --- > .../memory-controllers/nvidia,tegra20-mc.txt | 40 ---------- > .../memory-controllers/nvidia,tegra20-mc.yaml | 78 +++++++++++++++++++ > 2 files changed, 78 insertions(+), 40 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt > create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml > > diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt > deleted file mode 100644 > index 739b7c6f2e26..000000000000 > --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt > +++ /dev/null > @@ -1,40 +0,0 @@ > -NVIDIA Tegra20 MC(Memory Controller) > - > -Required properties: > -- compatible : "nvidia,tegra20-mc-gart" > -- reg : Should contain 2 register ranges: physical base address and length of > - the controller's registers and the GART aperture respectively. > -- clocks: Must contain an entry for each entry in clock-names. > - See ../clocks/clock-bindings.txt for details. > -- clock-names: Must include the following entries: > - - mc: the module's clock input > -- interrupts : Should contain MC General interrupt. > -- #reset-cells : Should be 1. This cell represents memory client module ID. > - The assignments may be found in header file <dt-bindings/memory/tegra20-mc.h> > - or in the TRM documentation. > -- #iommu-cells: Should be 0. This cell represents the number of cells in an > - IOMMU specifier needed to encode an address. GART supports only a single > - address space that is shared by all devices, therefore no additional > - information needed for the address encoding. > -- #interconnect-cells : Should be 1. This cell represents memory client. > - The assignments may be found in header file <dt-bindings/memory/tegra20-mc.h>. > - > -Example: > - mc: memory-controller@7000f000 { > - compatible = "nvidia,tegra20-mc-gart"; > - reg = <0x7000f000 0x400 /* controller registers */ > - 0x58000000 0x02000000>; /* GART aperture */ > - clocks = <&tegra_car TEGRA20_CLK_MC>; > - clock-names = "mc"; > - interrupts = <GIC_SPI 77 0x04>; > - #reset-cells = <1>; > - #iommu-cells = <0>; > - #interconnect-cells = <1>; > - }; > - > - video-codec@6001a000 { > - compatible = "nvidia,tegra20-vde"; > - ... > - resets = <&mc TEGRA20_MC_RESET_VDE>; > - iommus = <&mc>; > - }; > diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml > new file mode 100644 > index 000000000000..c5731fa41e83 > --- /dev/null > +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml > @@ -0,0 +1,78 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-mc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NVIDIA Tegra20 SoC Memory Controller > + > +maintainers: > + - Dmitry Osipenko <digetx@gmail.com> > + - Jon Hunter <jonathanh@nvidia.com> > + - Thierry Reding <thierry.reding@gmail.com> > + > +description: | > + The Tegra20 Memory Controller merges request streams from various client > + interfaces into request stream(s) for the various memory target devices, > + and returns response data to the various clients. The Memory Controller > + has a configurable arbitration algorithm to allow the user to fine-tune > + performance among the various clients. > + > + Tegra20 Memory Controller includes the GART (Graphics Address Relocation > + Table) which allows Memory Controller to provide a linear view of a > + fragmented memory pages. > + > +properties: > + compatible: > + const: nvidia,tegra20-mc-gart > + > + reg: > + minItems: 1 > + maxItems: 2 I think you always need two regs, don't you? If so, then better to use "description" like in Documentation/devicetree/bindings/example-schema.yaml to describe which set is for which range/purpose. Best regards, Krzysztof
On Mon, 29 Mar 2021 22:46:00 +0300, Dmitry Osipenko wrote: > Convert Tegra20 Memory Controller binding to schema. > > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- > .../memory-controllers/nvidia,tegra20-mc.txt | 40 ---------- > .../memory-controllers/nvidia,tegra20-mc.yaml | 78 +++++++++++++++++++ > 2 files changed, 78 insertions(+), 40 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt > create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: dtschema/dtc warnings/errors: Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.example.dt.yaml:0:0: /example-0/memory-controller@7000f000: failed to match any schema with compatible: ['nvidia,tegra20-mc'] See https://patchwork.ozlabs.org/patch/1459800 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
On Tue, Mar 30, 2021 at 08:08:43AM -0500, Rob Herring wrote: > On Mon, 29 Mar 2021 22:46:00 +0300, Dmitry Osipenko wrote: > > Convert Tegra20 Memory Controller binding to schema. > > > > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > > --- > > .../memory-controllers/nvidia,tegra20-mc.txt | 40 ---------- > > .../memory-controllers/nvidia,tegra20-mc.yaml | 78 +++++++++++++++++++ > > 2 files changed, 78 insertions(+), 40 deletions(-) > > delete mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt > > create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml > > > > My bot found errors running 'make dt_binding_check' on your patch: > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.example.dt.yaml:0:0: /example-0/memory-controller@7000f000: failed to match any schema with compatible: ['nvidia,tegra20-mc'] Yes, this is a new warning. It's off by default for dt_binding_check until we fix the existing warnings, but you can enable by adding 'DT_CHECKER_FLAGS=-m'. Support for this is in the dt/next branch. Rob
30.03.2021 11:37, Krzysztof Kozlowski пишет: >> +properties: >> + compatible: >> + const: nvidia,tegra20-mc-gart >> + >> + reg: >> + minItems: 1 >> + maxItems: 2 > I think you always need two regs, don't you? If so, then better to use > "description" like in > Documentation/devicetree/bindings/example-schema.yaml to describe which > set is for which range/purpose. I did this because the original example from the txt binding was failing with: Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.example.dt.yaml: memory-controller@7000f000: reg: [[1879109632, 1024, 1476395008, 33554432]] is too short But then I just corrected the example and forgot to change the reg entry. I'll fix it in v2, thanks.
30.03.2021 16:46, Rob Herring пишет: > On Tue, Mar 30, 2021 at 08:08:43AM -0500, Rob Herring wrote: >> On Mon, 29 Mar 2021 22:46:00 +0300, Dmitry Osipenko wrote: >>> Convert Tegra20 Memory Controller binding to schema. >>> >>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> >>> --- >>> .../memory-controllers/nvidia,tegra20-mc.txt | 40 ---------- >>> .../memory-controllers/nvidia,tegra20-mc.yaml | 78 +++++++++++++++++++ >>> 2 files changed, 78 insertions(+), 40 deletions(-) >>> delete mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt >>> create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml >>> >> >> My bot found errors running 'make dt_binding_check' on your patch: >> >> yamllint warnings/errors: >> >> dtschema/dtc warnings/errors: >> Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.example.dt.yaml:0:0: /example-0/memory-controller@7000f000: failed to match any schema with compatible: ['nvidia,tegra20-mc'] > > Yes, this is a new warning. It's off by default for dt_binding_check > until we fix the existing warnings, but you can enable by adding > 'DT_CHECKER_FLAGS=-m'. Support for this is in the dt/next branch. Thanks!
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt deleted file mode 100644 index 739b7c6f2e26..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt +++ /dev/null @@ -1,40 +0,0 @@ -NVIDIA Tegra20 MC(Memory Controller) - -Required properties: -- compatible : "nvidia,tegra20-mc-gart" -- reg : Should contain 2 register ranges: physical base address and length of - the controller's registers and the GART aperture respectively. -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - mc: the module's clock input -- interrupts : Should contain MC General interrupt. -- #reset-cells : Should be 1. This cell represents memory client module ID. - The assignments may be found in header file <dt-bindings/memory/tegra20-mc.h> - or in the TRM documentation. -- #iommu-cells: Should be 0. This cell represents the number of cells in an - IOMMU specifier needed to encode an address. GART supports only a single - address space that is shared by all devices, therefore no additional - information needed for the address encoding. -- #interconnect-cells : Should be 1. This cell represents memory client. - The assignments may be found in header file <dt-bindings/memory/tegra20-mc.h>. - -Example: - mc: memory-controller@7000f000 { - compatible = "nvidia,tegra20-mc-gart"; - reg = <0x7000f000 0x400 /* controller registers */ - 0x58000000 0x02000000>; /* GART aperture */ - clocks = <&tegra_car TEGRA20_CLK_MC>; - clock-names = "mc"; - interrupts = <GIC_SPI 77 0x04>; - #reset-cells = <1>; - #iommu-cells = <0>; - #interconnect-cells = <1>; - }; - - video-codec@6001a000 { - compatible = "nvidia,tegra20-vde"; - ... - resets = <&mc TEGRA20_MC_RESET_VDE>; - iommus = <&mc>; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml new file mode 100644 index 000000000000..c5731fa41e83 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-mc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra20 SoC Memory Controller + +maintainers: + - Dmitry Osipenko <digetx@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + - Thierry Reding <thierry.reding@gmail.com> + +description: | + The Tegra20 Memory Controller merges request streams from various client + interfaces into request stream(s) for the various memory target devices, + and returns response data to the various clients. The Memory Controller + has a configurable arbitration algorithm to allow the user to fine-tune + performance among the various clients. + + Tegra20 Memory Controller includes the GART (Graphics Address Relocation + Table) which allows Memory Controller to provide a linear view of a + fragmented memory pages. + +properties: + compatible: + const: nvidia,tegra20-mc-gart + + reg: + minItems: 1 + maxItems: 2 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: mc + + interrupts: + maxItems: 1 + + "#reset-cells": + const: 1 + + "#iommu-cells": + const: 0 + + "#interconnect-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - "#reset-cells" + - "#iommu-cells" + - "#interconnect-cells" + +additionalProperties: false + +examples: + - | + memory-controller@7000f000 { + compatible = "nvidia,tegra20-mc"; + reg = <0x7000f000 0x400>, /* Controller registers */ + <0x58000000 0x02000000>; /* GART aperture */ + clocks = <&clock_controller 32>; + clock-names = "mc"; + + interrupts = <0 77 4>; + + #iommu-cells = <0>; + #reset-cells = <1>; + #interconnect-cells = <1>; + };
Convert Tegra20 Memory Controller binding to schema. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- .../memory-controllers/nvidia,tegra20-mc.txt | 40 ---------- .../memory-controllers/nvidia,tegra20-mc.yaml | 78 +++++++++++++++++++ 2 files changed, 78 insertions(+), 40 deletions(-) delete mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml