mbox series

[net-next,v4,0/2] axienet clock additions

Message ID 20210326000438.2292548-1-robert.hancock@calian.com
Headers show
Series axienet clock additions | expand

Message

Robert Hancock March 26, 2021, 12:04 a.m. UTC 
Add support to the axienet driver for controlling all of the clocks that
the logic core may utilize.

Changed since v3:
-Added Acked-by to patch 1
-Now applies to net-next tree after earlier patches merged in - code
unchanged from v3

Changed since v2:
-Additional clock description clarification

Changed since v1:
-Clarified clock usages in documentation and code comments

Robert Hancock (2):
  dt-bindings: net: xilinx_axienet: Document additional clocks
  net: axienet: Enable more clocks

 .../bindings/net/xilinx_axienet.txt           | 25 ++++++++++----
 drivers/net/ethernet/xilinx/xilinx_axienet.h  |  8 +++--
 .../net/ethernet/xilinx/xilinx_axienet_main.c | 34 +++++++++++++++----
 .../net/ethernet/xilinx/xilinx_axienet_mdio.c |  4 +--
 4 files changed, 54 insertions(+), 17 deletions(-)

Comments

Andrew Lunn March 26, 2021, 12:12 p.m. UTC | #1 
On Thu, Mar 25, 2021 at 06:04:37PM -0600, Robert Hancock wrote:
> Update DT bindings to describe all of the clocks that the axienet
> driver will now be able to make use of.
> 
> Acked-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Robert Hancock <robert.hancock@calian.com>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew
Andrew Lunn March 26, 2021, 12:14 p.m. UTC | #2 
On Thu, Mar 25, 2021 at 06:04:38PM -0600, Robert Hancock wrote:
> This driver was only enabling the first clock on the device, regardless
> of its name. However, this controller logic can have multiple clocks
> which should all be enabled. Add support for enabling additional clocks.
> The clock names used are matching those used in the Xilinx version of this
> driver as well as the Xilinx device tree generator, except for mgt_clk
> which is not present there.
> 
> For backward compatibility, if no named clocks are present, the first
> clock present is used for determining the MDIO bus clock divider.
> 
> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
> Signed-off-by: Robert Hancock <robert.hancock@calian.com>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew
patchwork-bot+netdevbpf@kernel.org March 26, 2021, 11 p.m. UTC | #3 
Hello:

This series was applied to netdev/net-next.git (refs/heads/master):

On Thu, 25 Mar 2021 18:04:36 -0600 you wrote:
> Add support to the axienet driver for controlling all of the clocks that
> the logic core may utilize.
> 
> Changed since v3:
> -Added Acked-by to patch 1
> -Now applies to net-next tree after earlier patches merged in - code
> unchanged from v3
> 
> [...]

Here is the summary with links:
  - [net-next,v4,1/2] dt-bindings: net: xilinx_axienet: Document additional clocks
    https://git.kernel.org/netdev/net-next/c/a0e55dcd2fa9
  - [net-next,v4,2/2] net: axienet: Enable more clocks
    https://git.kernel.org/netdev/net-next/c/b11bfb9a19f9

You are awesome, thank you!
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