[RFT,v3,16/27] irqchip/apple-aic: Add support for the Apple Interrupt Controller

This is the root interrupt controller used on Apple ARM SoCs such as the
M1. This irqchip driver performs multiple functions:

* Handles both IRQs and FIQs

* Drives the AIC peripheral itself (which handles IRQs)

* Dispatches FIQs to downstream hard-wired clients (currently the ARM
  timer).

* Implements a virtual IPI multiplexer to funnel multiple Linux IPIs
  into a single hardware IPI

Signed-off-by: Hector Martin <marcan@marcan.st>
---
 MAINTAINERS                     |   2 +
 drivers/irqchip/Kconfig         |   8 +
 drivers/irqchip/Makefile        |   1 +
 drivers/irqchip/irq-apple-aic.c | 710 ++++++++++++++++++++++++++++++++
 include/linux/cpuhotplug.h      |   1 +
 5 files changed, 722 insertions(+)
 create mode 100644 drivers/irqchip/irq-apple-aic.c

On Fri, 05 Mar 2021 15:05:08 +0000,
Andy Shevchenko <andy.shevchenko@gmail.com> wrote:

[...]

> > +#define TIMER_FIRING(x)                                                        \
> > +       (((x) & (ARCH_TIMER_CTRL_ENABLE | ARCH_TIMER_CTRL_IT_MASK |            \
> > +                ARCH_TIMER_CTRL_IT_STAT)) ==                                  \
> > +        (ARCH_TIMER_CTRL_ENABLE | ARCH_TIMER_CTRL_IT_STAT))
> 
> It's a bit hard to read. Perhaps
> 
> #define FOO_MASK  (_ENABLE | _STAT)
> #define _FIRING ... (FOO_MASK | _MASK == FOO_MASK)

The expression above is a direct translation of the architecture
reference manual, and I'd rather not have that hidden behind a bunch
of obscure macros.

[...]

> > +       irqc->hw_domain = irq_domain_create_linear(of_node_to_fwnode(node),
> > +                                                  irqc->nr_hw + AIC_NR_FIQ,
> > +                                                  &aic_irq_domain_ops, irqc);
> 
> If you are sure it will be always OF-only, why not to use
> irq_domain_add_linear()?

The OF-only API is deprecated, and there is no point in using it for
*new* code, specially when things like IPI allocation require the use
of the modern API. For arm64 root controllers, that's the way to go.

Thanks,

	M.

On Thu, 04 Mar 2021 21:38:51 +0000,
Hector Martin <marcan@marcan.st> wrote:
> 

> This is the root interrupt controller used on Apple ARM SoCs such as the

> M1. This irqchip driver performs multiple functions:

> 

> * Handles both IRQs and FIQs

> 

> * Drives the AIC peripheral itself (which handles IRQs)

> 

> * Dispatches FIQs to downstream hard-wired clients (currently the ARM

>   timer).

> 

> * Implements a virtual IPI multiplexer to funnel multiple Linux IPIs

>   into a single hardware IPI

>


[...]

> Signed-off-by: Hector Martin <marcan@marcan.st>

> +static void __exception_irq_entry aic_handle_irq(struct pt_regs *regs)

> +{

> +	struct aic_irq_chip *ic = aic_irqc;

> +	u32 event, type, irq;

> +

> +	do {

> +		/*

> +		 * We cannot use a relaxed read here, as DMA needs to be

> +		 * ordered with respect to the IRQ firing.

> +		 */

> +		event = readl(ic->base + AIC_EVENT);

> +		type = FIELD_GET(AIC_EVENT_TYPE, event);

> +		irq = FIELD_GET(AIC_EVENT_NUM, event);

> +

> +		if (type == AIC_EVENT_TYPE_HW)

> +			handle_domain_irq(aic_irqc->hw_domain, irq, regs);

> +		else if (type == AIC_EVENT_TYPE_IPI && irq == 1)

> +			aic_handle_ipi(regs);

> +		else if (event != 0)

> +			pr_err("Unknown IRQ event %d, %d\n", type, irq);

> +	} while (event);

> +

> +	/*

> +	 * vGIC maintenance interrupts end up here too, so we need to check

> +	 * for them separately. Just report and disable vGIC for now, until

> +	 * we implement this properly.

> +	 */

> +	if ((read_sysreg_s(SYS_ICH_HCR_EL2) & ICH_HCR_EN) &&

> +		read_sysreg_s(SYS_ICH_MISR_EL2) != 0) {

> +		pr_err("vGIC IRQ fired, disabling.\n");


Please add a _ratelimited here. Whilst debugging KVM on this machine,
I ended up with this firing at such a rate that it was impossible to
do anything useful. Ratelimiting it allowed me to pinpoint the
problem.

[...]

> +/*

> + * FIQ irqchip

> + */

> +

> +static void aic_fiq_mask(struct irq_data *d)

> +{

> +	/* Only the guest timers have real mask bits, unfortunately. */

> +	switch (d->hwirq) {

> +	case AIC_TMR_GUEST_PHYS:

> +		sysreg_clear_set_s(SYS_APL_VM_TMR_FIQ_ENA_EL1, VM_TMR_FIQ_ENABLE_P, 0);

> +		break;

> +	case AIC_TMR_GUEST_VIRT:

> +		sysreg_clear_set_s(SYS_APL_VM_TMR_FIQ_ENA_EL1, VM_TMR_FIQ_ENABLE_V, 0);

> +		break;

> +	}

> +}

> +

> +static void aic_fiq_unmask(struct irq_data *d)

> +{

> +	switch (d->hwirq) {

> +	case AIC_TMR_GUEST_PHYS:

> +		sysreg_clear_set_s(SYS_APL_VM_TMR_FIQ_ENA_EL1, 0, VM_TMR_FIQ_ENABLE_P);

> +		break;

> +	case AIC_TMR_GUEST_VIRT:

> +		sysreg_clear_set_s(SYS_APL_VM_TMR_FIQ_ENA_EL1, 0, VM_TMR_FIQ_ENABLE_V);

> +		break;

> +	}

> +}

> +

> +static void aic_fiq_eoi(struct irq_data *d)

> +{

> +	/* We mask to ack (where we can), so we need to unmask at EOI. */

> +	if (!irqd_irq_disabled(d) && !irqd_irq_masked(d))


Ah, be careful here: irqd_irq_masked() doesn't do what you think it
does for per-CPU interrupts. It's been on my list to fix for the rVIC
implementation, but I never got around to doing it, and all decent ICs
hide this from SW by having a HW-managed mask, similar to what is on
the IRQ side.

I can see two possibilities:

- you can track the masked state directly and use that instead of
  these predicates

- you can just drop the masking altogether as this is only useful to a
  hosted hypervisor (KVM), which will have to do its own masking
  behind the scenes anyway

> +		aic_fiq_unmask(d);

> +}

> +


The rest looks good to me.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

Hi Hector,

Sorry it took me so long to get to this. Some comments below.

On Fri, Mar 05, 2021 at 06:38:51AM +0900, Hector Martin wrote:
> This is the root interrupt controller used on Apple ARM SoCs such as the
> M1. This irqchip driver performs multiple functions:
> 
> * Handles both IRQs and FIQs
> 
> * Drives the AIC peripheral itself (which handles IRQs)
> 
> * Dispatches FIQs to downstream hard-wired clients (currently the ARM
>   timer).
> 
> * Implements a virtual IPI multiplexer to funnel multiple Linux IPIs
>   into a single hardware IPI
> 
> Signed-off-by: Hector Martin <marcan@marcan.st>
> ---
>  MAINTAINERS                     |   2 +
>  drivers/irqchip/Kconfig         |   8 +
>  drivers/irqchip/Makefile        |   1 +
>  drivers/irqchip/irq-apple-aic.c | 710 ++++++++++++++++++++++++++++++++
>  include/linux/cpuhotplug.h      |   1 +
>  5 files changed, 722 insertions(+)
>  create mode 100644 drivers/irqchip/irq-apple-aic.c

[...]

> + * Implementation notes:
> + *
> + * - This driver creates two IRQ domains, one for HW IRQs and internal FIQs,
> + *   and one for IPIs.
> + * - Since Linux needs more than 2 IPIs, we implement a software IRQ controller
> + *   and funnel all IPIs into one per-CPU IPI (the second "self" IPI is unused).
> + * - FIQ hwirq numbers are assigned after true hwirqs, and are per-cpu.
> + * - DT bindings use 3-cell form (like GIC):
> + *   - <0 nr flags> - hwirq #nr
> + *   - <1 nr flags> - FIQ #nr
> + *     - nr=0  Physical HV timer
> + *     - nr=1  Virtual HV timer
> + *     - nr=2  Physical guest timer
> + *     - nr=3  Virtual guest timer
> + *
> + */
> +
> +#define pr_fmt(fmt) "%s: " fmt, __func__

General nit: but I suspect many of the prints in here probably want to be
using the *_ratelimited variants.

> +static void __exception_irq_entry aic_handle_irq(struct pt_regs *regs)
> +{
> +	struct aic_irq_chip *ic = aic_irqc;
> +	u32 event, type, irq;
> +
> +	do {
> +		/*
> +		 * We cannot use a relaxed read here, as DMA needs to be
> +		 * ordered with respect to the IRQ firing.
> +		 */

I think this could be a bit clearer: the readl() doesn't order any DMA
accesses, but instead means that subsequent reads by the CPU are ordered
(which may be from a buffer which was DMA'd to) are ordered after the
read of the MMIO register.

> +		event = readl(ic->base + AIC_EVENT);
> +		type = FIELD_GET(AIC_EVENT_TYPE, event);
> +		irq = FIELD_GET(AIC_EVENT_NUM, event);
> +
> +		if (type == AIC_EVENT_TYPE_HW)
> +			handle_domain_irq(aic_irqc->hw_domain, irq, regs);
> +		else if (type == AIC_EVENT_TYPE_IPI && irq == 1)
> +			aic_handle_ipi(regs);
> +		else if (event != 0)
> +			pr_err("Unknown IRQ event %d, %d\n", type, irq);
> +	} while (event);
> +
> +	/*
> +	 * vGIC maintenance interrupts end up here too, so we need to check
> +	 * for them separately. Just report and disable vGIC for now, until
> +	 * we implement this properly.
> +	 */
> +	if ((read_sysreg_s(SYS_ICH_HCR_EL2) & ICH_HCR_EN) &&
> +		read_sysreg_s(SYS_ICH_MISR_EL2) != 0) {
> +		pr_err("vGIC IRQ fired, disabling.\n");
> +		sysreg_clear_set_s(SYS_ICH_HCR_EL2, ICH_HCR_EN, 0);
> +	}

What prevents all these system register accesses being speculated up before
the handler?

> +}
> +
> +static int aic_irq_set_affinity(struct irq_data *d,
> +				const struct cpumask *mask_val, bool force)
> +{
> +	irq_hw_number_t hwirq = irqd_to_hwirq(d);
> +	struct aic_irq_chip *ic = irq_data_get_irq_chip_data(d);
> +	int cpu;
> +
> +	if (hwirq > ic->nr_hw)
> +		return -EINVAL;
> +
> +	if (force)
> +		cpu = cpumask_first(mask_val);
> +	else
> +		cpu = cpumask_any_and(mask_val, cpu_online_mask);
> +
> +	aic_ic_write(ic, AIC_TARGET_CPU + hwirq * 4, BIT(cpu));
> +	irq_data_update_effective_affinity(d, cpumask_of(cpu));
> +
> +	return IRQ_SET_MASK_OK;
> +}
> +
> +static int aic_irq_set_type(struct irq_data *d, unsigned int type)
> +{
> +	return (type == IRQ_TYPE_LEVEL_HIGH) ? 0 : -EINVAL;
> +}
> +
> +static struct irq_chip aic_chip = {
> +	.name = "AIC",
> +	.irq_mask = aic_irq_mask,
> +	.irq_unmask = aic_irq_unmask,

I know these are driven by the higher-level irq chip code, but I'm a bit
confused as to what provides ordering if, e.g. something ends up calling:

	aic_chip.irq_mask(d);
	...
	aic_chip.irq_unmask(d);

I can't see any ISBs in here and they're writing to two different registers,
so can we end up with the IRQ masked after this sequence?

> +/*
> + * IPI irqchip
> + */
> +
> +static void aic_ipi_mask(struct irq_data *d)
> +{
> +	u32 irq_bit = BIT(irqd_to_hwirq(d));
> +	int this_cpu = smp_processor_id();
> +
> +	/* No specific ordering requirements needed here. */
> +	atomic_andnot(irq_bit, &aic_vipi_enable[this_cpu]);
> +}

Why not use a per-cpu variable here instead of an array of atomics? The pcpu
API has things for atomic updates (e.g. or, and, xchg).

> +static void aic_ipi_unmask(struct irq_data *d)
> +{
> +	struct aic_irq_chip *ic = irq_data_get_irq_chip_data(d);
> +	u32 irq_bit = BIT(irqd_to_hwirq(d));
> +	int this_cpu = smp_processor_id();
> +
> +	/*
> +	 * This must complete before the atomic_read_acquire() below to avoid
> +	 * racing aic_ipi_send_mask(). Use a dummy fetch op with release
> +	 * semantics for this. This is arch-specific: ARMv8 B2.3.3 specifies
> +	 * that writes with Release semantics are Barrier-ordered-before reads
> +	 * with Acquire semantics, even though the Linux arch-independent
> +	 * definition of these atomic ops does not.
> +	 */

I think a more idiomatic (and portable) way to do this would be to use
the relaxed accessors, but with smp_mb__after_atomic() between them. Do you
have a good reason for _not_ doing it like that?

> +	(void)atomic_fetch_or_release(irq_bit, &aic_vipi_enable[this_cpu]);
> +
> +	/*
> +	 * If a pending vIPI was unmasked, raise a HW IPI to ourselves.
> +	 * No barriers needed here since this is a self-IPI.
> +	 */
> +	if (atomic_read_acquire(&aic_vipi_flag[this_cpu]) & irq_bit)

"No barriers needed here" right before an acquire is confusing ;)

> +		aic_ic_write(ic, AIC_IPI_SEND, AIC_IPI_SEND_CPU(this_cpu));
> +}
> +
> +static void aic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask)
> +{
> +	struct aic_irq_chip *ic = irq_data_get_irq_chip_data(d);
> +	u32 irq_bit = BIT(irqd_to_hwirq(d));
> +	u32 send = 0;
> +	int cpu;
> +	unsigned long pending;
> +
> +	for_each_cpu(cpu, mask) {
> +		/*
> +		 * This sequence is the mirror of the one in aic_ipi_unmask();
> +		 * see the comment there. Additionally, release semantics
> +		 * ensure that the vIPI flag set is ordered after any shared
> +		 * memory accesses that precede it. This therefore also pairs
> +		 * with the atomic_fetch_andnot in aic_handle_ipi().
> +		 */
> +		pending = atomic_fetch_or_release(irq_bit, &aic_vipi_flag[cpu]);

(same here)

> +		if (!(pending & irq_bit) && (atomic_read_acquire(&aic_vipi_enable[cpu]) & irq_bit))
> +			send |= AIC_IPI_SEND_CPU(cpu);
> +	}
> +
> +	/*
> +	 * The flag writes must complete before the physical IPI is issued
> +	 * to another CPU. This is implied by the control dependency on
> +	 * the result of atomic_read_acquire() above, which is itself
> +	 * already ordered after the vIPI flag write.
> +	 */
> +	if (send)
> +		aic_ic_write(ic, AIC_IPI_SEND, send);
> +}
> +
> +static struct irq_chip ipi_chip = {
> +	.name = "AIC-IPI",
> +	.irq_mask = aic_ipi_mask,
> +	.irq_unmask = aic_ipi_unmask,
> +	.ipi_send_mask = aic_ipi_send_mask,
> +};
> +
> +/*
> + * IPI IRQ domain
> + */
> +
> +static void aic_handle_ipi(struct pt_regs *regs)
> +{
> +	int this_cpu = smp_processor_id();
> +	int i;
> +	unsigned long enabled, firing;
> +
> +	/*
> +	 * Ack the IPI. We need to order this after the AIC event read, but
> +	 * that is enforced by normal MMIO ordering guarantees.
> +	 */
> +	aic_ic_write(aic_irqc, AIC_IPI_ACK, AIC_IPI_OTHER);
> +
> +	/*
> +	 * The mask read does not need to be ordered. Only we can change
> +	 * our own mask anyway, so no races are possible here, as long as
> +	 * we are properly in the interrupt handler (which is covered by
> +	 * the barrier that is part of the top-level AIC handler's readl()).
> +	 */
> +	enabled = atomic_read(&aic_vipi_enable[this_cpu]);
> +
> +	/*
> +	 * Clear the IPIs we are about to handle. This pairs with the
> +	 * atomic_fetch_or_release() in aic_ipi_send_mask(), and needs to be
> +	 * ordered after the aic_ic_write() above (to avoid dropping vIPIs) and
> +	 * before IPI handling code (to avoid races handling vIPIs before they
> +	 * are signaled). The former is taken care of by the release semantics
> +	 * of the write portion, while the latter is taken care of by the
> +	 * acquire semantics of the read portion.
> +	 */
> +	firing = atomic_fetch_andnot(enabled, &aic_vipi_flag[this_cpu]) & enabled;

Does this also need to be ordered after the Ack? For example, if we have
something like:

CPU 0						CPU 1
						<some other IPI>
aic_ipi_send_mask()
						atomic_fetch_andnot(flag)
	atomic_fetch_or_release(flag)
	aic_ic_write(AIC_IPI_SEND)
						aic_ic_write(AIC_IPI_ACK)

sorry if it's a stupid question, I'm just not sure about the cases in which
the hardware will pend things for you.

Will

On 08/03/2021 22.31, Marc Zyngier wrote:
>> +	if ((read_sysreg_s(SYS_ICH_HCR_EL2) & ICH_HCR_EN) &&

>> +		read_sysreg_s(SYS_ICH_MISR_EL2) != 0) {

>> +		pr_err("vGIC IRQ fired, disabling.\n");

> 

> Please add a _ratelimited here. Whilst debugging KVM on this machine,

> I ended up with this firing at such a rate that it was impossible to

> do anything useful. Ratelimiting it allowed me to pinpoint the

> problem.


Ouch. Done for v4.

>> +static void aic_fiq_eoi(struct irq_data *d)

>> +{

>> +	/* We mask to ack (where we can), so we need to unmask at EOI. */

>> +	if (!irqd_irq_disabled(d) && !irqd_irq_masked(d))

> 

> Ah, be careful here: irqd_irq_masked() doesn't do what you think it

> does for per-CPU interrupts. It's been on my list to fix for the rVIC

> implementation, but I never got around to doing it, and all decent ICs

> hide this from SW by having a HW-managed mask, similar to what is on

> the IRQ side.

> 

> I can see two possibilities:

> 

> - you can track the masked state directly and use that instead of

>    these predicates

> 

> - you can just drop the masking altogether as this is only useful to a

>    hosted hypervisor (KVM), which will have to do its own masking

>    behind the scenes anyway

> 


Since you're using the masking in KVM after all, I'm tracking the mask 
state in a percpu variable now. Also folded in your two minor bugfixes 
from the KVM series. Cheers!


-- 
Hector Martin (marcan@marcan.st)
Public Key: https://mrcn.st/pub

Hi Will,

No worries, I was busy until a couple days ago anyway.

On 25/03/2021 04.57, Will Deacon wrote:
>> +#define pr_fmt(fmt) "%s: " fmt, __func__

> 

> General nit: but I suspect many of the prints in here probably want to be

> using the *_ratelimited variants.


You're right, everything complaining about spurious/unsupported stuff is 
probably safer rate-limited. I also made them all pr_err_ratelimited, 
since nothing should be trying to use that hardware before we get around 
to supporting it in this driver.

>> +static void __exception_irq_entry aic_handle_irq(struct pt_regs *regs)

>> +{

>> +	struct aic_irq_chip *ic = aic_irqc;

>> +	u32 event, type, irq;

>> +

>> +	do {

>> +		/*

>> +		 * We cannot use a relaxed read here, as DMA needs to be

>> +		 * ordered with respect to the IRQ firing.

>> +		 */

> 

> I think this could be a bit clearer: the readl() doesn't order any DMA

> accesses, but instead means that subsequent reads by the CPU are ordered

> (which may be from a buffer which was DMA'd to) are ordered after the

> read of the MMIO register.


Good point, reworded it for v4:

/*
  * We cannot use a relaxed read here, as reads from DMA buffers
  * need to be ordered after the IRQ fires.
  */

> 

>> +		event = readl(ic->base + AIC_EVENT);

>> +		type = FIELD_GET(AIC_EVENT_TYPE, event);

>> +		irq = FIELD_GET(AIC_EVENT_NUM, event);

>> +

>> +		if (type == AIC_EVENT_TYPE_HW)

>> +			handle_domain_irq(aic_irqc->hw_domain, irq, regs);

>> +		else if (type == AIC_EVENT_TYPE_IPI && irq == 1)

>> +			aic_handle_ipi(regs);

>> +		else if (event != 0)

>> +			pr_err("Unknown IRQ event %d, %d\n", type, irq);

>> +	} while (event);

>> +

>> +	/*

>> +	 * vGIC maintenance interrupts end up here too, so we need to check

>> +	 * for them separately. Just report and disable vGIC for now, until

>> +	 * we implement this properly.

>> +	 */

>> +	if ((read_sysreg_s(SYS_ICH_HCR_EL2) & ICH_HCR_EN) &&

>> +		read_sysreg_s(SYS_ICH_MISR_EL2) != 0) {

>> +		pr_err("vGIC IRQ fired, disabling.\n");

>> +		sysreg_clear_set_s(SYS_ICH_HCR_EL2, ICH_HCR_EN, 0);

>> +	}

> 

> What prevents all these system register accesses being speculated up before

> the handler?


Nothing, but that's not a problem, is it? If the condition is met, it 
means the vGIC IRQ *is* firing and needs clearing. We don't particularly 
care if this happens before, after, or during the rest of the IRQ handling.

I changed the message to this, because we actually should never hit this 
path with correctly-working KVM code (it takes care of it before this 
handler runs):

pr_err_ratelimited("vGIC IRQ fired and not handled by KVM, disabling.\n");

>> +static struct irq_chip aic_chip = {

>> +	.name = "AIC",

>> +	.irq_mask = aic_irq_mask,

>> +	.irq_unmask = aic_irq_unmask,

> 

> I know these are driven by the higher-level irq chip code, but I'm a bit

> confused as to what provides ordering if, e.g. something ends up calling:

> 

> 	aic_chip.irq_mask(d);

> 	...

> 	aic_chip.irq_unmask(d);

> 

> I can't see any ISBs in here and they're writing to two different registers,

> so can we end up with the IRQ masked after this sequence?


Wait, aren't MMIO writes to the same peripheral using device-nGnRnE 
memory modes always ordered with respect to each other? I thought the 
_relaxed versions were only trouble when mixed with memory/DMA buffers, 
and MMIO for any given peripheral always takes effect in program order.

>> +static void aic_ipi_mask(struct irq_data *d)

>> +{

>> +	u32 irq_bit = BIT(irqd_to_hwirq(d));

>> +	int this_cpu = smp_processor_id();

>> +

>> +	/* No specific ordering requirements needed here. */

>> +	atomic_andnot(irq_bit, &aic_vipi_enable[this_cpu]);

>> +}

> 

> Why not use a per-cpu variable here instead of an array of atomics? The pcpu

> API has things for atomic updates (e.g. or, and, xchg).


One CPU still needs to be able to mutate the flags of another CPU to 
fire an IPI; AIUI the per-cpu ops are *not* atomic for concurrent access 
by multiple CPUs, and in fact there is no API for that, only for "this CPU".

>> +static void aic_ipi_unmask(struct irq_data *d)

>> +{

>> +	struct aic_irq_chip *ic = irq_data_get_irq_chip_data(d);

>> +	u32 irq_bit = BIT(irqd_to_hwirq(d));

>> +	int this_cpu = smp_processor_id();

>> +

>> +	/*

>> +	 * This must complete before the atomic_read_acquire() below to avoid

>> +	 * racing aic_ipi_send_mask(). Use a dummy fetch op with release

>> +	 * semantics for this. This is arch-specific: ARMv8 B2.3.3 specifies

>> +	 * that writes with Release semantics are Barrier-ordered-before reads

>> +	 * with Acquire semantics, even though the Linux arch-independent

>> +	 * definition of these atomic ops does not.

>> +	 */

> 

> I think a more idiomatic (and portable) way to do this would be to use

> the relaxed accessors, but with smp_mb__after_atomic() between them. Do you

> have a good reason for _not_ doing it like that?


Not particularly, other than symmetry with the case below.

>> +		/*

>> +		 * This sequence is the mirror of the one in aic_ipi_unmask();

>> +		 * see the comment there. Additionally, release semantics

>> +		 * ensure that the vIPI flag set is ordered after any shared

>> +		 * memory accesses that precede it. This therefore also pairs

>> +		 * with the atomic_fetch_andnot in aic_handle_ipi().

>> +		 */

>> +		pending = atomic_fetch_or_release(irq_bit, &aic_vipi_flag[cpu]);


We do need the return data here, and the release semantics (or another 
barrier before it). But the read below can be made relaxed and a barrier 
used instead, and then the same patern above except with a plain 
atomic_or().

>> +		if (!(pending & irq_bit) && (atomic_read_acquire(&aic_vipi_enable[cpu]) & irq_bit))

>> +			send |= AIC_IPI_SEND_CPU(cpu);

>> +	}


[...]

>> +	/*

>> +	 * Clear the IPIs we are about to handle. This pairs with the

>> +	 * atomic_fetch_or_release() in aic_ipi_send_mask(), and needs to be

>> +	 * ordered after the aic_ic_write() above (to avoid dropping vIPIs) and

>> +	 * before IPI handling code (to avoid races handling vIPIs before they

>> +	 * are signaled). The former is taken care of by the release semantics

>> +	 * of the write portion, while the latter is taken care of by the

>> +	 * acquire semantics of the read portion.

>> +	 */

>> +	firing = atomic_fetch_andnot(enabled, &aic_vipi_flag[this_cpu]) & enabled;

> 

> Does this also need to be ordered after the Ack? For example, if we have

> something like:

> 

> CPU 0						CPU 1

> 						<some other IPI>

> aic_ipi_send_mask()

> 						atomic_fetch_andnot(flag)

> 	atomic_fetch_or_release(flag)

> 	aic_ic_write(AIC_IPI_SEND)

> 						aic_ic_write(AIC_IPI_ACK)

> 

> sorry if it's a stupid question, I'm just not sure about the cases in which

> the hardware will pend things for you.


It is ordered, right? As the comment says, it "needs to be ordered after 
the aic_ic_write() above". atomic_fetch_andnot() is *supposed* to be 
fully ordered and that should include against the writel_relaxed() on 
AIC_IPI_FLAG. On ARM it turns out it's not quite fully ordered, but the 
acquire semantics of the read half are sufficient for this case, as they 
guarantee the flags are always read after the FIQ has been ACKed.

Cheeers,
-- 
Hector Martin (marcan@marcan.st)
Public Key: https://mrcn.st/pub

Hi Will,

On 29/03/2021 21.04, Will Deacon wrote:
>> One CPU still needs to be able to mutate the flags of another CPU to fire an

>> IPI; AIUI the per-cpu ops are *not* atomic for concurrent access by multiple

>> CPUs, and in fact there is no API for that, only for "this CPU".

> 

> Huh, I really thought we had an API for that, but you're right. Oh well! But

> I'd still suggest a per-cpu atomic_t in that case, rather than the array.


Yeah, after digging into the per-cpu stuff earlier and understanding how 
it works, I agree that a per-cpu atomic makes sense here. Switched it to 
that (which simplified out a bunch of smp_processor_id() calls too). Thanks!

>>> I think a more idiomatic (and portable) way to do this would be to use

>>> the relaxed accessors, but with smp_mb__after_atomic() between them. Do you

>>> have a good reason for _not_ doing it like that?

>>

>> Not particularly, other than symmetry with the case below.

> 

> I think it would be better not to rely on arm64-specific ordering unless

> there's a good reason to.


Sounds reasonable, I'll switch to the barrier version.

>> We do need the return data here, and the release semantics (or another

>> barrier before it). But the read below can be made relaxed and a barrier

>> used instead, and then the same patern above except with a plain

>> atomic_or().

> 

> Yes, I think using atomic_fetch_or() followed by atomic_read() would be

> best (obviously with the relevant comments!)


atomic_fetch_or_release is sufficient here (atomic_fetch_or is stronger; 
atomic_fetch_or_relaxed would not be strong enough as this needs to be 
ordered after any writes prior to sending the IPI; in this case release 
semantics also make logical sense).

>> It is ordered, right? As the comment says, it "needs to be ordered after the

>> aic_ic_write() above". atomic_fetch_andnot() is *supposed* to be fully

>> ordered and that should include against the writel_relaxed() on

>> AIC_IPI_FLAG. On ARM it turns out it's not quite fully ordered, but the

>> acquire semantics of the read half are sufficient for this case, as they

>> guarantee the flags are always read after the FIQ has been ACKed.

> 

> Sorry, I missed that the answer to my question was already written in the

> comment. However, I'm still a bit unsure about whether the memory barriers

> give you what you need here. The barrier in atomic_fetch_andnot() will

> order the previous aic_ic_write(AIC_IPI_ACK) for the purposes of other

> CPUs reading those locations, but it doesn't say anything about when the

> interrupt controller actually changes state after the Ack.

> 

> Given that the AIC is mapped Device-nGnRnE, the Arm ARM offers:

> 

>    | Additionally, for Device-nGnRnE memory, a read or write of a Location

>    | in a Memory-mapped peripheral that exhibits side-effects is complete

>    | only when the read or write both:

>    |

>    | * Can begin to affect the state of the Memory-mapped peripheral.

>    | * Can trigger all associated side-effects, whether they affect other

>    |   peripheral devices, PEs, or memory.

> 

> so without AIC documentation I can't tell whether completion of the Ack write

> just begins the process of an Ack (in which case we might need something like

> a read-back), or whether the write response back from the AIC only occurs once

> the Ack has taken effect. Any ideas?


Ahh, you're talking about latency within AIC itself... I obviously don't 
have an authoritative answer to this, though the hardware designer in me 
wants to say this really ought to be single-cycle type stuff that isn't 
internally pipelined in a way that would create races.

I tried to set up an SMP test case for the atomic-to-AIC sequence in 
m1n1, but unfortunately I couldn't hit the race window in deliberately 
racy code (i.e. ack after clearing flags) without widening it even 
further with at least one dummy load in between, and of course I didn't 
experience any races with the proper code either.

What I can say is that a simple set IPI; ack IPI (in adjacent str 
instructions) sequence always yields a cleared IPI, and the converse 
always yields a set IPI. So if there is latency to the operations it 
seems it would at least be the same for sets and acks and would imply 
readbacks block, which should still yield equivalently correct results. 
But of course this is a single-CPU test, so it is not fully 
representative of what could happen in an SMP scenario.

At this point all I can say is I'm inclined to shrug and say we have no 
evidence of this being something that can happen, and it shouldn't in 
sane hardware, and hope for the best :-)

Thanks,
-- 
Hector Martin (marcan@marcan.st)
Public Key: https://mrcn.st/pub