diff mbox

[v2,09/18] omap_gpmc: Fix handling of FIFOTHRESHOLDSTATUS bit

Message ID 1314550628-26869-11-git-send-email-peter.maydell@linaro.org
State Accepted
Commit de8af7fe0158493baa1c9a5418ac598a18e86027
Headers show

Commit Message

Peter Maydell Aug. 28, 2011, 4:56 p.m. UTC
The OMAP3 TRM is inconsistent about whether the GPMC FIFOTHRESHOLDSTATUS
bit should be set when FIFOPOINTER > FIFOTHRESHOLD or when it is >=
FIFOTHRESHOLD. Apparently the underlying functional spec from which
the TRM was created states that the behaviour is ">=", and this also
makes more conceptual sense.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/omap_gpmc.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

Comments

andrzej zaborowski Sept. 17, 2011, 1:22 a.m. UTC | #1
On 28 August 2011 18:56, Peter Maydell <peter.maydell@linaro.org> wrote:
> The OMAP3 TRM is inconsistent about whether the GPMC FIFOTHRESHOLDSTATUS
> bit should be set when FIFOPOINTER > FIFOTHRESHOLD or when it is >=
> FIFOTHRESHOLD. Apparently the underlying functional spec from which
> the TRM was created states that the behaviour is ">=", and this also
> makes more conceptual sense.

It would be good to have a comment about this in the code.

Cheers
diff mbox

Patch

diff --git a/hw/omap_gpmc.c b/hw/omap_gpmc.c
index b728397..9da8491 100644
--- a/hw/omap_gpmc.c
+++ b/hw/omap_gpmc.c
@@ -222,7 +222,7 @@  static uint64_t omap_gpmc_read(void *opaque, target_phys_addr_t addr,
         return s->prefcontrol;
     case 0x1f0:	/* GPMC_PREFETCH_STATUS */
         return (s->preffifo << 24) |
-                ((s->preffifo >
+                ((s->preffifo >=
                   ((s->prefconfig[0] >> 8) & 0x7f) ? 1 : 0) << 16) |
                 s->prefcount;