diff mbox series

[v4,03/17] target/ppc: Properly sync cpu state with new msr in cpu_load_old

Message ID 20210315184615.1985590-4-richard.henderson@linaro.org
State Superseded
Headers show
Series target/ppc: Fix truncation of env->hflags | expand

Commit Message

Richard Henderson March 15, 2021, 6:46 p.m. UTC
Match cpu_post_load in using ppc_store_msr to set all of
the cpu state implied by the value of msr.  Do not restore
hflags or hflags_nmsr, as we recompute them in ppc_store_msr.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/ppc/machine.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

-- 
2.25.1

Comments

Cédric Le Goater March 16, 2021, 8:15 a.m. UTC | #1
On 3/15/21 7:46 PM, Richard Henderson wrote:
> Match cpu_post_load in using ppc_store_msr to set all of

> the cpu state implied by the value of msr.  Do not restore

> hflags or hflags_nmsr, as we recompute them in ppc_store_msr.

> 

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Could we add a common routine used by cpu_post_load() and cpu_load_old() ?


Reviewed-by: Cédric Le Goater <clg@kaod.org>


Thanks,

C.

> ---

>  target/ppc/machine.c | 13 +++++++++++--

>  1 file changed, 11 insertions(+), 2 deletions(-)

> 

> diff --git a/target/ppc/machine.c b/target/ppc/machine.c

> index 283db1d28a..87d7bffb86 100644

> --- a/target/ppc/machine.c

> +++ b/target/ppc/machine.c

> @@ -21,6 +21,7 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)

>      int32_t slb_nr;

>  #endif

>      target_ulong xer;

> +    target_ulong msr;

>  

>      for (i = 0; i < 32; i++) {

>          qemu_get_betls(f, &env->gpr[i]);

> @@ -111,11 +112,19 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)

>      qemu_get_betls(f, &env->ivpr_mask);

>      qemu_get_betls(f, &env->hreset_vector);

>      qemu_get_betls(f, &env->nip);

> -    qemu_get_betls(f, &env->hflags);

> -    qemu_get_betls(f, &env->hflags_nmsr);

> +    qemu_get_sbetl(f); /* Discard unused hflags */

> +    qemu_get_sbetl(f); /* Discard unused hflags_nmsr */

>      qemu_get_sbe32(f); /* Discard unused mmu_idx */

>      qemu_get_sbe32(f); /* Discard unused power_mode */

>  

> +    /*

> +     * Invalidate all supported msr bits except MSR_TGPR/MSR_HVB

> +     * before restoring.  Note that this recomputes hflags and mem_idx.

> +     */

> +    msr = env->msr;

> +    env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB);

> +    ppc_store_msr(env, msr);

> +

>      /* Recompute mmu indices */

>      hreg_compute_mem_idx(env);

>  

>
David Gibson March 22, 2021, 3:38 a.m. UTC | #2
On Mon, Mar 15, 2021 at 12:46:01PM -0600, Richard Henderson wrote:
> Match cpu_post_load in using ppc_store_msr to set all of

> the cpu state implied by the value of msr.  Do not restore

> hflags or hflags_nmsr, as we recompute them in ppc_store_msr.

> 

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Applied to ppc-for-6.0, thanks.

> ---

>  target/ppc/machine.c | 13 +++++++++++--

>  1 file changed, 11 insertions(+), 2 deletions(-)

> 

> diff --git a/target/ppc/machine.c b/target/ppc/machine.c

> index 283db1d28a..87d7bffb86 100644

> --- a/target/ppc/machine.c

> +++ b/target/ppc/machine.c

> @@ -21,6 +21,7 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)

>      int32_t slb_nr;

>  #endif

>      target_ulong xer;

> +    target_ulong msr;

>  

>      for (i = 0; i < 32; i++) {

>          qemu_get_betls(f, &env->gpr[i]);

> @@ -111,11 +112,19 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)

>      qemu_get_betls(f, &env->ivpr_mask);

>      qemu_get_betls(f, &env->hreset_vector);

>      qemu_get_betls(f, &env->nip);

> -    qemu_get_betls(f, &env->hflags);

> -    qemu_get_betls(f, &env->hflags_nmsr);

> +    qemu_get_sbetl(f); /* Discard unused hflags */

> +    qemu_get_sbetl(f); /* Discard unused hflags_nmsr */

>      qemu_get_sbe32(f); /* Discard unused mmu_idx */

>      qemu_get_sbe32(f); /* Discard unused power_mode */

>  

> +    /*

> +     * Invalidate all supported msr bits except MSR_TGPR/MSR_HVB

> +     * before restoring.  Note that this recomputes hflags and mem_idx.

> +     */

> +    msr = env->msr;

> +    env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB);

> +    ppc_store_msr(env, msr);

> +

>      /* Recompute mmu indices */

>      hreg_compute_mem_idx(env);

>  


-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson
Richard Henderson March 22, 2021, 4:53 p.m. UTC | #3
On 3/16/21 2:15 AM, Cédric Le Goater wrote:
> On 3/15/21 7:46 PM, Richard Henderson wrote:

>> Match cpu_post_load in using ppc_store_msr to set all of

>> the cpu state implied by the value of msr.  Do not restore

>> hflags or hflags_nmsr, as we recompute them in ppc_store_msr.

>>

>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> 

> Could we add a common routine used by cpu_post_load() and cpu_load_old() ?


Will do.  David, would you like to unqueue this one, or shall I send another 
patch on top?


r~
David Gibson March 22, 2021, 11:19 p.m. UTC | #4
On Mon, Mar 22, 2021 at 10:53:01AM -0600, Richard Henderson wrote:
> On 3/16/21 2:15 AM, Cédric Le Goater wrote:

> > On 3/15/21 7:46 PM, Richard Henderson wrote:

> > > Match cpu_post_load in using ppc_store_msr to set all of

> > > the cpu state implied by the value of msr.  Do not restore

> > > hflags or hflags_nmsr, as we recompute them in ppc_store_msr.

> > > 

> > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> > 

> > Could we add a common routine used by cpu_post_load() and cpu_load_old() ?

> 

> Will do.  David, would you like to unqueue this one, or shall I send another

> patch on top?


Pulling that one out causes conflicts with later patches, so another
one on top, please.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson
diff mbox series

Patch

diff --git a/target/ppc/machine.c b/target/ppc/machine.c
index 283db1d28a..87d7bffb86 100644
--- a/target/ppc/machine.c
+++ b/target/ppc/machine.c
@@ -21,6 +21,7 @@  static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
     int32_t slb_nr;
 #endif
     target_ulong xer;
+    target_ulong msr;
 
     for (i = 0; i < 32; i++) {
         qemu_get_betls(f, &env->gpr[i]);
@@ -111,11 +112,19 @@  static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
     qemu_get_betls(f, &env->ivpr_mask);
     qemu_get_betls(f, &env->hreset_vector);
     qemu_get_betls(f, &env->nip);
-    qemu_get_betls(f, &env->hflags);
-    qemu_get_betls(f, &env->hflags_nmsr);
+    qemu_get_sbetl(f); /* Discard unused hflags */
+    qemu_get_sbetl(f); /* Discard unused hflags_nmsr */
     qemu_get_sbe32(f); /* Discard unused mmu_idx */
     qemu_get_sbe32(f); /* Discard unused power_mode */
 
+    /*
+     * Invalidate all supported msr bits except MSR_TGPR/MSR_HVB
+     * before restoring.  Note that this recomputes hflags and mem_idx.
+     */
+    msr = env->msr;
+    env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB);
+    ppc_store_msr(env, msr);
+
     /* Recompute mmu indices */
     hreg_compute_mem_idx(env);