| Message ID | cover.1614244789.git.saiprakash.ranjan@codeaurora.org |
|---|---|
| Headers | show |
| Series | qcom/sc7280: Enable various hardware blocks on SC7280 SoC | expand |
Quoting Sai Prakash Ranjan (2021-02-25 01:30:23) > Add AOSS QMP support for SC7280 SoC. > > Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org>
On 2021-02-26 01:11, Stephen Boyd wrote: > Quoting Sai Prakash Ranjan (2021-02-25 01:30:24) >> Add a DT node for the AOSS QMP on SC7280 SoC. >> >> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> >> --- >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++++++++++++++ >> 1 file changed, 14 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index 65c1e0f2fb56..cbd567ccc04e 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -9,6 +9,7 @@ >> #include <dt-bindings/clock/qcom,rpmh.h> >> #include <dt-bindings/interrupt-controller/arm-gic.h> >> #include <dt-bindings/mailbox/qcom-ipcc.h> >> +#include <dt-bindings/power/qcom-aoss-qmp.h> >> #include <dt-bindings/soc/qcom,rpmh-rsc.h> >> >> / { >> @@ -368,6 +369,19 @@ pdc: interrupt-controller@b220000 { >> interrupt-controller; >> }; >> >> + aoss_qmp: qmp@c300000 { > > power-domain-controller@c300000? power-controller@c300000? > Its an AOSS message RAM and all other SM* SoCs have as qmp@ and the dt binding as well, I see only SM8150 with power-controller, that should probably be fixed? >> + compatible = "qcom,sc7280-aoss-qmp"; >> + reg = <0 0x0c300000 0 0x100000>; >> + interrupts-extended = <&ipcc IPCC_CLIENT_AOP >> + >> IPCC_MPROC_SIGNAL_GLINK_QMP >> + >> IRQ_TYPE_EDGE_RISING>; >> + mboxes = <&ipcc IPCC_CLIENT_AOP >> + IPCC_MPROC_SIGNAL_GLINK_QMP>; >> + >> + #clock-cells = <0>; >> + #power-domain-cells = <1>; >> + }; >> + >> spmi_bus: qcom,spmi@c440000 { > > Ick, should be spmi@ > Not introduced by this patch but I'll pass on the comment. >> compatible = "qcom,spmi-pmic-arb"; >> reg = <0 0x0c440000 0 0x1100>, Thanks, Sai
Quoting Sai Prakash Ranjan (2021-02-25 23:51:00) > On 2021-02-26 01:11, Stephen Boyd wrote: > > Quoting Sai Prakash Ranjan (2021-02-25 01:30:24) > >> Add a DT node for the AOSS QMP on SC7280 SoC. > >> > >> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> > >> --- > >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++++++++++++++ > >> 1 file changed, 14 insertions(+) > >> > >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi > >> b/arch/arm64/boot/dts/qcom/sc7280.dtsi > >> index 65c1e0f2fb56..cbd567ccc04e 100644 > >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > >> @@ -9,6 +9,7 @@ > >> #include <dt-bindings/clock/qcom,rpmh.h> > >> #include <dt-bindings/interrupt-controller/arm-gic.h> > >> #include <dt-bindings/mailbox/qcom-ipcc.h> > >> +#include <dt-bindings/power/qcom-aoss-qmp.h> > >> #include <dt-bindings/soc/qcom,rpmh-rsc.h> > >> > >> / { > >> @@ -368,6 +369,19 @@ pdc: interrupt-controller@b220000 { > >> interrupt-controller; > >> }; > >> > >> + aoss_qmp: qmp@c300000 { > > > > power-domain-controller@c300000? power-controller@c300000? > > > > Its an AOSS message RAM and all other SM* SoCs have as qmp@ > and the dt binding as well, I see only SM8150 with power-controller, > that should probably be fixed? Node name should be generic while still being meaningful. Nobody knows what qmp is, but power-controller makes sense. Can you fix this and the others to be power-controller?
On 2021-02-27 00:16, Stephen Boyd wrote: > Quoting Sai Prakash Ranjan (2021-02-25 23:51:00) >> On 2021-02-26 01:11, Stephen Boyd wrote: >> > Quoting Sai Prakash Ranjan (2021-02-25 01:30:24) >> >> Add a DT node for the AOSS QMP on SC7280 SoC. >> >> >> >> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> >> >> --- >> >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++++++++++++++ >> >> 1 file changed, 14 insertions(+) >> >> >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> >> b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> >> index 65c1e0f2fb56..cbd567ccc04e 100644 >> >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> >> @@ -9,6 +9,7 @@ >> >> #include <dt-bindings/clock/qcom,rpmh.h> >> >> #include <dt-bindings/interrupt-controller/arm-gic.h> >> >> #include <dt-bindings/mailbox/qcom-ipcc.h> >> >> +#include <dt-bindings/power/qcom-aoss-qmp.h> >> >> #include <dt-bindings/soc/qcom,rpmh-rsc.h> >> >> >> >> / { >> >> @@ -368,6 +369,19 @@ pdc: interrupt-controller@b220000 { >> >> interrupt-controller; >> >> }; >> >> >> >> + aoss_qmp: qmp@c300000 { >> > >> > power-domain-controller@c300000? power-controller@c300000? >> > >> >> Its an AOSS message RAM and all other SM* SoCs have as qmp@ >> and the dt binding as well, I see only SM8150 with power-controller, >> that should probably be fixed? > > Node name should be generic while still being meaningful. Nobody knows > what qmp is, but power-controller makes sense. Can you fix this and the > others to be power-controller? > Ok makes sense, I will post changing others as well and see if we get any comments there. Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
On Thu, 25 Feb 2021 15:00:17 +0530, Sai Prakash Ranjan wrote: > Add LLCC compatible for SC7280 SoC. > > Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> > --- > Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 1 + > 1 file changed, 1 insertion(+) > Acked-by: Rob Herring <robh@kernel.org>
On Thu, 25 Feb 2021 15:00:22 +0530, Sai Prakash Ranjan wrote: > Add SC7280 AOSS QMP compatible to the list of possible bindings. > > Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> > --- > Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt | 1 + > 1 file changed, 1 insertion(+) > Acked-by: Rob Herring <robh@kernel.org>
On 2021-02-27 19:26, Sai Prakash Ranjan wrote: > On 2021-02-27 00:16, Stephen Boyd wrote: >> Quoting Sai Prakash Ranjan (2021-02-25 23:51:00) >>> On 2021-02-26 01:11, Stephen Boyd wrote: >>> > Quoting Sai Prakash Ranjan (2021-02-25 01:30:24) >>> >> Add a DT node for the AOSS QMP on SC7280 SoC. >>> >> >>> >> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> >>> >> --- >>> >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++++++++++++++ >>> >> 1 file changed, 14 insertions(+) >>> >> >>> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi >>> >> b/arch/arm64/boot/dts/qcom/sc7280.dtsi >>> >> index 65c1e0f2fb56..cbd567ccc04e 100644 >>> >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >>> >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >>> >> @@ -9,6 +9,7 @@ >>> >> #include <dt-bindings/clock/qcom,rpmh.h> >>> >> #include <dt-bindings/interrupt-controller/arm-gic.h> >>> >> #include <dt-bindings/mailbox/qcom-ipcc.h> >>> >> +#include <dt-bindings/power/qcom-aoss-qmp.h> >>> >> #include <dt-bindings/soc/qcom,rpmh-rsc.h> >>> >> >>> >> / { >>> >> @@ -368,6 +369,19 @@ pdc: interrupt-controller@b220000 { >>> >> interrupt-controller; >>> >> }; >>> >> >>> >> + aoss_qmp: qmp@c300000 { >>> > >>> > power-domain-controller@c300000? power-controller@c300000? >>> > >>> >>> Its an AOSS message RAM and all other SM* SoCs have as qmp@ >>> and the dt binding as well, I see only SM8150 with power-controller, >>> that should probably be fixed? >> >> Node name should be generic while still being meaningful. Nobody knows >> what qmp is, but power-controller makes sense. Can you fix this and >> the >> others to be power-controller? >> we probably would be changing them back to qmp or something more generic soon since the consensus was qmp wasn't a power-controller. So not sure if its worth the effort here. > > Ok makes sense, I will post changing others as well and see if we get > any comments there. > > Thanks, > Sai
On Thu 25 Feb 03:30 CST 2021, Sai Prakash Ranjan wrote: > This series enables various hardware blocks such as LLCC, IPCC, AOSS QMP > and Coresight on SC7280 SoC. > > This series is dependent on the base support added for SC7280 in [1]. > I've picked some of these patches... It would be helpful if you split series like this based on how they will be picked up my various maintainers. E.g. I think it's quite likely Jassi won't find and pick up the mailbox binding patch. PS. I sent a patch to Jassi adding the mailbox binding directory to MAINTAINERS. Regards, Bjorn > [1] https://lore.kernel.org/patchwork/cover/1379842/ > > Sai Prakash Ranjan (9): > dt-bindings: arm: msm: Add LLCC for SC7280 > soc: qcom: llcc: Add configuration data for SC7280 > arm64: dts: qcom: sc7280: Add device tree node for LLCC > dt-bindings: mailbox: qcom-ipcc: Add compatible for SC7280 > arm64: dts: qcom: sc7280: Add IPCC for SC7280 SoC > dt-bindings: soc: qcom: aoss: Add SC7280 compatible > soc: qcom: aoss: Add AOSS QMP support for SC7280 > arm64: dts: qcom: sc7280: Add AOSS QMP node > arm64: dts: qcom: sc7280: Add Coresight support > > .../bindings/arm/msm/qcom,llcc.yaml | 1 + > .../bindings/mailbox/qcom-ipcc.yaml | 1 + > .../bindings/soc/qcom/qcom,aoss-qmp.txt | 1 + > arch/arm64/boot/dts/qcom/sc7280.dtsi | 520 ++++++++++++++++++ > drivers/soc/qcom/llcc-qcom.c | 19 + > drivers/soc/qcom/qcom_aoss.c | 1 + > 6 files changed, 543 insertions(+) > > > base-commit: d79b47c59576a51d8e288a6b98b75ccf4afb8acd > prerequisite-patch-id: d8babdd3c8a9923360af342f3d8d9876820272e5 > prerequisite-patch-id: 5757e07e4336d773d402769d09106924962ce31b > prerequisite-patch-id: 9b21eb51aa86619f5695a511c65c9236e3bc0f2b > prerequisite-patch-id: 2f834cc892f7f9109cbf32a87d504ba27b64a5df > prerequisite-patch-id: 14b1185357703d750c3411a16e97675489ca7dde > prerequisite-patch-id: 55c143f21b646c18da921a62bbd2801a5df38c8f > prerequisite-patch-id: 66f4c58aff2f1a7283b0103590ff82384907bae3 > prerequisite-patch-id: 75e73e6b13ab91ed5e3a96b59957aa5e867d65ea > prerequisite-patch-id: eb46845b4f9eb3706a26911042c2865a58577198 > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation >
On 2021-03-12 04:44, Bjorn Andersson wrote: > On Thu 25 Feb 03:30 CST 2021, Sai Prakash Ranjan wrote: > >> This series enables various hardware blocks such as LLCC, IPCC, AOSS >> QMP >> and Coresight on SC7280 SoC. >> >> This series is dependent on the base support added for SC7280 in [1]. >> > > I've picked some of these patches... > > > It would be helpful if you split series like this based on how they > will > be picked up my various maintainers. E.g. I think it's quite likely > Jassi won't find and pick up the mailbox binding patch. > > > PS. I sent a patch to Jassi adding the mailbox binding directory to > MAINTAINERS. > Sure I will group patches(mainly dt-bindings for other subsystems) accordingly. Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Quoting Sibi Sankar (2021-03-08 21:58:21) > On 2021-02-27 19:26, Sai Prakash Ranjan wrote: > > On 2021-02-27 00:16, Stephen Boyd wrote: > >> Quoting Sai Prakash Ranjan (2021-02-25 23:51:00) > >>> On 2021-02-26 01:11, Stephen Boyd wrote: > >>> > Quoting Sai Prakash Ranjan (2021-02-25 01:30:24) > >>> >> Add a DT node for the AOSS QMP on SC7280 SoC. > >>> >> > >>> >> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> > >>> >> --- > >>> >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++++++++++++++ > >>> >> 1 file changed, 14 insertions(+) > >>> >> > >>> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi > >>> >> b/arch/arm64/boot/dts/qcom/sc7280.dtsi > >>> >> index 65c1e0f2fb56..cbd567ccc04e 100644 > >>> >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > >>> >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > >>> >> @@ -9,6 +9,7 @@ > >>> >> #include <dt-bindings/clock/qcom,rpmh.h> > >>> >> #include <dt-bindings/interrupt-controller/arm-gic.h> > >>> >> #include <dt-bindings/mailbox/qcom-ipcc.h> > >>> >> +#include <dt-bindings/power/qcom-aoss-qmp.h> > >>> >> #include <dt-bindings/soc/qcom,rpmh-rsc.h> > >>> >> > >>> >> / { > >>> >> @@ -368,6 +369,19 @@ pdc: interrupt-controller@b220000 { > >>> >> interrupt-controller; > >>> >> }; > >>> >> > >>> >> + aoss_qmp: qmp@c300000 { > >>> > > >>> > power-domain-controller@c300000? power-controller@c300000? > >>> > > >>> > >>> Its an AOSS message RAM and all other SM* SoCs have as qmp@ > >>> and the dt binding as well, I see only SM8150 with power-controller, > >>> that should probably be fixed? > >> > >> Node name should be generic while still being meaningful. Nobody knows > >> what qmp is, but power-controller makes sense. Can you fix this and > >> the > >> others to be power-controller? > >> > > we probably would be changing them back > to qmp or something more generic soon > since the consensus was qmp wasn't a > power-controller. So not sure if its > worth the effort here. > Hmm alright. Maybe mailbox? qmp is not generic. What does it stand for? qualcomm messaging protocol?
On 2021-03-23 09:08, Stephen Boyd wrote: > Quoting Sibi Sankar (2021-03-08 21:58:21) >> On 2021-02-27 19:26, Sai Prakash Ranjan wrote: >> > On 2021-02-27 00:16, Stephen Boyd wrote: >> >> Quoting Sai Prakash Ranjan (2021-02-25 23:51:00) >> >>> On 2021-02-26 01:11, Stephen Boyd wrote: >> >>> > Quoting Sai Prakash Ranjan (2021-02-25 01:30:24) >> >>> >> Add a DT node for the AOSS QMP on SC7280 SoC. >> >>> >> >> >>> >> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> >> >>> >> --- >> >>> >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++++++++++++++ >> >>> >> 1 file changed, 14 insertions(+) >> >>> >> >> >>> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> >>> >> b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> >>> >> index 65c1e0f2fb56..cbd567ccc04e 100644 >> >>> >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> >>> >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> >>> >> @@ -9,6 +9,7 @@ >> >>> >> #include <dt-bindings/clock/qcom,rpmh.h> >> >>> >> #include <dt-bindings/interrupt-controller/arm-gic.h> >> >>> >> #include <dt-bindings/mailbox/qcom-ipcc.h> >> >>> >> +#include <dt-bindings/power/qcom-aoss-qmp.h> >> >>> >> #include <dt-bindings/soc/qcom,rpmh-rsc.h> >> >>> >> >> >>> >> / { >> >>> >> @@ -368,6 +369,19 @@ pdc: interrupt-controller@b220000 { >> >>> >> interrupt-controller; >> >>> >> }; >> >>> >> >> >>> >> + aoss_qmp: qmp@c300000 { >> >>> > >> >>> > power-domain-controller@c300000? power-controller@c300000? >> >>> > >> >>> >> >>> Its an AOSS message RAM and all other SM* SoCs have as qmp@ >> >>> and the dt binding as well, I see only SM8150 with power-controller, >> >>> that should probably be fixed? >> >> >> >> Node name should be generic while still being meaningful. Nobody knows >> >> what qmp is, but power-controller makes sense. Can you fix this and >> >> the >> >> others to be power-controller? >> >> >> >> we probably would be changing them back >> to qmp or something more generic soon >> since the consensus was qmp wasn't a >> power-controller. So not sure if its >> worth the effort here. >> > > Hmm alright. Maybe mailbox? qmp is not generic. What does it stand for? > qualcomm messaging protocol? It's documented as ^^ in the git log but I guess it should be called qualcomm mailbox protocol instead. I don't think it can be called mailbox since it doesn't have mbox cells in its bindings.