mbox series

[v4,00/78] target/arm: Implement SVE2

Message ID 20210309162041.23124-1-richard.henderson@linaro.org
Headers show
Series target/arm: Implement SVE2 | expand

Message

Richard Henderson March 9, 2021, 4:19 p.m. UTC 
After a 6-month hiatus, sve2 is back.  This time, with RISU
testing vs FVP 11.13.36.

Based-on: 20210309155305.11301-1-richard.henderson@linaro.org
("target/arm: sve1 fixes")


r~


Richard Henderson (60):
  target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2
  target/arm: Implement SVE2 Integer Multiply - Unpredicated
  target/arm: Implement SVE2 integer pairwise add and accumulate long
  target/arm: Implement SVE2 integer unary operations (predicated)
  target/arm: Split out saturating/rounding shifts from neon
  target/arm: Implement SVE2 saturating/rounding bitwise shift left
    (predicated)
  target/arm: Implement SVE2 integer halving add/subtract (predicated)
  target/arm: Implement SVE2 integer pairwise arithmetic
  target/arm: Implement SVE2 saturating add/subtract (predicated)
  target/arm: Implement SVE2 integer add/subtract long
  target/arm: Implement SVE2 integer add/subtract interleaved long
  target/arm: Implement SVE2 integer add/subtract wide
  target/arm: Implement SVE2 integer multiply long
  target/arm: Implement PMULLB and PMULLT
  target/arm: Implement SVE2 bitwise shift left long
  target/arm: Implement SVE2 bitwise exclusive-or interleaved
  target/arm: Implement SVE2 bitwise permute
  target/arm: Implement SVE2 complex integer add
  target/arm: Implement SVE2 integer absolute difference and accumulate
    long
  target/arm: Implement SVE2 integer add/subtract long with carry
  target/arm: Implement SVE2 bitwise shift right and accumulate
  target/arm: Implement SVE2 bitwise shift and insert
  target/arm: Implement SVE2 integer absolute difference and accumulate
  target/arm: Implement SVE2 saturating extract narrow
  target/arm: Implement SVE2 SHRN, RSHRN
  target/arm: Implement SVE2 SQSHRUN, SQRSHRUN
  target/arm: Implement SVE2 UQSHRN, UQRSHRN
  target/arm: Implement SVE2 SQSHRN, SQRSHRN
  target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS
  target/arm: Implement SVE2 WHILERW, WHILEWR
  target/arm: Implement SVE2 bitwise ternary operations
  target/arm: Implement SVE2 saturating multiply-add long
  target/arm: Implement SVE2 saturating multiply-add high
  target/arm: Implement SVE2 integer multiply-add long
  target/arm: Implement SVE2 complex integer multiply-add
  target/arm: Implement SVE2 XAR
  target/arm: Pass separate addend to {U,S}DOT helpers
  target/arm: Pass separate addend to FCMLA helpers
  target/arm: Split out formats for 2 vectors + 1 index
  target/arm: Split out formats for 3 vectors + 1 index
  target/arm: Implement SVE2 integer multiply (indexed)
  target/arm: Implement SVE2 integer multiply-add (indexed)
  target/arm: Implement SVE2 saturating multiply-add high (indexed)
  target/arm: Implement SVE2 saturating multiply-add (indexed)
  target/arm: Implement SVE2 integer multiply long (indexed)
  target/arm: Implement SVE2 saturating multiply (indexed)
  target/arm: Implement SVE2 signed saturating doubling multiply high
  target/arm: Implement SVE2 saturating multiply high (indexed)
  target/arm: Implement SVE2 multiply-add long (indexed)
  target/arm: Implement SVE2 complex integer multiply-add (indexed)
  target/arm: Implement SVE mixed sign dot product (indexed)
  target/arm: Implement SVE mixed sign dot product
  target/arm: Implement SVE2 crypto unary operations
  target/arm: Implement SVE2 crypto destructive binary operations
  target/arm: Implement SVE2 crypto constructive binary operations
  target/arm: Share table of sve load functions
  target/arm: Implement SVE2 LD1RO
  target/arm: Implement 128-bit ZIP, UZP, TRN
  target/arm: Implement SVE2 complex integer dot product
  target/arm: Enable SVE2 and some extensions

Stephen Long (18):
  target/arm: Implement SVE2 floating-point pairwise
  target/arm: Implement SVE2 MATCH, NMATCH
  target/arm: Implement SVE2 ADDHNB, ADDHNT
  target/arm: Implement SVE2 RADDHNB, RADDHNT
  target/arm: Implement SVE2 SUBHNB, SUBHNT
  target/arm: Implement SVE2 RSUBHNB, RSUBHNT
  target/arm: Implement SVE2 HISTCNT, HISTSEG
  target/arm: Implement SVE2 scatter store insns
  target/arm: Implement SVE2 gather load insns
  target/arm: Implement SVE2 FMMLA
  target/arm: Implement SVE2 SPLICE, EXT
  target/arm: Implement SVE2 TBL, TBX
  target/arm: Implement SVE2 FCVTNT
  target/arm: Implement SVE2 FCVTLT
  target/arm: Implement SVE2 FCVTXNT, FCVTX
  target/arm: Implement SVE2 FLOGB
  target/arm: Implement SVE2 bitwise shift immediate
  target/arm: Implement SVE2 fp multiply-add long

 target/arm/cpu.h                |   56 +
 target/arm/helper-sve.h         |  722 ++++++-
 target/arm/helper.h             |  104 +-
 target/arm/translate-a64.h      |    3 +
 target/arm/vec_internal.h       |  143 ++
 target/arm/sve.decode           |  568 +++++-
 target/arm/cpu64.c              |   11 +
 target/arm/helper.c             |    3 +-
 target/arm/kvm64.c              |   11 +
 target/arm/neon_helper.c        |  507 +----
 target/arm/sve_helper.c         | 2123 ++++++++++++++++++++-
 target/arm/translate-a64.c      |   68 +-
 target/arm/translate-sve.c      | 3157 +++++++++++++++++++++++++++++--
 target/arm/vec_helper.c         |  777 +++++++-
 target/arm/translate-neon.c.inc |   20 +-
 15 files changed, 7425 insertions(+), 848 deletions(-)

-- 
2.25.1

Comments

no-reply@patchew.org March 9, 2021, 7:28 p.m. UTC | #1 
Patchew URL: https://patchew.org/QEMU/20210309162041.23124-1-richard.henderson@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20210309162041.23124-1-richard.henderson@linaro.org
Subject: [PATCH v4 00/78] target/arm: Implement SVE2

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]      patchew/20210309102742.30442-1-eric.auger@redhat.com -> patchew/20210309102742.30442-1-eric.auger@redhat.com
 - [tag update]      patchew/20210309141727.12522-1-alex.bennee@linaro.org -> patchew/20210309141727.12522-1-alex.bennee@linaro.org
 * [new tag]         patchew/20210309162041.23124-1-richard.henderson@linaro.org -> patchew/20210309162041.23124-1-richard.henderson@linaro.org
 * [new tag]         patchew/20210309190802.830969-1-f4bug@amsat.org -> patchew/20210309190802.830969-1-f4bug@amsat.org
Switched to a new branch 'test'
1eff40a target/arm: Enable SVE2 and some extensions
e42cf3b target/arm: Implement SVE2 complex integer dot product
938e262 target/arm: Implement SVE2 fp multiply-add long
a2f28a7 target/arm: Implement SVE2 bitwise shift immediate
b3dd26a target/arm: Implement 128-bit ZIP, UZP, TRN
84a6955 target/arm: Implement SVE2 LD1RO
edfcd8d target/arm: Share table of sve load functions
9481bd3 target/arm: Implement SVE2 FLOGB
72a40a6 target/arm: Implement SVE2 FCVTXNT, FCVTX
45cea39 target/arm: Implement SVE2 FCVTLT
b7eedd5 target/arm: Implement SVE2 FCVTNT
6db1320 target/arm: Implement SVE2 TBL, TBX
323aa98 target/arm: Implement SVE2 crypto constructive binary operations
714a0d8 target/arm: Implement SVE2 crypto destructive binary operations
fe72343 target/arm: Implement SVE2 crypto unary operations
b99fde4 target/arm: Implement SVE mixed sign dot product
4b2ca84 target/arm: Implement SVE mixed sign dot product (indexed)
ec4f871 target/arm: Implement SVE2 complex integer multiply-add (indexed)
3caa3ca target/arm: Implement SVE2 multiply-add long (indexed)
4dd2716 target/arm: Implement SVE2 saturating multiply high (indexed)
7c69dd0 target/arm: Implement SVE2 signed saturating doubling multiply high
bb2242c target/arm: Implement SVE2 saturating multiply (indexed)
bfc85c0 target/arm: Implement SVE2 integer multiply long (indexed)
673d83b target/arm: Implement SVE2 saturating multiply-add (indexed)
0d57bd6 target/arm: Implement SVE2 saturating multiply-add high (indexed)
9a5714c target/arm: Implement SVE2 integer multiply-add (indexed)
6ba9389 target/arm: Implement SVE2 integer multiply (indexed)
7c6425c target/arm: Split out formats for 3 vectors + 1 index
a321b4b target/arm: Split out formats for 2 vectors + 1 index
9ce3aa9 target/arm: Pass separate addend to FCMLA helpers
f6c2b98 target/arm: Pass separate addend to {U, S}DOT helpers
9d0dff3 target/arm: Implement SVE2 SPLICE, EXT
e8decc7 target/arm: Implement SVE2 FMMLA
44a25a1 target/arm: Implement SVE2 gather load insns
400234f target/arm: Implement SVE2 scatter store insns
43ca8a3 target/arm: Implement SVE2 XAR
c35ea38 target/arm: Implement SVE2 HISTCNT, HISTSEG
25e8326 target/arm: Implement SVE2 RSUBHNB, RSUBHNT
85f7579 target/arm: Implement SVE2 SUBHNB, SUBHNT
9b00ef7 target/arm: Implement SVE2 RADDHNB, RADDHNT
58cf01b target/arm: Implement SVE2 ADDHNB, ADDHNT
db2f497 target/arm: Implement SVE2 complex integer multiply-add
a93815e target/arm: Implement SVE2 integer multiply-add long
bc25759 target/arm: Implement SVE2 saturating multiply-add high
15bb3c9 target/arm: Implement SVE2 saturating multiply-add long
ec41ea4 target/arm: Implement SVE2 MATCH, NMATCH
12fe76b target/arm: Implement SVE2 bitwise ternary operations
e9ea9bc target/arm: Implement SVE2 WHILERW, WHILEWR
a841987 target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS
15c530b target/arm: Implement SVE2 SQSHRN, SQRSHRN
39fa39b target/arm: Implement SVE2 UQSHRN, UQRSHRN
280c16b target/arm: Implement SVE2 SQSHRUN, SQRSHRUN
74f89c6 target/arm: Implement SVE2 SHRN, RSHRN
3324808 target/arm: Implement SVE2 floating-point pairwise
8326d0a target/arm: Implement SVE2 saturating extract narrow
ed1a862 target/arm: Implement SVE2 integer absolute difference and accumulate
5c475ed target/arm: Implement SVE2 bitwise shift and insert
233f461 target/arm: Implement SVE2 bitwise shift right and accumulate
3ea64a3 target/arm: Implement SVE2 integer add/subtract long with carry
86f0b5c target/arm: Implement SVE2 integer absolute difference and accumulate long
3f2da1f target/arm: Implement SVE2 complex integer add
2112ab8 target/arm: Implement SVE2 bitwise permute
330009e target/arm: Implement SVE2 bitwise exclusive-or interleaved
3f81380 target/arm: Implement SVE2 bitwise shift left long
a294e74 target/arm: Implement PMULLB and PMULLT
7d6b2c5 target/arm: Implement SVE2 integer multiply long
4492c09 target/arm: Implement SVE2 integer add/subtract wide
3f47ba5 target/arm: Implement SVE2 integer add/subtract interleaved long
40fae12 target/arm: Implement SVE2 integer add/subtract long
1414c2c target/arm: Implement SVE2 saturating add/subtract (predicated)
0687701 target/arm: Implement SVE2 integer pairwise arithmetic
069d84a target/arm: Implement SVE2 integer halving add/subtract (predicated)
ce18e2e target/arm: Implement SVE2 saturating/rounding bitwise shift left (predicated)
df48ac7 target/arm: Split out saturating/rounding shifts from neon
779bab7 target/arm: Implement SVE2 integer unary operations (predicated)
03739b4 target/arm: Implement SVE2 integer pairwise add and accumulate long
bf02cd4 target/arm: Implement SVE2 Integer Multiply - Unpredicated
5c56841 target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2

=== OUTPUT BEGIN ===
1/78 Checking commit 5c56841dc33e (target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2)
2/78 Checking commit bf02cd48f16d (target/arm: Implement SVE2 Integer Multiply - Unpredicated)
3/78 Checking commit 03739b4fc44b (target/arm: Implement SVE2 integer pairwise add and accumulate long)
4/78 Checking commit 779bab716e59 (target/arm: Implement SVE2 integer unary operations (predicated))
5/78 Checking commit df48ac740676 (target/arm: Split out saturating/rounding shifts from neon)
6/78 Checking commit ce18e2e0b6bb (target/arm: Implement SVE2 saturating/rounding bitwise shift left (predicated))
7/78 Checking commit 069d84a3345c (target/arm: Implement SVE2 integer halving add/subtract (predicated))
8/78 Checking commit 06877012c982 (target/arm: Implement SVE2 integer pairwise arithmetic)
9/78 Checking commit 1414c2c2407e (target/arm: Implement SVE2 saturating add/subtract (predicated))
10/78 Checking commit 40fae122fc78 (target/arm: Implement SVE2 integer add/subtract long)
11/78 Checking commit 3f47ba5084f3 (target/arm: Implement SVE2 integer add/subtract interleaved long)
12/78 Checking commit 4492c091ea6b (target/arm: Implement SVE2 integer add/subtract wide)
13/78 Checking commit 7d6b2c5ef5e1 (target/arm: Implement SVE2 integer multiply long)
14/78 Checking commit a294e743adf4 (target/arm: Implement PMULLB and PMULLT)
15/78 Checking commit 3f813800cc56 (target/arm: Implement SVE2 bitwise shift left long)
16/78 Checking commit 330009ea9638 (target/arm: Implement SVE2 bitwise exclusive-or interleaved)
17/78 Checking commit 2112ab872834 (target/arm: Implement SVE2 bitwise permute)
18/78 Checking commit 3f2da1fa3e1e (target/arm: Implement SVE2 complex integer add)
19/78 Checking commit 86f0b5ccb93d (target/arm: Implement SVE2 integer absolute difference and accumulate long)
20/78 Checking commit 3ea64a32570f (target/arm: Implement SVE2 integer add/subtract long with carry)
21/78 Checking commit 233f4614d4b7 (target/arm: Implement SVE2 bitwise shift right and accumulate)
22/78 Checking commit 5c475ed2f067 (target/arm: Implement SVE2 bitwise shift and insert)
23/78 Checking commit ed1a86235325 (target/arm: Implement SVE2 integer absolute difference and accumulate)
24/78 Checking commit 8326d0a7087c (target/arm: Implement SVE2 saturating extract narrow)
25/78 Checking commit 33248084756e (target/arm: Implement SVE2 floating-point pairwise)
26/78 Checking commit 74f89c60413f (target/arm: Implement SVE2 SHRN, RSHRN)
27/78 Checking commit 280c16b7b9e2 (target/arm: Implement SVE2 SQSHRUN, SQRSHRUN)
28/78 Checking commit 39fa39bf05fe (target/arm: Implement SVE2 UQSHRN, UQRSHRN)
29/78 Checking commit 15c530bd9c21 (target/arm: Implement SVE2 SQSHRN, SQRSHRN)
30/78 Checking commit a84198789915 (target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS)
31/78 Checking commit e9ea9bcadbc0 (target/arm: Implement SVE2 WHILERW, WHILEWR)
32/78 Checking commit 12fe76bf29f1 (target/arm: Implement SVE2 bitwise ternary operations)
33/78 Checking commit ec41ea404c1a (target/arm: Implement SVE2 MATCH, NMATCH)
34/78 Checking commit 15bb3c935985 (target/arm: Implement SVE2 saturating multiply-add long)
35/78 Checking commit bc25759ed1c9 (target/arm: Implement SVE2 saturating multiply-add high)
36/78 Checking commit a93815eb621d (target/arm: Implement SVE2 integer multiply-add long)
37/78 Checking commit db2f49736773 (target/arm: Implement SVE2 complex integer multiply-add)
38/78 Checking commit 58cf01b89367 (target/arm: Implement SVE2 ADDHNB, ADDHNT)
39/78 Checking commit 9b00ef73c734 (target/arm: Implement SVE2 RADDHNB, RADDHNT)
40/78 Checking commit 85f75792eb6c (target/arm: Implement SVE2 SUBHNB, SUBHNT)
41/78 Checking commit 25e83262d1b9 (target/arm: Implement SVE2 RSUBHNB, RSUBHNT)
42/78 Checking commit c35ea3834d08 (target/arm: Implement SVE2 HISTCNT, HISTSEG)
43/78 Checking commit 43ca8a382121 (target/arm: Implement SVE2 XAR)
44/78 Checking commit 400234f0d892 (target/arm: Implement SVE2 scatter store insns)
45/78 Checking commit 44a25a13cfd0 (target/arm: Implement SVE2 gather load insns)
46/78 Checking commit e8decc7769af (target/arm: Implement SVE2 FMMLA)
WARNING: line over 80 characters
#181: FILE: target/arm/translate-sve.c:7699:
+        TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);

total: 0 errors, 1 warnings, 149 lines checked

Patch 46/78 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
47/78 Checking commit 9d0dff35c633 (target/arm: Implement SVE2 SPLICE, EXT)
48/78 Checking commit f6c2b98484b5 (target/arm: Pass separate addend to {U, S}DOT helpers)
49/78 Checking commit 9ce3aa945543 (target/arm: Pass separate addend to FCMLA helpers)
50/78 Checking commit a321b4be8ca1 (target/arm: Split out formats for 2 vectors + 1 index)
51/78 Checking commit 7c6425ccf296 (target/arm: Split out formats for 3 vectors + 1 index)
52/78 Checking commit 6ba9389dd784 (target/arm: Implement SVE2 integer multiply (indexed))
53/78 Checking commit 9a5714c966c7 (target/arm: Implement SVE2 integer multiply-add (indexed))
54/78 Checking commit 0d57bd69a1d2 (target/arm: Implement SVE2 saturating multiply-add high (indexed))
55/78 Checking commit 673d83bd0d71 (target/arm: Implement SVE2 saturating multiply-add (indexed))
56/78 Checking commit bfc85c0636bf (target/arm: Implement SVE2 integer multiply long (indexed))
57/78 Checking commit bb2242c7aa26 (target/arm: Implement SVE2 saturating multiply (indexed))
58/78 Checking commit 7c69dd06dcb5 (target/arm: Implement SVE2 signed saturating doubling multiply high)
59/78 Checking commit 4dd271601f56 (target/arm: Implement SVE2 saturating multiply high (indexed))
60/78 Checking commit 3caa3ca51335 (target/arm: Implement SVE2 multiply-add long (indexed))
61/78 Checking commit ec4f871cd73e (target/arm: Implement SVE2 complex integer multiply-add (indexed))
ERROR: spaces required around that '*' (ctx:WxV)
#288: FILE: target/arm/translate-sve.c:3969:
+static bool trans_##NAME(DisasContext *s, arg_##NAME *a)       \
                                                      ^

total: 1 errors, 0 warnings, 265 lines checked

Patch 61/78 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

62/78 Checking commit 4b2ca84bd3b8 (target/arm: Implement SVE mixed sign dot product (indexed))
63/78 Checking commit b99fde4127d6 (target/arm: Implement SVE mixed sign dot product)
64/78 Checking commit fe723436ecc0 (target/arm: Implement SVE2 crypto unary operations)
65/78 Checking commit 714a0d81adda (target/arm: Implement SVE2 crypto destructive binary operations)
66/78 Checking commit 323aa986709f (target/arm: Implement SVE2 crypto constructive binary operations)
67/78 Checking commit 6db1320a1081 (target/arm: Implement SVE2 TBL, TBX)
ERROR: space prohibited before that close parenthesis ')'
#155: FILE: target/arm/sve_helper.c:3109:
+DO_TB(d, uint64_t,   )

total: 1 errors, 0 warnings, 165 lines checked

Patch 67/78 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

68/78 Checking commit b7eedd56bee8 (target/arm: Implement SVE2 FCVTNT)
69/78 Checking commit 45cea39080e4 (target/arm: Implement SVE2 FCVTLT)
70/78 Checking commit 72a40a65d8a6 (target/arm: Implement SVE2 FCVTXNT, FCVTX)
71/78 Checking commit 9481bd36c139 (target/arm: Implement SVE2 FLOGB)
72/78 Checking commit edfcd8daa095 (target/arm: Share table of sve load functions)
73/78 Checking commit 84a695576c17 (target/arm: Implement SVE2 LD1RO)
74/78 Checking commit b3dd26acf42d (target/arm: Implement 128-bit ZIP, UZP, TRN)
ERROR: space prohibited before that close parenthesis ')'
#77: FILE: target/arm/sve_helper.c:3470:
+DO_ZIP(sve2_zip_q, Int128, )

ERROR: space prohibited before that close parenthesis ')'
#114: FILE: target/arm/sve_helper.c:3499:
+DO_UZP(sve2_uzp_q, Int128, )

ERROR: space prohibited before that close parenthesis ')'
#131: FILE: target/arm/sve_helper.c:3522:
+DO_TRN(sve2_trn_q, Int128, )

total: 3 errors, 0 warnings, 178 lines checked

Patch 74/78 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

75/78 Checking commit a2f28a72d7e5 (target/arm: Implement SVE2 bitwise shift immediate)
76/78 Checking commit 938e2623645b (target/arm: Implement SVE2 fp multiply-add long)
77/78 Checking commit e42cf3bcaf9e (target/arm: Implement SVE2 complex integer dot product)
78/78 Checking commit 1eff40a70f11 (target/arm: Enable SVE2 and some extensions)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20210309162041.23124-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
Peter Maydell March 10, 2021, 8:17 p.m. UTC | #2 
On Tue, 9 Mar 2021 at 16:20, Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> After a 6-month hiatus, sve2 is back.  This time, with RISU

> testing vs FVP 11.13.36.

>

> Based-on: 20210309155305.11301-1-richard.henderson@linaro.org

> ("target/arm: sve1 fixes")


Are you hoping to squeeze this into 6.0, or can I delay
review of it in favour of for-6.0 stuff ?

thanks
-- PMM
Richard Henderson March 11, 2021, 2:33 a.m. UTC | #3 
On 3/10/21 2:17 PM, Peter Maydell wrote:
> On Tue, 9 Mar 2021 at 16:20, Richard Henderson

> <richard.henderson@linaro.org> wrote:

>>

>> After a 6-month hiatus, sve2 is back.  This time, with RISU

>> testing vs FVP 11.13.36.

>>

>> Based-on: 20210309155305.11301-1-richard.henderson@linaro.org

>> ("target/arm: sve1 fixes")

> 

> Are you hoping to squeeze this into 6.0, or can I delay

> review of it in favour of for-6.0 stuff ?


I didn't expect to get it into 6.0.  Too much too late.


r~