| Message ID | 20210304044122.15166-14-kishon@ti.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | PHY: Add support in Sierra to use external clock | expand |
Hi Kishon, > -----Original Message----- > From: Kishon Vijay Abraham I <kishon@ti.com> > Sent: Thursday, March 4, 2021 10:11 AM > To: Kishon Vijay Abraham I <kishon@ti.com>; Vinod Koul > <vkoul@kernel.org>; Rob Herring <robh+dt@kernel.org>; Philipp Zabel > <p.zabel@pengutronix.de>; Swapnil Kashinath Jakhade > <sjakhade@cadence.com> > Cc: linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Lokesh Vutla > <lokeshvutla@ti.com> > Subject: [PATCH v4 13/13] phy: cadence: phy-cadence-sierra: Enable > pll_cmnlc and pll_cmnlc1 clocks > > EXTERNAL MAIL > > > Get pll_cmnlc and pll_cmnlc1 optional clocks and enable them. > This will enable REFRCV/1 in case the pll_cmnlc/1 takes input > from REFRCV/1 respectively. > > Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> > --- > drivers/phy/cadence/phy-cadence-sierra.c | 40 ++++++++++++++++++++++-- > 1 file changed, 37 insertions(+), 3 deletions(-) > > diff --git a/drivers/phy/cadence/phy-cadence-sierra.c > b/drivers/phy/cadence/phy-cadence-sierra.c > index be2c91be4205..68d81f953f4f 100644 > --- a/drivers/phy/cadence/phy-cadence-sierra.c > +++ b/drivers/phy/cadence/phy-cadence-sierra.c > @@ -768,6 +768,40 @@ static int cdns_sierra_phy_get_clocks(struct > cdns_sierra_phy *sp, > return 0; > } > > +static int cdns_sierra_phy_enable_clocks(struct cdns_sierra_phy *sp) > +{ > + int ret; > + > + ret = clk_prepare_enable(sp->input_clks[PLL0_REFCLK]); Should be PHY_CLK instead of PLL0_REFCLK ? > + if (ret) > + return ret; > + > + ret = clk_prepare_enable(sp- > >output_clks[CDNS_SIERRA_PLL_CMNLC]); > + if (ret) > + goto err_pll_cmnlc; > + > + ret = clk_prepare_enable(sp- > >output_clks[CDNS_SIERRA_PLL_CMNLC1]); > + if (ret) > + goto err_pll_cmnlc1; > + > + return 0; > + > +err_pll_cmnlc: > + clk_disable_unprepare(sp->input_clks[PHY_CLK]); > + > +err_pll_cmnlc1: > + clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]); > + Error handling above looks incorrect. Also should this error path return ret instead of 0 ? > + return 0; > +} > + > +static void cdns_sierra_phy_disable_clocks(struct cdns_sierra_phy *sp) > +{ > + clk_disable_unprepare(sp- > >output_clks[CDNS_SIERRA_PLL_CMNLC1]); > + clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]); > + clk_disable_unprepare(sp->input_clks[PHY_CLK]); > +} > + > static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp, > struct device *dev) > { > @@ -848,7 +882,7 @@ static int cdns_sierra_phy_probe(struct > platform_device *pdev) > if (ret) > goto unregister_clk; > > - ret = clk_prepare_enable(sp->input_clks[PHY_CLK]); > + ret = cdns_sierra_phy_enable_clocks(sp); > if (ret) > goto unregister_clk; > > @@ -925,7 +959,7 @@ static int cdns_sierra_phy_probe(struct > platform_device *pdev) > reset_control_put(sp->phys[i].lnk_rst); > of_node_put(child); > clk_disable: > - clk_disable_unprepare(sp->input_clks[PHY_CLK]); > + cdns_sierra_phy_disable_clocks(sp); > reset_control_assert(sp->apb_rst); > unregister_clk: > cdns_sierra_clk_register(sp); > @@ -941,6 +975,7 @@ static int cdns_sierra_phy_remove(struct > platform_device *pdev) > reset_control_assert(phy->apb_rst); > pm_runtime_disable(&pdev->dev); > > + cdns_sierra_phy_disable_clocks(phy); > /* > * The device level resets will be put automatically. > * Need to put the subnode resets here though. > @@ -950,7 +985,6 @@ static int cdns_sierra_phy_remove(struct > platform_device *pdev) > reset_control_put(phy->phys[i].lnk_rst); > } > > - clk_disable_unprepare(phy->input_clks[PHY_CLK]); > cdns_sierra_clk_unregister(phy); > > return 0; > -- > 2.17.1 Thanks & regards, Swapnil
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index be2c91be4205..68d81f953f4f 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -768,6 +768,40 @@ static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp, return 0; } +static int cdns_sierra_phy_enable_clocks(struct cdns_sierra_phy *sp) +{ + int ret; + + ret = clk_prepare_enable(sp->input_clks[PLL0_REFCLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]); + if (ret) + goto err_pll_cmnlc; + + ret = clk_prepare_enable(sp->output_clks[CDNS_SIERRA_PLL_CMNLC1]); + if (ret) + goto err_pll_cmnlc1; + + return 0; + +err_pll_cmnlc: + clk_disable_unprepare(sp->input_clks[PHY_CLK]); + +err_pll_cmnlc1: + clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]); + + return 0; +} + +static void cdns_sierra_phy_disable_clocks(struct cdns_sierra_phy *sp) +{ + clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC1]); + clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]); + clk_disable_unprepare(sp->input_clks[PHY_CLK]); +} + static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp, struct device *dev) { @@ -848,7 +882,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) if (ret) goto unregister_clk; - ret = clk_prepare_enable(sp->input_clks[PHY_CLK]); + ret = cdns_sierra_phy_enable_clocks(sp); if (ret) goto unregister_clk; @@ -925,7 +959,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) reset_control_put(sp->phys[i].lnk_rst); of_node_put(child); clk_disable: - clk_disable_unprepare(sp->input_clks[PHY_CLK]); + cdns_sierra_phy_disable_clocks(sp); reset_control_assert(sp->apb_rst); unregister_clk: cdns_sierra_clk_register(sp); @@ -941,6 +975,7 @@ static int cdns_sierra_phy_remove(struct platform_device *pdev) reset_control_assert(phy->apb_rst); pm_runtime_disable(&pdev->dev); + cdns_sierra_phy_disable_clocks(phy); /* * The device level resets will be put automatically. * Need to put the subnode resets here though. @@ -950,7 +985,6 @@ static int cdns_sierra_phy_remove(struct platform_device *pdev) reset_control_put(phy->phys[i].lnk_rst); } - clk_disable_unprepare(phy->input_clks[PHY_CLK]); cdns_sierra_clk_unregister(phy); return 0;
Get pll_cmnlc and pll_cmnlc1 optional clocks and enable them. This will enable REFRCV/1 in case the pll_cmnlc/1 takes input from REFRCV/1 respectively. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- drivers/phy/cadence/phy-cadence-sierra.c | 40 ++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 3 deletions(-) -- 2.17.1