| Message ID | 20210212163526.69422-1-krzk@kernel.org |
|---|---|
| State | New |
| Headers | show |
| Series | [RFT] crypto: s5p-sss - initialize APB clock after the AXI bus clock for SlimSSS | expand |
On Fri, Feb 12, 2021 at 05:35:26PM +0100, Krzysztof Kozlowski wrote: > The driver for Slim Security Subsystem (SlimSSS) on Exynos5433 takes two > clocks - aclk (AXI/AHB clock) and pclk (APB/Advanced Peripheral Bus > clock). The "aclk", as main high speed bus clock, is enabled first. Then > the "pclk" is enabled. > > However the driver assigned reversed names for lookup of these clocks > from devicetree, so effectively the "pclk" was enabled first. > > Although it might not matter in reality, the correct order is to enable > first main/high speed bus clock - "aclk". Also this was the intention > of the actual code. > > Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> > > --- > > Not tested, please kindly test on Exynos5433 hardware. > --- > drivers/crypto/s5p-sss.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Patch applied. Thanks. -- Email: Herbert Xu <herbert@gondor.apana.org.au> Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c index 682c8a450a57..8ed08130196f 100644 --- a/drivers/crypto/s5p-sss.c +++ b/drivers/crypto/s5p-sss.c @@ -401,7 +401,7 @@ static const struct samsung_aes_variant exynos_aes_data = { static const struct samsung_aes_variant exynos5433_slim_aes_data = { .aes_offset = 0x400, .hash_offset = 0x800, - .clk_names = { "pclk", "aclk", }, + .clk_names = { "aclk", "pclk", }, }; static const struct of_device_id s5p_sss_dt_match[] = {
The driver for Slim Security Subsystem (SlimSSS) on Exynos5433 takes two clocks - aclk (AXI/AHB clock) and pclk (APB/Advanced Peripheral Bus clock). The "aclk", as main high speed bus clock, is enabled first. Then the "pclk" is enabled. However the driver assigned reversed names for lookup of these clocks from devicetree, so effectively the "pclk" was enabled first. Although it might not matter in reality, the correct order is to enable first main/high speed bus clock - "aclk". Also this was the intention of the actual code. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> --- Not tested, please kindly test on Exynos5433 hardware. --- drivers/crypto/s5p-sss.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)