| Message ID | 20210215190322.22094-1-marten.lindahl@axis.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | i2c: exynos5: Preserve high speed master code | expand |
On Mon, Feb 15, 2021 at 08:03:21PM +0100, Mårten Lindahl wrote: > From: Mårten Lindahl <martenli@axis.com> > > When the controller starts to send a message with the MASTER_ID field > set (high speed), the whole I2C_ADDR register is overwritten including > MASTER_ID as the SLV_ADDR_MAS field is set. Are you here describing bug in driver or hardware (the controller?)? Looking at the code, I think the driver, but description got me confused. > > This patch preserves already written fields in I2C_ADDR when writing > SLV_ADDR_MAS. > > Signed-off-by: Mårten Lindahl <martenli@axis.com> > --- > drivers/i2c/busses/i2c-exynos5.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c > index 20a9881a0d6c..f2d04c241299 100644 > --- a/drivers/i2c/busses/i2c-exynos5.c > +++ b/drivers/i2c/busses/i2c-exynos5.c > @@ -606,6 +606,7 @@ static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop) > u32 i2c_ctl; > u32 int_en = 0; > u32 i2c_auto_conf = 0; > + u32 i2c_addr = 0; > u32 fifo_ctl; > unsigned long flags; > unsigned short trig_lvl; > @@ -640,7 +641,12 @@ static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop) > int_en |= HSI2C_INT_TX_ALMOSTEMPTY_EN; > } > > - writel(HSI2C_SLV_ADDR_MAS(i2c->msg->addr), i2c->regs + HSI2C_ADDR); > + i2c_addr = HSI2C_SLV_ADDR_MAS(i2c->msg->addr); > + > + if (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ) > + i2c_addr |= readl(i2c->regs + HSI2C_ADDR); Any reason why not "|= MASTER_ID(i2c->adap.nr)" here instead of more expensive IO read? It's quite important because your current code will bitwise-or old I2C slave address with a new one... This should break during tests with multiple I2C slave devices, shouldn't it? On which HW did you test it? Best regards, Krzysztof > + > + writel(i2c_addr, i2c->regs + HSI2C_ADDR);
Hi Krzysztof! Thank you for your comments! Please see my reply below. I will send v2 in a moment. On Tue, Feb 16, 2021 at 08:51:41AM +0100, Krzysztof Kozlowski wrote: > On Mon, Feb 15, 2021 at 08:03:21PM +0100, Mårten Lindahl wrote: > > From: Mårten Lindahl <martenli@axis.com> > > > > When the controller starts to send a message with the MASTER_ID field > > set (high speed), the whole I2C_ADDR register is overwritten including > > MASTER_ID as the SLV_ADDR_MAS field is set. > > Are you here describing bug in driver or hardware (the controller?)? > Looking at the code, I think the driver, but description got me > confused. > Yes, it is the driver. I will change. > > > > This patch preserves already written fields in I2C_ADDR when writing > > SLV_ADDR_MAS. > > > > Signed-off-by: Mårten Lindahl <martenli@axis.com> > > --- > > drivers/i2c/busses/i2c-exynos5.c | 8 +++++++- > > 1 file changed, 7 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c > > index 20a9881a0d6c..f2d04c241299 100644 > > --- a/drivers/i2c/busses/i2c-exynos5.c > > +++ b/drivers/i2c/busses/i2c-exynos5.c > > @@ -606,6 +606,7 @@ static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop) > > u32 i2c_ctl; > > u32 int_en = 0; > > u32 i2c_auto_conf = 0; > > + u32 i2c_addr = 0; > > u32 fifo_ctl; > > unsigned long flags; > > unsigned short trig_lvl; > > @@ -640,7 +641,12 @@ static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop) > > int_en |= HSI2C_INT_TX_ALMOSTEMPTY_EN; > > } > > > > - writel(HSI2C_SLV_ADDR_MAS(i2c->msg->addr), i2c->regs + HSI2C_ADDR); > > + i2c_addr = HSI2C_SLV_ADDR_MAS(i2c->msg->addr); > > + > > + if (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ) > > + i2c_addr |= readl(i2c->regs + HSI2C_ADDR); > > Any reason why not "|= MASTER_ID(i2c->adap.nr)" here instead of more > expensive IO read? It's quite important because your current code will > bitwise-or old I2C slave address with a new one... This should break > during tests with multiple I2C slave devices, shouldn't it? > You are correct. It is better to use the macro instead, and yes, safer too. I only have one device that supports high speed i2c, but I get your point. It could potentially break. > On which HW did you test it? I used an Artpec development board as master and INA230EVM board as slave. > > Best regards, > Krzysztof > Best regards Mårten > > > + > > + writel(i2c_addr, i2c->regs + HSI2C_ADDR);
On Tue, Feb 16, 2021 at 11:09:33PM +0100, Marten Lindahl wrote: > > Any reason why not "|= MASTER_ID(i2c->adap.nr)" here instead of more > > expensive IO read? It's quite important because your current code will > > bitwise-or old I2C slave address with a new one... This should break > > during tests with multiple I2C slave devices, shouldn't it? > > > > You are correct. It is better to use the macro instead, and yes, > safer too. I only have one device that supports high speed i2c, but > I get your point. It could potentially break. > > > On which HW did you test it? > > I used an Artpec development board as master and INA230EVM board > as slave. Artpec development board with? What SoC? Best regards, Krzysztof
On Wed, Feb 17, 2021 at 09:07:47AM +0100, Krzysztof Kozlowski wrote: > On Tue, Feb 16, 2021 at 11:09:33PM +0100, Marten Lindahl wrote: > > > Any reason why not "|= MASTER_ID(i2c->adap.nr)" here instead of more > > > expensive IO read? It's quite important because your current code will > > > bitwise-or old I2C slave address with a new one... This should break > > > during tests with multiple I2C slave devices, shouldn't it? > > > > > > > You are correct. It is better to use the macro instead, and yes, > > safer too. I only have one device that supports high speed i2c, but > > I get your point. It could potentially break. > > > > > On which HW did you test it? > > > > I used an Artpec development board as master and INA230EVM board > > as slave. > > Artpec development board with? What SoC? The ARTPEC-line of SoC:s are Axis Communications own ASICs, in the latest iteration it's a Cortex-53 and includes instances of the exynos5 HSI2C ip. > Best regards, > Krzysztof /^JN - Jesper Nilsson -- Jesper Nilsson -- jesper.nilsson@axis.com
On Wed, Feb 17, 2021 at 09:32:11AM +0100, Jesper Nilsson wrote: > On Wed, Feb 17, 2021 at 09:07:47AM +0100, Krzysztof Kozlowski wrote: > > On Tue, Feb 16, 2021 at 11:09:33PM +0100, Marten Lindahl wrote: > > > > Any reason why not "|= MASTER_ID(i2c->adap.nr)" here instead of more > > > > expensive IO read? It's quite important because your current code will > > > > bitwise-or old I2C slave address with a new one... This should break > > > > during tests with multiple I2C slave devices, shouldn't it? > > > > > > > > > > You are correct. It is better to use the macro instead, and yes, > > > safer too. I only have one device that supports high speed i2c, but > > > I get your point. It could potentially break. > > > > > > > On which HW did you test it? > > > > > > I used an Artpec development board as master and INA230EVM board > > > as slave. > > > > Artpec development board with? What SoC? > > The ARTPEC-line of SoC:s are Axis Communications own ASICs, in the latest iteration > it's a Cortex-53 and includes instances of the exynos5 HSI2C ip. Cool! Good to see that this code is re-used. :) Best regards, Krzysztof
diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c index 20a9881a0d6c..f2d04c241299 100644 --- a/drivers/i2c/busses/i2c-exynos5.c +++ b/drivers/i2c/busses/i2c-exynos5.c @@ -606,6 +606,7 @@ static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop) u32 i2c_ctl; u32 int_en = 0; u32 i2c_auto_conf = 0; + u32 i2c_addr = 0; u32 fifo_ctl; unsigned long flags; unsigned short trig_lvl; @@ -640,7 +641,12 @@ static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop) int_en |= HSI2C_INT_TX_ALMOSTEMPTY_EN; } - writel(HSI2C_SLV_ADDR_MAS(i2c->msg->addr), i2c->regs + HSI2C_ADDR); + i2c_addr = HSI2C_SLV_ADDR_MAS(i2c->msg->addr); + + if (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ) + i2c_addr |= readl(i2c->regs + HSI2C_ADDR); + + writel(i2c_addr, i2c->regs + HSI2C_ADDR); writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL); writel(i2c_ctl, i2c->regs + HSI2C_CTL);