| Message ID | 20210210000259.635748-1-ben.widawsky@intel.com |
|---|---|
| Headers | show |
| Series | CXL 2.0 Support | expand |
On Tue, 9 Feb 2021 16:02:53 -0800 Ben Widawsky <ben.widawsky@intel.com> wrote: > Provide enough functionality to utilize the mailbox of a memory device. > The mailbox is used to interact with the firmware running on the memory > device. The flow is proven with one implemented command, "identify". > Because the class code has already told the driver this is a memory > device and the identify command is mandatory. > > CXL devices contain an array of capabilities that describe the > interactions software can have with the device or firmware running on > the device. A CXL compliant device must implement the device status and > the mailbox capability. Additionally, a CXL compliant memory device must > implement the memory device capability. Each of the capabilities can > [will] provide an offset within the MMIO region for interacting with the > CXL device. > > The capabilities tell the driver how to find and map the register space > for CXL Memory Devices. The registers are required to utilize the CXL > spec defined mailbox interface. The spec outlines two mailboxes, primary > and secondary. The secondary mailbox is earmarked for system firmware, > and not handled in this driver. > > Primary mailboxes are capable of generating an interrupt when submitting > a background command. That implementation is saved for a later time. > > Link: https://www.computeexpresslink.org/download-the-specification > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> > Reviewed-by: Dan Williams <dan.j.williams@intel.com> Hi Ben, > +/** > + * cxl_mem_mbox_send_cmd() - Send a mailbox command to a memory device. > + * @cxlm: The CXL memory device to communicate with. > + * @mbox_cmd: Command to send to the memory device. > + * > + * Context: Any context. Expects mbox_lock to be held. > + * Return: -ETIMEDOUT if timeout occurred waiting for completion. 0 on success. > + * Caller should check the return code in @mbox_cmd to make sure it > + * succeeded. cxl_xfer_log() doesn't check mbox_cmd->return_code and for my test it currently enters an infinite loop as a result. I haven't checked other paths, but to my mind it is not a good idea to require two levels of error checking - the example here proves how easy it is to forget one. Now all I have to do is figure out why I'm getting an error in the first place! Jonathan > + * > + * This is a generic form of the CXL mailbox send command, thus the only I/O > + * operations used are cxl_read_mbox_reg(). Memory devices, and perhaps other > + * types of CXL devices may have further information available upon error > + * conditions. > + * > + * The CXL spec allows for up to two mailboxes. The intention is for the primary > + * mailbox to be OS controlled and the secondary mailbox to be used by system > + * firmware. This allows the OS and firmware to communicate with the device and > + * not need to coordinate with each other. The driver only uses the primary > + * mailbox. > + */ > +static int cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, > + struct mbox_cmd *mbox_cmd) > +{ > + void __iomem *payload = cxlm->mbox_regs + CXLDEV_MBOX_PAYLOAD_OFFSET; > + u64 cmd_reg, status_reg; > + size_t out_len; > + int rc; > + > + lockdep_assert_held(&cxlm->mbox_mutex); > + > + /* > + * Here are the steps from 8.2.8.4 of the CXL 2.0 spec. > + * 1. Caller reads MB Control Register to verify doorbell is clear > + * 2. Caller writes Command Register > + * 3. Caller writes Command Payload Registers if input payload is non-empty > + * 4. Caller writes MB Control Register to set doorbell > + * 5. Caller either polls for doorbell to be clear or waits for interrupt if configured > + * 6. Caller reads MB Status Register to fetch Return code > + * 7. If command successful, Caller reads Command Register to get Payload Length > + * 8. If output payload is non-empty, host reads Command Payload Registers > + * > + * Hardware is free to do whatever it wants before the doorbell is rung, > + * and isn't allowed to change anything after it clears the doorbell. As > + * such, steps 2 and 3 can happen in any order, and steps 6, 7, 8 can > + * also happen in any order (though some orders might not make sense). > + */ > + > + /* #1 */ > + if (cxl_doorbell_busy(cxlm)) { > + dev_err_ratelimited(&cxlm->pdev->dev, > + "Mailbox re-busy after acquiring\n"); > + return -EBUSY; > + } > + > + cmd_reg = FIELD_PREP(CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK, > + mbox_cmd->opcode); > + if (mbox_cmd->size_in) { > + if (WARN_ON(!mbox_cmd->payload_in)) > + return -EINVAL; > + > + cmd_reg |= FIELD_PREP(CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK, > + mbox_cmd->size_in); > + memcpy_toio(payload, mbox_cmd->payload_in, mbox_cmd->size_in); > + } > + > + /* #2, #3 */ > + writeq(cmd_reg, cxlm->mbox_regs + CXLDEV_MBOX_CMD_OFFSET); > + > + /* #4 */ > + dev_dbg(&cxlm->pdev->dev, "Sending command\n"); > + writel(CXLDEV_MBOX_CTRL_DOORBELL, > + cxlm->mbox_regs + CXLDEV_MBOX_CTRL_OFFSET); > + > + /* #5 */ > + rc = cxl_mem_wait_for_doorbell(cxlm); > + if (rc == -ETIMEDOUT) { > + cxl_mem_mbox_timeout(cxlm, mbox_cmd); > + return rc; > + } > + > + /* #6 */ > + status_reg = readq(cxlm->mbox_regs + CXLDEV_MBOX_STATUS_OFFSET); > + mbox_cmd->return_code = > + FIELD_GET(CXLDEV_MBOX_STATUS_RET_CODE_MASK, status_reg); > + > + if (mbox_cmd->return_code != 0) { > + dev_dbg(&cxlm->pdev->dev, "Mailbox operation had an error\n"); > + return 0; I'd return some sort of error in this path. Otherwise the sort of missing handling I mention above is too easy to hit. > + } > + > + /* #7 */ > + cmd_reg = readq(cxlm->mbox_regs + CXLDEV_MBOX_CMD_OFFSET); > + out_len = FIELD_GET(CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK, cmd_reg); > + > + /* #8 */ > + if (out_len && mbox_cmd->payload_out) > + memcpy_fromio(mbox_cmd->payload_out, payload, out_len); > + > + mbox_cmd->size_out = out_len; > + > + return 0; > +} > + > +/** > + * cxl_mem_mbox_get() - Acquire exclusive access to the mailbox. > + * @cxlm: The memory device to gain access to. > + * > + * Context: Any context. Takes the mbox_lock. > + * Return: 0 if exclusive access was acquired. > + */ > +static int cxl_mem_mbox_get(struct cxl_mem *cxlm) > +{ > + struct device *dev = &cxlm->pdev->dev; > + int rc = -EBUSY; > + u64 md_status; > + > + mutex_lock_io(&cxlm->mbox_mutex); > + > + /* > + * XXX: There is some amount of ambiguity in the 2.0 version of the spec > + * around the mailbox interface ready (8.2.8.5.1.1). The purpose of the > + * bit is to allow firmware running on the device to notify the driver > + * that it's ready to receive commands. It is unclear if the bit needs > + * to be read for each transaction mailbox, ie. the firmware can switch > + * it on and off as needed. Second, there is no defined timeout for > + * mailbox ready, like there is for the doorbell interface. > + * > + * Assumptions: > + * 1. The firmware might toggle the Mailbox Interface Ready bit, check > + * it for every command. > + * > + * 2. If the doorbell is clear, the firmware should have first set the > + * Mailbox Interface Ready bit. Therefore, waiting for the doorbell > + * to be ready is sufficient. > + */ > + rc = cxl_mem_wait_for_doorbell(cxlm); > + if (rc) { > + dev_warn(dev, "Mailbox interface not ready\n"); > + goto out; > + } > + > + md_status = readq(cxlm->memdev_regs + CXLMDEV_STATUS_OFFSET); > + if (!(md_status & CXLMDEV_MBOX_IF_READY && CXLMDEV_READY(md_status))) { > + dev_err(dev, > + "mbox: reported doorbell ready, but not mbox ready\n"); > + goto out; > + } > + > + /* > + * Hardware shouldn't allow a ready status but also have failure bits > + * set. Spit out an error, this should be a bug report > + */ > + rc = -EFAULT; > + if (md_status & CXLMDEV_DEV_FATAL) { > + dev_err(dev, "mbox: reported ready, but fatal\n"); > + goto out; > + } > + if (md_status & CXLMDEV_FW_HALT) { > + dev_err(dev, "mbox: reported ready, but halted\n"); > + goto out; > + } > + if (CXLMDEV_RESET_NEEDED(md_status)) { > + dev_err(dev, "mbox: reported ready, but reset needed\n"); > + goto out; > + } > + > + /* with lock held */ > + return 0; > + > +out: > + mutex_unlock(&cxlm->mbox_mutex); > + return rc; > +} > + > +/** > + * cxl_mem_mbox_put() - Release exclusive access to the mailbox. > + * @cxlm: The CXL memory device to communicate with. > + * > + * Context: Any context. Expects mbox_lock to be held. > + */ > +static void cxl_mem_mbox_put(struct cxl_mem *cxlm) > +{ > + mutex_unlock(&cxlm->mbox_mutex); > +} > + > +/** > + * cxl_mem_setup_regs() - Setup necessary MMIO. > + * @cxlm: The CXL memory device to communicate with. > + * > + * Return: 0 if all necessary registers mapped. > + * > + * A memory device is required by spec to implement a certain set of MMIO > + * regions. The purpose of this function is to enumerate and map those > + * registers. > + */ > +static int cxl_mem_setup_regs(struct cxl_mem *cxlm) > +{ > + struct device *dev = &cxlm->pdev->dev; > + int cap, cap_count; > + u64 cap_array; > + > + cap_array = readq(cxlm->regs + CXLDEV_CAP_ARRAY_OFFSET); > + if (FIELD_GET(CXLDEV_CAP_ARRAY_ID_MASK, cap_array) != > + CXLDEV_CAP_ARRAY_CAP_ID) > + return -ENODEV; > + > + cap_count = FIELD_GET(CXLDEV_CAP_ARRAY_COUNT_MASK, cap_array); > + > + for (cap = 1; cap <= cap_count; cap++) { > + void __iomem *register_block; > + u32 offset; > + u16 cap_id; > + > + cap_id = readl(cxlm->regs + cap * 0x10) & 0xffff; > + offset = readl(cxlm->regs + cap * 0x10 + 0x4); > + register_block = cxlm->regs + offset; > + > + switch (cap_id) { > + case CXLDEV_CAP_CAP_ID_DEVICE_STATUS: > + dev_dbg(dev, "found Status capability (0x%x)\n", offset); > + cxlm->status_regs = register_block; > + break; > + case CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX: > + dev_dbg(dev, "found Mailbox capability (0x%x)\n", offset); > + cxlm->mbox_regs = register_block; > + break; > + case CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX: > + dev_dbg(dev, "found Secondary Mailbox capability (0x%x)\n", offset); > + break; > + case CXLDEV_CAP_CAP_ID_MEMDEV: > + dev_dbg(dev, "found Memory Device capability (0x%x)\n", offset); > + cxlm->memdev_regs = register_block; > + break; > + default: > + dev_dbg(dev, "Unknown cap ID: %d (0x%x)\n", cap_id, offset); > + break; > + } > + } > + > + if (!cxlm->status_regs || !cxlm->mbox_regs || !cxlm->memdev_regs) { > + dev_err(dev, "registers not found: %s%s%s\n", > + !cxlm->status_regs ? "status " : "", > + !cxlm->mbox_regs ? "mbox " : "", > + !cxlm->memdev_regs ? "memdev" : ""); > + return -ENXIO; > + } > + > + return 0; > +} > + > +static int cxl_mem_setup_mailbox(struct cxl_mem *cxlm) > +{ > + const int cap = readl(cxlm->mbox_regs + CXLDEV_MBOX_CAPS_OFFSET); > + > + cxlm->payload_size = > + 1 << FIELD_GET(CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK, cap); > + > + /* > + * CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register > + * > + * If the size is too small, mandatory commands will not work and so > + * there's no point in going forward. If the size is too large, there's > + * no harm is soft limiting it. > + */ > + cxlm->payload_size = min_t(size_t, cxlm->payload_size, SZ_1M); > + if (cxlm->payload_size < 256) { > + dev_err(&cxlm->pdev->dev, "Mailbox is too small (%zub)", > + cxlm->payload_size); > + return -ENXIO; > + } > + > + dev_dbg(&cxlm->pdev->dev, "Mailbox payload sized %zu", > + cxlm->payload_size); > + > + return 0; > +} > + > +static struct cxl_mem *cxl_mem_create(struct pci_dev *pdev, u32 reg_lo, > + u32 reg_hi) > +{ > + struct device *dev = &pdev->dev; > + struct cxl_mem *cxlm; > + void __iomem *regs; > + u64 offset; > + u8 bar; > + int rc; > + > + cxlm = devm_kzalloc(&pdev->dev, sizeof(*cxlm), GFP_KERNEL); > + if (!cxlm) { > + dev_err(dev, "No memory available\n"); > + return NULL; > + } > + > + offset = ((u64)reg_hi << 32) | FIELD_GET(CXL_REGLOC_ADDR_MASK, reg_lo); > + bar = FIELD_GET(CXL_REGLOC_BIR_MASK, reg_lo); > + > + /* Basic sanity check that BAR is big enough */ > + if (pci_resource_len(pdev, bar) < offset) { > + dev_err(dev, "BAR%d: %pr: too small (offset: %#llx)\n", bar, > + &pdev->resource[bar], (unsigned long long)offset); > + return NULL; > + } > + > + rc = pcim_iomap_regions(pdev, BIT(bar), pci_name(pdev)); > + if (rc != 0) { > + dev_err(dev, "failed to map registers\n"); > + return NULL; > + } > + regs = pcim_iomap_table(pdev)[bar]; > + > + mutex_init(&cxlm->mbox_mutex); > + cxlm->pdev = pdev; > + cxlm->regs = regs + offset; > + > + dev_dbg(dev, "Mapped CXL Memory Device resource\n"); > + return cxlm; > +} > > static int cxl_mem_dvsec(struct pci_dev *pdev, int dvsec) > { > @@ -28,10 +423,85 @@ static int cxl_mem_dvsec(struct pci_dev *pdev, int dvsec) > return 0; > } > > +/** > + * cxl_mem_identify() - Send the IDENTIFY command to the device. > + * @cxlm: The device to identify. > + * > + * Return: 0 if identify was executed successfully. > + * > + * This will dispatch the identify command to the device and on success populate > + * structures to be exported to sysfs. > + */ > +static int cxl_mem_identify(struct cxl_mem *cxlm) > +{ > + struct cxl_mbox_identify { > + char fw_revision[0x10]; > + __le64 total_capacity; > + __le64 volatile_capacity; > + __le64 persistent_capacity; > + __le64 partition_align; > + __le16 info_event_log_size; > + __le16 warning_event_log_size; > + __le16 failure_event_log_size; > + __le16 fatal_event_log_size; > + __le32 lsa_size; > + u8 poison_list_max_mer[3]; > + __le16 inject_poison_limit; > + u8 poison_caps; > + u8 qos_telemetry_caps; > + } __packed id; > + struct mbox_cmd mbox_cmd = { > + .opcode = CXL_MBOX_OP_IDENTIFY, > + .payload_out = &id, > + .size_in = 0, > + }; > + int rc; > + > + /* Retrieve initial device memory map */ > + rc = cxl_mem_mbox_get(cxlm); > + if (rc) > + return rc; > + > + rc = cxl_mem_mbox_send_cmd(cxlm, &mbox_cmd); > + cxl_mem_mbox_put(cxlm); > + if (rc) > + return rc; > + > + /* TODO: Handle retry or reset responses from firmware. */ > + if (mbox_cmd.return_code != CXL_MBOX_SUCCESS) { > + dev_err(&cxlm->pdev->dev, "Mailbox command failed (%d)\n", > + mbox_cmd.return_code); > + return -ENXIO; > + } > + > + if (mbox_cmd.size_out != sizeof(id)) > + return -ENXIO; > + > + /* > + * TODO: enumerate DPA map, as 'ram' and 'pmem' do not alias. > + * For now, only the capacity is exported in sysfs > + */ > + cxlm->ram.range.start = 0; > + cxlm->ram.range.end = le64_to_cpu(id.volatile_capacity) - 1; > + > + cxlm->pmem.range.start = 0; > + cxlm->pmem.range.end = le64_to_cpu(id.persistent_capacity) - 1; > + > + memcpy(cxlm->firmware_version, id.fw_revision, sizeof(id.fw_revision)); > + > + return rc; > +} > + > static int cxl_mem_probe(struct pci_dev *pdev, const struct pci_device_id *id) > { > struct device *dev = &pdev->dev; > - int regloc; > + struct cxl_mem *cxlm; > + int rc, regloc, i; > + u32 regloc_size; > + > + rc = pcim_enable_device(pdev); > + if (rc) > + return rc; > > regloc = cxl_mem_dvsec(pdev, PCI_DVSEC_ID_CXL_REGLOC_OFFSET); > if (!regloc) { > @@ -39,7 +509,44 @@ static int cxl_mem_probe(struct pci_dev *pdev, const struct pci_device_id *id) > return -ENXIO; > } > > - return 0; > + /* Get the size of the Register Locator DVSEC */ > + pci_read_config_dword(pdev, regloc + PCI_DVSEC_HEADER1, ®loc_size); > + regloc_size = FIELD_GET(PCI_DVSEC_HEADER1_LENGTH_MASK, regloc_size); > + > + regloc += PCI_DVSEC_ID_CXL_REGLOC_BLOCK1_OFFSET; > + > + rc = -ENXIO; > + for (i = regloc; i < regloc + regloc_size; i += 8) { > + u32 reg_lo, reg_hi; > + u8 reg_type; > + > + /* "register low and high" contain other bits */ > + pci_read_config_dword(pdev, i, ®_lo); > + pci_read_config_dword(pdev, i + 4, ®_hi); > + > + reg_type = FIELD_GET(CXL_REGLOC_RBI_MASK, reg_lo); > + > + if (reg_type == CXL_REGLOC_RBI_MEMDEV) { > + rc = 0; > + cxlm = cxl_mem_create(pdev, reg_lo, reg_hi); > + if (!cxlm) > + rc = -ENODEV; > + break; > + } > + } > + > + if (rc) > + return rc; > + > + rc = cxl_mem_setup_regs(cxlm); > + if (rc) > + return rc; > + > + rc = cxl_mem_setup_mailbox(cxlm); > + if (rc) > + return rc; > + > + return cxl_mem_identify(cxlm); > } > > static const struct pci_device_id cxl_mem_pci_tbl[] = { > diff --git a/drivers/cxl/pci.h b/drivers/cxl/pci.h > index f135b9f7bb21..ffcbc13d7b5b 100644 > --- a/drivers/cxl/pci.h > +++ b/drivers/cxl/pci.h > @@ -14,5 +14,18 @@ > #define PCI_DVSEC_ID_CXL 0x0 > > #define PCI_DVSEC_ID_CXL_REGLOC_OFFSET 0x8 > +#define PCI_DVSEC_ID_CXL_REGLOC_BLOCK1_OFFSET 0xC > + > +/* BAR Indicator Register (BIR) */ > +#define CXL_REGLOC_BIR_MASK GENMASK(2, 0) > + > +/* Register Block Identifier (RBI) */ > +#define CXL_REGLOC_RBI_MASK GENMASK(15, 8) > +#define CXL_REGLOC_RBI_EMPTY 0 > +#define CXL_REGLOC_RBI_COMPONENT 1 > +#define CXL_REGLOC_RBI_VIRT 2 > +#define CXL_REGLOC_RBI_MEMDEV 3 > + > +#define CXL_REGLOC_ADDR_MASK GENMASK(31, 16) > > #endif /* __CXL_PCI_H__ */ > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > index e709ae8235e7..6267ca9ae683 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -1080,6 +1080,7 @@ > > /* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */ > #define PCI_DVSEC_HEADER1 0x4 /* Designated Vendor-Specific Header1 */ > +#define PCI_DVSEC_HEADER1_LENGTH_MASK 0xFFF00000 > #define PCI_DVSEC_HEADER2 0x8 /* Designated Vendor-Specific Header2 */ > > /* Data Link Feature */
On Wed, 10 Feb 2021 13:32:52 +0000 Jonathan Cameron <Jonathan.Cameron@Huawei.com> wrote: > On Tue, 9 Feb 2021 16:02:53 -0800 > Ben Widawsky <ben.widawsky@intel.com> wrote: > > > Provide enough functionality to utilize the mailbox of a memory device. > > The mailbox is used to interact with the firmware running on the memory > > device. The flow is proven with one implemented command, "identify". > > Because the class code has already told the driver this is a memory > > device and the identify command is mandatory. > > > > CXL devices contain an array of capabilities that describe the > > interactions software can have with the device or firmware running on > > the device. A CXL compliant device must implement the device status and > > the mailbox capability. Additionally, a CXL compliant memory device must > > implement the memory device capability. Each of the capabilities can > > [will] provide an offset within the MMIO region for interacting with the > > CXL device. > > > > The capabilities tell the driver how to find and map the register space > > for CXL Memory Devices. The registers are required to utilize the CXL > > spec defined mailbox interface. The spec outlines two mailboxes, primary > > and secondary. The secondary mailbox is earmarked for system firmware, > > and not handled in this driver. > > > > Primary mailboxes are capable of generating an interrupt when submitting > > a background command. That implementation is saved for a later time. > > > > Link: https://www.computeexpresslink.org/download-the-specification > > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> > > Reviewed-by: Dan Williams <dan.j.williams@intel.com> > > Hi Ben, > > > > +/** > > + * cxl_mem_mbox_send_cmd() - Send a mailbox command to a memory device. > > + * @cxlm: The CXL memory device to communicate with. > > + * @mbox_cmd: Command to send to the memory device. > > + * > > + * Context: Any context. Expects mbox_lock to be held. > > + * Return: -ETIMEDOUT if timeout occurred waiting for completion. 0 on success. > > + * Caller should check the return code in @mbox_cmd to make sure it > > + * succeeded. > > cxl_xfer_log() doesn't check mbox_cmd->return_code and for my test it currently > enters an infinite loop as a result. > > I haven't checked other paths, but to my mind it is not a good idea to require > two levels of error checking - the example here proves how easy it is to forget > one. > > Now all I have to do is figure out why I'm getting an error in the first place! For reference this seems to be our old issue of arm64 memcpy_fromio() only doing 8 byte or 1 byte copies. The hack in QEMU to allow that to work, doesn't work. Result is that 1 byte reads replicate across the register (in this case instead of 0000001c I get 1c1c1c1c) For these particular registers, we are covered by the rules in 8.2 which says that a 1, 2, 4, 8 aligned reads of 64 bit registers etc are fine. So we should not have to care. This isn't true for the component registers where we need to guarantee 4 or 8 byte reads only. For this particular issue the mailbox_read_reg() function in the QEMU code needs to handle the size 1 case and set min_access_size = 1 for mailbox_ops. Logically it should also handle the 2 byte case I think, but I'm not hitting that. Jonathan > > Jonathan > > > > > + * > > + * This is a generic form of the CXL mailbox send command, thus the only I/O > > + * operations used are cxl_read_mbox_reg(). Memory devices, and perhaps other > > + * types of CXL devices may have further information available upon error > > + * conditions. > > + * > > + * The CXL spec allows for up to two mailboxes. The intention is for the primary > > + * mailbox to be OS controlled and the secondary mailbox to be used by system > > + * firmware. This allows the OS and firmware to communicate with the device and > > + * not need to coordinate with each other. The driver only uses the primary > > + * mailbox. > > + */ > > +static int cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, > > + struct mbox_cmd *mbox_cmd) > > +{ > > + void __iomem *payload = cxlm->mbox_regs + CXLDEV_MBOX_PAYLOAD_OFFSET; > > + u64 cmd_reg, status_reg; > > + size_t out_len; > > + int rc; > > + > > + lockdep_assert_held(&cxlm->mbox_mutex); > > + > > + /* > > + * Here are the steps from 8.2.8.4 of the CXL 2.0 spec. > > + * 1. Caller reads MB Control Register to verify doorbell is clear > > + * 2. Caller writes Command Register > > + * 3. Caller writes Command Payload Registers if input payload is non-empty > > + * 4. Caller writes MB Control Register to set doorbell > > + * 5. Caller either polls for doorbell to be clear or waits for interrupt if configured > > + * 6. Caller reads MB Status Register to fetch Return code > > + * 7. If command successful, Caller reads Command Register to get Payload Length > > + * 8. If output payload is non-empty, host reads Command Payload Registers > > + * > > + * Hardware is free to do whatever it wants before the doorbell is rung, > > + * and isn't allowed to change anything after it clears the doorbell. As > > + * such, steps 2 and 3 can happen in any order, and steps 6, 7, 8 can > > + * also happen in any order (though some orders might not make sense). > > + */ > > + > > + /* #1 */ > > + if (cxl_doorbell_busy(cxlm)) { > > + dev_err_ratelimited(&cxlm->pdev->dev, > > + "Mailbox re-busy after acquiring\n"); > > + return -EBUSY; > > + } > > + > > + cmd_reg = FIELD_PREP(CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK, > > + mbox_cmd->opcode); > > + if (mbox_cmd->size_in) { > > + if (WARN_ON(!mbox_cmd->payload_in)) > > + return -EINVAL; > > + > > + cmd_reg |= FIELD_PREP(CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK, > > + mbox_cmd->size_in); > > + memcpy_toio(payload, mbox_cmd->payload_in, mbox_cmd->size_in); > > + } > > + > > + /* #2, #3 */ > > + writeq(cmd_reg, cxlm->mbox_regs + CXLDEV_MBOX_CMD_OFFSET); > > + > > + /* #4 */ > > + dev_dbg(&cxlm->pdev->dev, "Sending command\n"); > > + writel(CXLDEV_MBOX_CTRL_DOORBELL, > > + cxlm->mbox_regs + CXLDEV_MBOX_CTRL_OFFSET); > > + > > + /* #5 */ > > + rc = cxl_mem_wait_for_doorbell(cxlm); > > + if (rc == -ETIMEDOUT) { > > + cxl_mem_mbox_timeout(cxlm, mbox_cmd); > > + return rc; > > + } > > + > > + /* #6 */ > > + status_reg = readq(cxlm->mbox_regs + CXLDEV_MBOX_STATUS_OFFSET); > > + mbox_cmd->return_code = > > + FIELD_GET(CXLDEV_MBOX_STATUS_RET_CODE_MASK, status_reg); > > + > > + if (mbox_cmd->return_code != 0) { > > + dev_dbg(&cxlm->pdev->dev, "Mailbox operation had an error\n"); > > + return 0; > > I'd return some sort of error in this path. Otherwise the sort of missing > handling I mention above is too easy to hit. > > > + } > > + > > + /* #7 */ > > + cmd_reg = readq(cxlm->mbox_regs + CXLDEV_MBOX_CMD_OFFSET); > > + out_len = FIELD_GET(CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK, cmd_reg); > > + > > + /* #8 */ > > + if (out_len && mbox_cmd->payload_out) > > + memcpy_fromio(mbox_cmd->payload_out, payload, out_len); > > + > > + mbox_cmd->size_out = out_len; > > + > > + return 0; > > +} > > + > > +/** > > + * cxl_mem_mbox_get() - Acquire exclusive access to the mailbox. > > + * @cxlm: The memory device to gain access to. > > + * > > + * Context: Any context. Takes the mbox_lock. > > + * Return: 0 if exclusive access was acquired. > > + */ > > +static int cxl_mem_mbox_get(struct cxl_mem *cxlm) > > +{ > > + struct device *dev = &cxlm->pdev->dev; > > + int rc = -EBUSY; > > + u64 md_status; > > + > > + mutex_lock_io(&cxlm->mbox_mutex); > > + > > + /* > > + * XXX: There is some amount of ambiguity in the 2.0 version of the spec > > + * around the mailbox interface ready (8.2.8.5.1.1). The purpose of the > > + * bit is to allow firmware running on the device to notify the driver > > + * that it's ready to receive commands. It is unclear if the bit needs > > + * to be read for each transaction mailbox, ie. the firmware can switch > > + * it on and off as needed. Second, there is no defined timeout for > > + * mailbox ready, like there is for the doorbell interface. > > + * > > + * Assumptions: > > + * 1. The firmware might toggle the Mailbox Interface Ready bit, check > > + * it for every command. > > + * > > + * 2. If the doorbell is clear, the firmware should have first set the > > + * Mailbox Interface Ready bit. Therefore, waiting for the doorbell > > + * to be ready is sufficient. > > + */ > > + rc = cxl_mem_wait_for_doorbell(cxlm); > > + if (rc) { > > + dev_warn(dev, "Mailbox interface not ready\n"); > > + goto out; > > + } > > + > > + md_status = readq(cxlm->memdev_regs + CXLMDEV_STATUS_OFFSET); > > + if (!(md_status & CXLMDEV_MBOX_IF_READY && CXLMDEV_READY(md_status))) { > > + dev_err(dev, > > + "mbox: reported doorbell ready, but not mbox ready\n"); > > + goto out; > > + } > > + > > + /* > > + * Hardware shouldn't allow a ready status but also have failure bits > > + * set. Spit out an error, this should be a bug report > > + */ > > + rc = -EFAULT; > > + if (md_status & CXLMDEV_DEV_FATAL) { > > + dev_err(dev, "mbox: reported ready, but fatal\n"); > > + goto out; > > + } > > + if (md_status & CXLMDEV_FW_HALT) { > > + dev_err(dev, "mbox: reported ready, but halted\n"); > > + goto out; > > + } > > + if (CXLMDEV_RESET_NEEDED(md_status)) { > > + dev_err(dev, "mbox: reported ready, but reset needed\n"); > > + goto out; > > + } > > + > > + /* with lock held */ > > + return 0; > > + > > +out: > > + mutex_unlock(&cxlm->mbox_mutex); > > + return rc; > > +} > > + > > +/** > > + * cxl_mem_mbox_put() - Release exclusive access to the mailbox. > > + * @cxlm: The CXL memory device to communicate with. > > + * > > + * Context: Any context. Expects mbox_lock to be held. > > + */ > > +static void cxl_mem_mbox_put(struct cxl_mem *cxlm) > > +{ > > + mutex_unlock(&cxlm->mbox_mutex); > > +} > > + > > +/** > > + * cxl_mem_setup_regs() - Setup necessary MMIO. > > + * @cxlm: The CXL memory device to communicate with. > > + * > > + * Return: 0 if all necessary registers mapped. > > + * > > + * A memory device is required by spec to implement a certain set of MMIO > > + * regions. The purpose of this function is to enumerate and map those > > + * registers. > > + */ > > +static int cxl_mem_setup_regs(struct cxl_mem *cxlm) > > +{ > > + struct device *dev = &cxlm->pdev->dev; > > + int cap, cap_count; > > + u64 cap_array; > > + > > + cap_array = readq(cxlm->regs + CXLDEV_CAP_ARRAY_OFFSET); > > + if (FIELD_GET(CXLDEV_CAP_ARRAY_ID_MASK, cap_array) != > > + CXLDEV_CAP_ARRAY_CAP_ID) > > + return -ENODEV; > > + > > + cap_count = FIELD_GET(CXLDEV_CAP_ARRAY_COUNT_MASK, cap_array); > > + > > + for (cap = 1; cap <= cap_count; cap++) { > > + void __iomem *register_block; > > + u32 offset; > > + u16 cap_id; > > + > > + cap_id = readl(cxlm->regs + cap * 0x10) & 0xffff; > > + offset = readl(cxlm->regs + cap * 0x10 + 0x4); > > + register_block = cxlm->regs + offset; > > + > > + switch (cap_id) { > > + case CXLDEV_CAP_CAP_ID_DEVICE_STATUS: > > + dev_dbg(dev, "found Status capability (0x%x)\n", offset); > > + cxlm->status_regs = register_block; > > + break; > > + case CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX: > > + dev_dbg(dev, "found Mailbox capability (0x%x)\n", offset); > > + cxlm->mbox_regs = register_block; > > + break; > > + case CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX: > > + dev_dbg(dev, "found Secondary Mailbox capability (0x%x)\n", offset); > > + break; > > + case CXLDEV_CAP_CAP_ID_MEMDEV: > > + dev_dbg(dev, "found Memory Device capability (0x%x)\n", offset); > > + cxlm->memdev_regs = register_block; > > + break; > > + default: > > + dev_dbg(dev, "Unknown cap ID: %d (0x%x)\n", cap_id, offset); > > + break; > > + } > > + } > > + > > + if (!cxlm->status_regs || !cxlm->mbox_regs || !cxlm->memdev_regs) { > > + dev_err(dev, "registers not found: %s%s%s\n", > > + !cxlm->status_regs ? "status " : "", > > + !cxlm->mbox_regs ? "mbox " : "", > > + !cxlm->memdev_regs ? "memdev" : ""); > > + return -ENXIO; > > + } > > + > > + return 0; > > +} > > + > > +static int cxl_mem_setup_mailbox(struct cxl_mem *cxlm) > > +{ > > + const int cap = readl(cxlm->mbox_regs + CXLDEV_MBOX_CAPS_OFFSET); > > + > > + cxlm->payload_size = > > + 1 << FIELD_GET(CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK, cap); > > + > > + /* > > + * CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register > > + * > > + * If the size is too small, mandatory commands will not work and so > > + * there's no point in going forward. If the size is too large, there's > > + * no harm is soft limiting it. > > + */ > > + cxlm->payload_size = min_t(size_t, cxlm->payload_size, SZ_1M); > > + if (cxlm->payload_size < 256) { > > + dev_err(&cxlm->pdev->dev, "Mailbox is too small (%zub)", > > + cxlm->payload_size); > > + return -ENXIO; > > + } > > + > > + dev_dbg(&cxlm->pdev->dev, "Mailbox payload sized %zu", > > + cxlm->payload_size); > > + > > + return 0; > > +} > > + > > +static struct cxl_mem *cxl_mem_create(struct pci_dev *pdev, u32 reg_lo, > > + u32 reg_hi) > > +{ > > + struct device *dev = &pdev->dev; > > + struct cxl_mem *cxlm; > > + void __iomem *regs; > > + u64 offset; > > + u8 bar; > > + int rc; > > + > > + cxlm = devm_kzalloc(&pdev->dev, sizeof(*cxlm), GFP_KERNEL); > > + if (!cxlm) { > > + dev_err(dev, "No memory available\n"); > > + return NULL; > > + } > > + > > + offset = ((u64)reg_hi << 32) | FIELD_GET(CXL_REGLOC_ADDR_MASK, reg_lo); > > + bar = FIELD_GET(CXL_REGLOC_BIR_MASK, reg_lo); > > + > > + /* Basic sanity check that BAR is big enough */ > > + if (pci_resource_len(pdev, bar) < offset) { > > + dev_err(dev, "BAR%d: %pr: too small (offset: %#llx)\n", bar, > > + &pdev->resource[bar], (unsigned long long)offset); > > + return NULL; > > + } > > + > > + rc = pcim_iomap_regions(pdev, BIT(bar), pci_name(pdev)); > > + if (rc != 0) { > > + dev_err(dev, "failed to map registers\n"); > > + return NULL; > > + } > > + regs = pcim_iomap_table(pdev)[bar]; > > + > > + mutex_init(&cxlm->mbox_mutex); > > + cxlm->pdev = pdev; > > + cxlm->regs = regs + offset; > > + > > + dev_dbg(dev, "Mapped CXL Memory Device resource\n"); > > + return cxlm; > > +} > > > > static int cxl_mem_dvsec(struct pci_dev *pdev, int dvsec) > > { > > @@ -28,10 +423,85 @@ static int cxl_mem_dvsec(struct pci_dev *pdev, int dvsec) > > return 0; > > } > > > > +/** > > + * cxl_mem_identify() - Send the IDENTIFY command to the device. > > + * @cxlm: The device to identify. > > + * > > + * Return: 0 if identify was executed successfully. > > + * > > + * This will dispatch the identify command to the device and on success populate > > + * structures to be exported to sysfs. > > + */ > > +static int cxl_mem_identify(struct cxl_mem *cxlm) > > +{ > > + struct cxl_mbox_identify { > > + char fw_revision[0x10]; > > + __le64 total_capacity; > > + __le64 volatile_capacity; > > + __le64 persistent_capacity; > > + __le64 partition_align; > > + __le16 info_event_log_size; > > + __le16 warning_event_log_size; > > + __le16 failure_event_log_size; > > + __le16 fatal_event_log_size; > > + __le32 lsa_size; > > + u8 poison_list_max_mer[3]; > > + __le16 inject_poison_limit; > > + u8 poison_caps; > > + u8 qos_telemetry_caps; > > + } __packed id; > > + struct mbox_cmd mbox_cmd = { > > + .opcode = CXL_MBOX_OP_IDENTIFY, > > + .payload_out = &id, > > + .size_in = 0, > > + }; > > + int rc; > > + > > + /* Retrieve initial device memory map */ > > + rc = cxl_mem_mbox_get(cxlm); > > + if (rc) > > + return rc; > > + > > + rc = cxl_mem_mbox_send_cmd(cxlm, &mbox_cmd); > > + cxl_mem_mbox_put(cxlm); > > + if (rc) > > + return rc; > > + > > + /* TODO: Handle retry or reset responses from firmware. */ > > + if (mbox_cmd.return_code != CXL_MBOX_SUCCESS) { > > + dev_err(&cxlm->pdev->dev, "Mailbox command failed (%d)\n", > > + mbox_cmd.return_code); > > + return -ENXIO; > > + } > > + > > + if (mbox_cmd.size_out != sizeof(id)) > > + return -ENXIO; > > + > > + /* > > + * TODO: enumerate DPA map, as 'ram' and 'pmem' do not alias. > > + * For now, only the capacity is exported in sysfs > > + */ > > + cxlm->ram.range.start = 0; > > + cxlm->ram.range.end = le64_to_cpu(id.volatile_capacity) - 1; > > + > > + cxlm->pmem.range.start = 0; > > + cxlm->pmem.range.end = le64_to_cpu(id.persistent_capacity) - 1; > > + > > + memcpy(cxlm->firmware_version, id.fw_revision, sizeof(id.fw_revision)); > > + > > + return rc; > > +} > > + > > static int cxl_mem_probe(struct pci_dev *pdev, const struct pci_device_id *id) > > { > > struct device *dev = &pdev->dev; > > - int regloc; > > + struct cxl_mem *cxlm; > > + int rc, regloc, i; > > + u32 regloc_size; > > + > > + rc = pcim_enable_device(pdev); > > + if (rc) > > + return rc; > > > > regloc = cxl_mem_dvsec(pdev, PCI_DVSEC_ID_CXL_REGLOC_OFFSET); > > if (!regloc) { > > @@ -39,7 +509,44 @@ static int cxl_mem_probe(struct pci_dev *pdev, const struct pci_device_id *id) > > return -ENXIO; > > } > > > > - return 0; > > + /* Get the size of the Register Locator DVSEC */ > > + pci_read_config_dword(pdev, regloc + PCI_DVSEC_HEADER1, ®loc_size); > > + regloc_size = FIELD_GET(PCI_DVSEC_HEADER1_LENGTH_MASK, regloc_size); > > + > > + regloc += PCI_DVSEC_ID_CXL_REGLOC_BLOCK1_OFFSET; > > + > > + rc = -ENXIO; > > + for (i = regloc; i < regloc + regloc_size; i += 8) { > > + u32 reg_lo, reg_hi; > > + u8 reg_type; > > + > > + /* "register low and high" contain other bits */ > > + pci_read_config_dword(pdev, i, ®_lo); > > + pci_read_config_dword(pdev, i + 4, ®_hi); > > + > > + reg_type = FIELD_GET(CXL_REGLOC_RBI_MASK, reg_lo); > > + > > + if (reg_type == CXL_REGLOC_RBI_MEMDEV) { > > + rc = 0; > > + cxlm = cxl_mem_create(pdev, reg_lo, reg_hi); > > + if (!cxlm) > > + rc = -ENODEV; > > + break; > > + } > > + } > > + > > + if (rc) > > + return rc; > > + > > + rc = cxl_mem_setup_regs(cxlm); > > + if (rc) > > + return rc; > > + > > + rc = cxl_mem_setup_mailbox(cxlm); > > + if (rc) > > + return rc; > > + > > + return cxl_mem_identify(cxlm); > > } > > > > static const struct pci_device_id cxl_mem_pci_tbl[] = { > > diff --git a/drivers/cxl/pci.h b/drivers/cxl/pci.h > > index f135b9f7bb21..ffcbc13d7b5b 100644 > > --- a/drivers/cxl/pci.h > > +++ b/drivers/cxl/pci.h > > @@ -14,5 +14,18 @@ > > #define PCI_DVSEC_ID_CXL 0x0 > > > > #define PCI_DVSEC_ID_CXL_REGLOC_OFFSET 0x8 > > +#define PCI_DVSEC_ID_CXL_REGLOC_BLOCK1_OFFSET 0xC > > + > > +/* BAR Indicator Register (BIR) */ > > +#define CXL_REGLOC_BIR_MASK GENMASK(2, 0) > > + > > +/* Register Block Identifier (RBI) */ > > +#define CXL_REGLOC_RBI_MASK GENMASK(15, 8) > > +#define CXL_REGLOC_RBI_EMPTY 0 > > +#define CXL_REGLOC_RBI_COMPONENT 1 > > +#define CXL_REGLOC_RBI_VIRT 2 > > +#define CXL_REGLOC_RBI_MEMDEV 3 > > + > > +#define CXL_REGLOC_ADDR_MASK GENMASK(31, 16) > > > > #endif /* __CXL_PCI_H__ */ > > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > > index e709ae8235e7..6267ca9ae683 100644 > > --- a/include/uapi/linux/pci_regs.h > > +++ b/include/uapi/linux/pci_regs.h > > @@ -1080,6 +1080,7 @@ > > > > /* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */ > > #define PCI_DVSEC_HEADER1 0x4 /* Designated Vendor-Specific Header1 */ > > +#define PCI_DVSEC_HEADER1_LENGTH_MASK 0xFFF00000 > > #define PCI_DVSEC_HEADER2 0x8 /* Designated Vendor-Specific Header2 */ > > > > /* Data Link Feature */ >
On Tue, 9 Feb 2021 16:02:53 -0800 Ben Widawsky <ben.widawsky@intel.com> wrote: > Provide enough functionality to utilize the mailbox of a memory device. > The mailbox is used to interact with the firmware running on the memory > device. The flow is proven with one implemented command, "identify". > Because the class code has already told the driver this is a memory > device and the identify command is mandatory. > > CXL devices contain an array of capabilities that describe the > interactions software can have with the device or firmware running on > the device. A CXL compliant device must implement the device status and > the mailbox capability. Additionally, a CXL compliant memory device must > implement the memory device capability. Each of the capabilities can > [will] provide an offset within the MMIO region for interacting with the > CXL device. > > The capabilities tell the driver how to find and map the register space > for CXL Memory Devices. The registers are required to utilize the CXL > spec defined mailbox interface. The spec outlines two mailboxes, primary > and secondary. The secondary mailbox is earmarked for system firmware, > and not handled in this driver. > > Primary mailboxes are capable of generating an interrupt when submitting > a background command. That implementation is saved for a later time. > > Link: https://www.computeexpresslink.org/download-the-specification > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> > Reviewed-by: Dan Williams <dan.j.williams@intel.com> A few more comments inline (proper review whereas my other reply was a bug chase). Jonathan > --- > drivers/cxl/Kconfig | 14 + > drivers/cxl/cxl.h | 93 +++++++ > drivers/cxl/mem.c | 511 +++++++++++++++++++++++++++++++++- > drivers/cxl/pci.h | 13 + > include/uapi/linux/pci_regs.h | 1 + > 5 files changed, 630 insertions(+), 2 deletions(-) > create mode 100644 drivers/cxl/cxl.h > > diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig > index 9e80b311e928..c4ba3aa0a05d 100644 > --- a/drivers/cxl/Kconfig > +++ b/drivers/cxl/Kconfig > @@ -32,4 +32,18 @@ config CXL_MEM > Chapter 2.3 Type 3 CXL Device in the CXL 2.0 specification. > > If unsure say 'm'. > + > +config CXL_MEM_INSECURE_DEBUG > + bool "CXL.mem debugging" As mentioned below, this makes me a tiny bit uncomfortable. > + depends on CXL_MEM > + help > + Enable debug of all CXL command payloads. > + > + Some CXL devices and controllers support encryption and other > + security features. The payloads for the commands that enable > + those features may contain sensitive clear-text security > + material. Disable debug of those command payloads by default. > + If you are a kernel developer actively working on CXL > + security enabling say Y, otherwise say N. > + > endif > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h > new file mode 100644 > index 000000000000..745f5e0bfce3 > --- /dev/null > +++ b/drivers/cxl/cxl.h > @@ -0,0 +1,93 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* Copyright(c) 2020 Intel Corporation. */ > + > +#ifndef __CXL_H__ > +#define __CXL_H__ > + > +#include <linux/bitfield.h> > +#include <linux/bitops.h> > +#include <linux/io.h> > + > +/* CXL 2.0 8.2.8.1 Device Capabilities Array Register */ > +#define CXLDEV_CAP_ARRAY_OFFSET 0x0 > +#define CXLDEV_CAP_ARRAY_CAP_ID 0 > +#define CXLDEV_CAP_ARRAY_ID_MASK GENMASK(15, 0) > +#define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK(47, 32) > +/* CXL 2.0 8.2.8.2.1 CXL Device Capabilities */ > +#define CXLDEV_CAP_CAP_ID_DEVICE_STATUS 0x1 > +#define CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX 0x2 > +#define CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX 0x3 > +#define CXLDEV_CAP_CAP_ID_MEMDEV 0x4000 > + > +/* CXL 2.0 8.2.8.4 Mailbox Registers */ > +#define CXLDEV_MBOX_CAPS_OFFSET 0x00 > +#define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0) > +#define CXLDEV_MBOX_CTRL_OFFSET 0x04 > +#define CXLDEV_MBOX_CTRL_DOORBELL BIT(0) > +#define CXLDEV_MBOX_CMD_OFFSET 0x08 > +#define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK(15, 0) > +#define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK(36, 16) > +#define CXLDEV_MBOX_STATUS_OFFSET 0x10 > +#define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK(47, 32) > +#define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18 > +#define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20 > + > +/* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */ > +#define CXLMDEV_STATUS_OFFSET 0x0 > +#define CXLMDEV_DEV_FATAL BIT(0) > +#define CXLMDEV_FW_HALT BIT(1) > +#define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2) > +#define CXLMDEV_MS_NOT_READY 0 > +#define CXLMDEV_MS_READY 1 > +#define CXLMDEV_MS_ERROR 2 > +#define CXLMDEV_MS_DISABLED 3 > +#define CXLMDEV_READY(status) \ > + (FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \ > + CXLMDEV_MS_READY) > +#define CXLMDEV_MBOX_IF_READY BIT(4) > +#define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5) > +#define CXLMDEV_RESET_NEEDED_NOT 0 > +#define CXLMDEV_RESET_NEEDED_COLD 1 > +#define CXLMDEV_RESET_NEEDED_WARM 2 > +#define CXLMDEV_RESET_NEEDED_HOT 3 > +#define CXLMDEV_RESET_NEEDED_CXL 4 > +#define CXLMDEV_RESET_NEEDED(status) \ > + (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \ > + CXLMDEV_RESET_NEEDED_NOT) > + > +/** > + * struct cxl_mem - A CXL memory device > + * @pdev: The PCI device associated with this CXL device. > + * @regs: IO mappings to the device's MMIO > + * @status_regs: CXL 2.0 8.2.8.3 Device Status Registers > + * @mbox_regs: CXL 2.0 8.2.8.4 Mailbox Registers > + * @memdev_regs: CXL 2.0 8.2.8.5 Memory Device Registers > + * @payload_size: Size of space for payload > + * (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register) > + * @mbox_mutex: Mutex to synchronize mailbox access. > + * @firmware_version: Firmware version for the memory device. > + * @pmem: Persistent memory capacity information. > + * @ram: Volatile memory capacity information. > + */ > +struct cxl_mem { > + struct pci_dev *pdev; > + void __iomem *regs; > + > + void __iomem *status_regs; > + void __iomem *mbox_regs; > + void __iomem *memdev_regs; > + > + size_t payload_size; > + struct mutex mbox_mutex; /* Protects device mailbox and firmware */ > + char firmware_version[0x10]; > + > + struct { > + struct range range; > + } pmem; Christoph raised this in v1, and I agree with him that his would me more compact and readable as struct range pmem_range; struct range ram_range; The discussion seemed to get lost without getting resolved that I can see. > + > + struct { > + struct range range; > + } ram; > +}; > + > +#endif /* __CXL_H__ */ > diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c > index 99a6571508df..0a868a15badc 100644 > --- a/drivers/cxl/mem.c > +++ b/drivers/cxl/mem.c ... > +static void cxl_mem_mbox_timeout(struct cxl_mem *cxlm, > + struct mbox_cmd *mbox_cmd) > +{ > + struct device *dev = &cxlm->pdev->dev; > + > + dev_dbg(dev, "Mailbox command (opcode: %#x size: %zub) timed out\n", > + mbox_cmd->opcode, mbox_cmd->size_in); > + > + if (IS_ENABLED(CONFIG_CXL_MEM_INSECURE_DEBUG)) { Hmm. Whilst I can see the advantage of this for debug, I'm not sure we want it upstream even under a rather evil looking CONFIG variable. Is there a bigger lock we can use to avoid chance of accidental enablement? > + print_hex_dump_debug("Payload ", DUMP_PREFIX_OFFSET, 16, 1, > + mbox_cmd->payload_in, mbox_cmd->size_in, > + true); > + } > +} > + > +/** > + * cxl_mem_mbox_send_cmd() - Send a mailbox command to a memory device. > + * @cxlm: The CXL memory device to communicate with. > + * @mbox_cmd: Command to send to the memory device. > + * > + * Context: Any context. Expects mbox_lock to be held. > + * Return: -ETIMEDOUT if timeout occurred waiting for completion. 0 on success. > + * Caller should check the return code in @mbox_cmd to make sure it > + * succeeded. > + * > + * This is a generic form of the CXL mailbox send command, thus the only I/O > + * operations used are cxl_read_mbox_reg(). Memory devices, and perhaps other > + * types of CXL devices may have further information available upon error > + * conditions. > + * > + * The CXL spec allows for up to two mailboxes. The intention is for the primary > + * mailbox to be OS controlled and the secondary mailbox to be used by system > + * firmware. This allows the OS and firmware to communicate with the device and > + * not need to coordinate with each other. The driver only uses the primary > + * mailbox. > + */ > +static int cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, > + struct mbox_cmd *mbox_cmd) > +{ > + void __iomem *payload = cxlm->mbox_regs + CXLDEV_MBOX_PAYLOAD_OFFSET; > + u64 cmd_reg, status_reg; > + size_t out_len; > + int rc; > + > + lockdep_assert_held(&cxlm->mbox_mutex); > + > + /* > + * Here are the steps from 8.2.8.4 of the CXL 2.0 spec. > + * 1. Caller reads MB Control Register to verify doorbell is clear > + * 2. Caller writes Command Register > + * 3. Caller writes Command Payload Registers if input payload is non-empty > + * 4. Caller writes MB Control Register to set doorbell > + * 5. Caller either polls for doorbell to be clear or waits for interrupt if configured > + * 6. Caller reads MB Status Register to fetch Return code > + * 7. If command successful, Caller reads Command Register to get Payload Length > + * 8. If output payload is non-empty, host reads Command Payload Registers > + * > + * Hardware is free to do whatever it wants before the doorbell is rung, > + * and isn't allowed to change anything after it clears the doorbell. As > + * such, steps 2 and 3 can happen in any order, and steps 6, 7, 8 can > + * also happen in any order (though some orders might not make sense). > + */ > + > + /* #1 */ > + if (cxl_doorbell_busy(cxlm)) { > + dev_err_ratelimited(&cxlm->pdev->dev, > + "Mailbox re-busy after acquiring\n"); > + return -EBUSY; > + } > + > + cmd_reg = FIELD_PREP(CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK, > + mbox_cmd->opcode); > + if (mbox_cmd->size_in) { > + if (WARN_ON(!mbox_cmd->payload_in)) > + return -EINVAL; > + > + cmd_reg |= FIELD_PREP(CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK, > + mbox_cmd->size_in); > + memcpy_toio(payload, mbox_cmd->payload_in, mbox_cmd->size_in); > + } > + > + /* #2, #3 */ > + writeq(cmd_reg, cxlm->mbox_regs + CXLDEV_MBOX_CMD_OFFSET); > + > + /* #4 */ > + dev_dbg(&cxlm->pdev->dev, "Sending command\n"); > + writel(CXLDEV_MBOX_CTRL_DOORBELL, > + cxlm->mbox_regs + CXLDEV_MBOX_CTRL_OFFSET); > + > + /* #5 */ > + rc = cxl_mem_wait_for_doorbell(cxlm); > + if (rc == -ETIMEDOUT) { > + cxl_mem_mbox_timeout(cxlm, mbox_cmd); > + return rc; > + } > + > + /* #6 */ > + status_reg = readq(cxlm->mbox_regs + CXLDEV_MBOX_STATUS_OFFSET); > + mbox_cmd->return_code = > + FIELD_GET(CXLDEV_MBOX_STATUS_RET_CODE_MASK, status_reg); > + > + if (mbox_cmd->return_code != 0) { > + dev_dbg(&cxlm->pdev->dev, "Mailbox operation had an error\n"); > + return 0; See earlier diversion whilst I was chasing my bug (another branch of this thread) > + } > + > + /* #7 */ > + cmd_reg = readq(cxlm->mbox_regs + CXLDEV_MBOX_CMD_OFFSET); > + out_len = FIELD_GET(CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK, cmd_reg); > + > + /* #8 */ > + if (out_len && mbox_cmd->payload_out) > + memcpy_fromio(mbox_cmd->payload_out, payload, out_len); > + > + mbox_cmd->size_out = out_len; > + > + return 0; > +} > + ... > +static struct cxl_mem *cxl_mem_create(struct pci_dev *pdev, u32 reg_lo, > + u32 reg_hi) > +{ > + struct device *dev = &pdev->dev; > + struct cxl_mem *cxlm; > + void __iomem *regs; > + u64 offset; > + u8 bar; > + int rc; > + > + cxlm = devm_kzalloc(&pdev->dev, sizeof(*cxlm), GFP_KERNEL); > + if (!cxlm) { > + dev_err(dev, "No memory available\n"); > + return NULL; > + } > + > + offset = ((u64)reg_hi << 32) | FIELD_GET(CXL_REGLOC_ADDR_MASK, reg_lo); > + bar = FIELD_GET(CXL_REGLOC_BIR_MASK, reg_lo); > + > + /* Basic sanity check that BAR is big enough */ > + if (pci_resource_len(pdev, bar) < offset) { > + dev_err(dev, "BAR%d: %pr: too small (offset: %#llx)\n", bar, > + &pdev->resource[bar], (unsigned long long)offset); > + return NULL; > + } > + > + rc = pcim_iomap_regions(pdev, BIT(bar), pci_name(pdev)); > + if (rc != 0) { if (rc) > + dev_err(dev, "failed to map registers\n"); > + return NULL; > + } > + regs = pcim_iomap_table(pdev)[bar]; > + > + mutex_init(&cxlm->mbox_mutex); > + cxlm->pdev = pdev; > + cxlm->regs = regs + offset; > + > + dev_dbg(dev, "Mapped CXL Memory Device resource\n"); > + return cxlm; > +} > ... > static int cxl_mem_probe(struct pci_dev *pdev, const struct pci_device_id *id) > { > struct device *dev = &pdev->dev; > - int regloc; > + struct cxl_mem *cxlm; > + int rc, regloc, i; > + u32 regloc_size; > + > + rc = pcim_enable_device(pdev); > + if (rc) > + return rc; > > regloc = cxl_mem_dvsec(pdev, PCI_DVSEC_ID_CXL_REGLOC_OFFSET); > if (!regloc) { > @@ -39,7 +509,44 @@ static int cxl_mem_probe(struct pci_dev *pdev, const struct pci_device_id *id) > return -ENXIO; > } > > - return 0; > + /* Get the size of the Register Locator DVSEC */ > + pci_read_config_dword(pdev, regloc + PCI_DVSEC_HEADER1, ®loc_size); > + regloc_size = FIELD_GET(PCI_DVSEC_HEADER1_LENGTH_MASK, regloc_size); > + > + regloc += PCI_DVSEC_ID_CXL_REGLOC_BLOCK1_OFFSET; > + > + rc = -ENXIO; > + for (i = regloc; i < regloc + regloc_size; i += 8) { > + u32 reg_lo, reg_hi; > + u8 reg_type; > + > + /* "register low and high" contain other bits */ high doesn't contain any other bits so that's a tiny bit misleading. > + pci_read_config_dword(pdev, i, ®_lo); > + pci_read_config_dword(pdev, i + 4, ®_hi); > + > + reg_type = FIELD_GET(CXL_REGLOC_RBI_MASK, reg_lo); > + > + if (reg_type == CXL_REGLOC_RBI_MEMDEV) { > + rc = 0; I sort of assumed this unusual structure was to allow for some future change, but checked end result and it still looks like this. So, drop the rc assignment here and... > + cxlm = cxl_mem_create(pdev, reg_lo, reg_hi); > + if (!cxlm) > + rc = -ENODEV; return -ENODEV; > + break; > + } > + } > + > + if (rc) > + return rc; With above direct return, only get here if rc = -ENXIO. Could just as easily check if i >= regloc + regloc_size then it's obvious this is kind of canonical form of 'not found'. Alternative would be to treat the above as a 'find' loop then have the clxm = cxl_mem_create() outside of the loop. > + > + rc = cxl_mem_setup_regs(cxlm); > + if (rc) > + return rc; > + > + rc = cxl_mem_setup_mailbox(cxlm); > + if (rc) > + return rc; > + > + return cxl_mem_identify(cxlm); > } > > static const struct pci_device_id cxl_mem_pci_tbl[] = { > diff --git a/drivers/cxl/pci.h b/drivers/cxl/pci.h > index f135b9f7bb21..ffcbc13d7b5b 100644 > --- a/drivers/cxl/pci.h > +++ b/drivers/cxl/pci.h > @@ -14,5 +14,18 @@ > #define PCI_DVSEC_ID_CXL 0x0 > > #define PCI_DVSEC_ID_CXL_REGLOC_OFFSET 0x8 > +#define PCI_DVSEC_ID_CXL_REGLOC_BLOCK1_OFFSET 0xC > + > +/* BAR Indicator Register (BIR) */ > +#define CXL_REGLOC_BIR_MASK GENMASK(2, 0) > + > +/* Register Block Identifier (RBI) */ > +#define CXL_REGLOC_RBI_MASK GENMASK(15, 8) > +#define CXL_REGLOC_RBI_EMPTY 0 > +#define CXL_REGLOC_RBI_COMPONENT 1 > +#define CXL_REGLOC_RBI_VIRT 2 > +#define CXL_REGLOC_RBI_MEMDEV 3 > + > +#define CXL_REGLOC_ADDR_MASK GENMASK(31, 16) CXL_REGLOCL_ADDR_LOW_MASK perhaps for clarity? > > #endif /* __CXL_PCI_H__ */ > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > index e709ae8235e7..6267ca9ae683 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -1080,6 +1080,7 @@ > > /* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */ > #define PCI_DVSEC_HEADER1 0x4 /* Designated Vendor-Specific Header1 */ > +#define PCI_DVSEC_HEADER1_LENGTH_MASK 0xFFF00000 Seems sensible to add the revision mask as well. The vendor id currently read using a word read rather than dword, but perhaps neater to add that as well for completeness? Having said that, given Bjorn's comment on clashes and the fact he'd rather see this stuff defined in drivers and combined later (see review patch 1 and follow the link) perhaps this series should not touch this header at all. > #define PCI_DVSEC_HEADER2 0x8 /* Designated Vendor-Specific Header2 */ > > /* Data Link Feature */
On Tue, 9 Feb 2021 16:02:54 -0800 Ben Widawsky <ben.widawsky@intel.com> wrote: > From: Dan Williams <dan.j.williams@intel.com> > > Create the /sys/bus/cxl hierarchy to enumerate: > > * Memory Devices (per-endpoint control devices) > > * Memory Address Space Devices (platform address ranges with > interleaving, performance, and persistence attributes) > > * Memory Regions (active provisioned memory from an address space device > that is in use as System RAM or delegated to libnvdimm as Persistent > Memory regions). > > For now, only the per-endpoint control devices are registered on the > 'cxl' bus. However, going forward it will provide a mechanism to > coordinate cross-device interleave. > > Signed-off-by: Dan Williams <dan.j.williams@intel.com> > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> One stray header, and a request for a tiny bit of reordering to make it easier to chase through creation and destruction. Either way with the header move to earlier patch I'm fine with this one. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- > Documentation/ABI/testing/sysfs-bus-cxl | 26 ++ > .../driver-api/cxl/memory-devices.rst | 17 + > drivers/cxl/Makefile | 3 + > drivers/cxl/bus.c | 29 ++ > drivers/cxl/cxl.h | 4 + > drivers/cxl/mem.c | 301 +++++++++++++++++- > 6 files changed, 378 insertions(+), 2 deletions(-) > create mode 100644 Documentation/ABI/testing/sysfs-bus-cxl > create mode 100644 drivers/cxl/bus.c > > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h > index 745f5e0bfce3..b3c56fa6e126 100644 > --- a/drivers/cxl/cxl.h > +++ b/drivers/cxl/cxl.h > @@ -3,6 +3,7 @@ > > #ifndef __CXL_H__ > #define __CXL_H__ > +#include <linux/range.h> Why is this coming in now? Feels like it should have been in earlier patch that started using struct range > > #include <linux/bitfield.h> > #include <linux/bitops.h> > @@ -55,6 +56,7 @@ > (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \ > CXLMDEV_RESET_NEEDED_NOT) > > +struct cxl_memdev; > /** > * struct cxl_mem - A CXL memory device > * @pdev: The PCI device associated with this CXL device. > @@ -72,6 +74,7 @@ > struct cxl_mem { > struct pci_dev *pdev; > void __iomem *regs; > + struct cxl_memdev *cxlmd; > > void __iomem *status_regs; > void __iomem *mbox_regs; > @@ -90,4 +93,5 @@ struct cxl_mem { > } ram; > }; > > +extern struct bus_type cxl_bus_type; > #endif /* __CXL_H__ */ > diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c > index 0a868a15badc..8bbd2495e237 100644 > --- a/drivers/cxl/mem.c > +++ b/drivers/cxl/mem.c > @@ -1,11 +1,36 @@ > > + > +static void cxl_memdev_release(struct device *dev) > +{ > + struct cxl_memdev *cxlmd = to_cxl_memdev(dev); > + > + percpu_ref_exit(&cxlmd->ops_active); > + ida_free(&cxl_memdev_ida, cxlmd->id); > + kfree(cxlmd); > +} > + ... > +static int cxl_mem_add_memdev(struct cxl_mem *cxlm) > +{ > + struct pci_dev *pdev = cxlm->pdev; > + struct cxl_memdev *cxlmd; > + struct device *dev; > + struct cdev *cdev; > + int rc; > + > + cxlmd = kzalloc(sizeof(*cxlmd), GFP_KERNEL); > + if (!cxlmd) > + return -ENOMEM; > + init_completion(&cxlmd->ops_dead); > + > + /* > + * @cxlm is deallocated when the driver unbinds so operations > + * that are using it need to hold a live reference. > + */ > + cxlmd->cxlm = cxlm; > + rc = percpu_ref_init(&cxlmd->ops_active, cxlmdev_ops_active_release, 0, > + GFP_KERNEL); > + if (rc) > + goto err_ref; > + > + rc = ida_alloc_range(&cxl_memdev_ida, 0, CXL_MEM_MAX_DEVS, GFP_KERNEL); > + if (rc < 0) > + goto err_id; > + cxlmd->id = rc; > + > + dev = &cxlmd->dev; > + device_initialize(dev); > + dev->parent = &pdev->dev; > + dev->bus = &cxl_bus_type; > + dev->devt = MKDEV(cxl_mem_major, cxlmd->id); > + dev->type = &cxl_memdev_type; > + dev_set_name(dev, "mem%d", cxlmd->id); > + > + cdev = &cxlmd->cdev; > + cdev_init(cdev, &cxl_memdev_fops); > + > + rc = cdev_device_add(cdev, dev); > + if (rc) > + goto err_add; > + > + return devm_add_action_or_reset(dev->parent, cxlmdev_unregister, cxlmd); This had me scratching my head. The cxlmdev_unregister() if called normally or in the _or_reset() results in percpu_ref_kill(&cxlmd->ops_active); cdev_device_del(&cxlmd->cdev, dev); wait_for_completion(&cxlmd->ops_dead); cxlmd->cxlm = NULL; put_device(dev); /* If last ref this will result in */ percpu_ref_exit(&cxlmd->ops_active); ida_free(&cxl_memdev_ida, cxlmd->id); kfree(cxlmd); So it's doing all the correct things but not necessarily in the obvious order. For simplicity of review perhaps it's worth reordering probe a bit to get the ida immediately after the cxlmd alloc and for the cxlmdev_unregister() perhaps reorder the cdev_device_del() before the percpu_ref_kill(). Trivial obvious as the ordering has no affect but makes it easy for reviewers to tick off setup vs tear down parts. > + > +err_add: > + ida_free(&cxl_memdev_ida, cxlmd->id); > +err_id: > + /* > + * Theoretically userspace could have already entered the fops, > + * so flush ops_active. > + */ > + percpu_ref_kill(&cxlmd->ops_active); > + wait_for_completion(&cxlmd->ops_dead); > + percpu_ref_exit(&cxlmd->ops_active); > +err_ref: > + kfree(cxlmd); > + > + return rc; > +} > +
On Tue, 9 Feb 2021 16:02:55 -0800 Ben Widawsky <ben.widawsky@intel.com> wrote: > Add a straightforward IOCTL that provides a mechanism for userspace to > query the supported memory device commands. CXL commands as they appear > to userspace are described as part of the UAPI kerneldoc. The command > list returned via this IOCTL will contain the full set of commands that > the driver supports, however, some of those commands may not be > available for use by userspace. > > Memory device commands first appear in the CXL 2.0 specification. They > are submitted through a mailbox mechanism specified also originally > specified in the CXL 2.0 specification. > > The send command allows userspace to issue mailbox commands directly to > the hardware. The list of available commands to send are the output of > the query command. The driver verifies basic properties of the command > and possibly inspect the input (or output) payload to determine whether > or not the command is allowed (or might taint the kernel). > > Reported-by: kernel test robot <lkp@intel.com> # bug in earlier revision > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> > Reviewed-by: Dan Williams <dan.j.willams@intel.com> A bit of anti macro commentary below. Heavy use of them may make the code shorter, but I'd argue they make it harder to do review if you've not looked at a given bit of code for a while. Also there is a bit of documentation in here for flags that don't seem to exist (at this stage anyway) - may just be in the wrong patch. Jonathan > --- > .clang-format | 1 + > .../userspace-api/ioctl/ioctl-number.rst | 1 + > drivers/cxl/mem.c | 291 +++++++++++++++++- > include/uapi/linux/cxl_mem.h | 152 +++++++++ > 4 files changed, 443 insertions(+), 2 deletions(-) > create mode 100644 include/uapi/linux/cxl_mem.h > > diff --git a/.clang-format b/.clang-format > index 10dc5a9a61b3..3f11c8901b43 100644 > --- a/.clang-format > +++ b/.clang-format > @@ -109,6 +109,7 @@ ForEachMacros: > - 'css_for_each_child' > - 'css_for_each_descendant_post' > - 'css_for_each_descendant_pre' > + - 'cxl_for_each_cmd' > - 'device_for_each_child_node' > - 'dma_fence_chain_for_each' > - 'do_for_each_ftrace_op' > diff --git a/Documentation/userspace-api/ioctl/ioctl-number.rst b/Documentation/userspace-api/ioctl/ioctl-number.rst > index a4c75a28c839..6eb8e634664d 100644 > --- a/Documentation/userspace-api/ioctl/ioctl-number.rst > +++ b/Documentation/userspace-api/ioctl/ioctl-number.rst > @@ -352,6 +352,7 @@ Code Seq# Include File Comments > <mailto:michael.klein@puffin.lb.shuttle.de> > 0xCC 00-0F drivers/misc/ibmvmc.h pseries VMC driver > 0xCD 01 linux/reiserfs_fs.h > +0xCE 01-02 uapi/linux/cxl_mem.h Compute Express Link Memory Devices > 0xCF 02 fs/cifs/ioctl.c > 0xDB 00-0F drivers/char/mwave/mwavepub.h > 0xDD 00-3F ZFCP device driver see drivers/s390/scsi/ > diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c > index 8bbd2495e237..ce65630bb75e 100644 > --- a/drivers/cxl/mem.c > +++ b/drivers/cxl/mem.c > @@ -1,5 +1,6 @@ > // SPDX-License-Identifier: GPL-2.0-only > /* Copyright(c) 2020 Intel Corporation. All rights reserved. */ > +#include <uapi/linux/cxl_mem.h> > #include <linux/module.h> > #include <linux/mutex.h> > #include <linux/cdev.h> > @@ -39,6 +40,7 @@ > #define CXL_MAILBOX_TIMEOUT_MS (2 * HZ) > > enum opcode { > + CXL_MBOX_OP_INVALID = 0x0000, > CXL_MBOX_OP_IDENTIFY = 0x4000, > CXL_MBOX_OP_MAX = 0x10000 > }; > @@ -90,9 +92,57 @@ struct cxl_memdev { > static int cxl_mem_major; > static DEFINE_IDA(cxl_memdev_ida); > > +/** > + * struct cxl_mem_command - Driver representation of a memory device command > + * @info: Command information as it exists for the UAPI > + * @opcode: The actual bits used for the mailbox protocol > + * @flags: Set of flags reflecting the state of the command. > + * > + * * %CXL_CMD_FLAG_MANDATORY: Hardware must support this command. This flag is > + * only used internally by the driver for sanity checking. Doesn't seem to be defined yet. > + * > + * The cxl_mem_command is the driver's internal representation of commands that > + * are supported by the driver. Some of these commands may not be supported by > + * the hardware. The driver will use @info to validate the fields passed in by > + * the user then submit the @opcode to the hardware. > + * > + * See struct cxl_command_info. > + */ > +struct cxl_mem_command { > + struct cxl_command_info info; > + enum opcode opcode; > +}; > + > +#define CXL_CMD(_id, _flags, sin, sout) \ > + [CXL_MEM_COMMAND_ID_##_id] = { \ > + .info = { \ > + .id = CXL_MEM_COMMAND_ID_##_id, \ > + .flags = CXL_MEM_COMMAND_FLAG_##_flags, \ > + .size_in = sin, \ > + .size_out = sout, \ > + }, \ > + .opcode = CXL_MBOX_OP_##_id, \ > + } > + > +/* > + * This table defines the supported mailbox commands for the driver. This table > + * is made up of a UAPI structure. Non-negative values as parameters in the > + * table will be validated against the user's input. For example, if size_in is > + * 0, and the user passed in 1, it is an error. > + */ > +static struct cxl_mem_command mem_commands[] = { > + CXL_CMD(IDENTIFY, NONE, 0, 0x43), > +}; As below, I'm doubtful about the macro magic and would rather see the long hand version. It's a fwe more characters but I can immediately see if fields are in the right places etc and we can skip the 0 default values. static struct cxl_mem_command mem_commands[] = { [CXL_MEM_COMMAND_ID_IDENTIFY] = { .info = { .id = CXL_MEM_COMMAND_ID_IDENTIFY, .size_out = 0x43, }, .opcode = CXL_MBOX_OP_IDENTIFY, }, }; Still it's your driver and I guess I'll guess I can probably get my head around this macro.. > > diff --git a/include/uapi/linux/cxl_mem.h b/include/uapi/linux/cxl_mem.h > new file mode 100644 > index 000000000000..f1f7e9f32ea5 > --- /dev/null > +++ b/include/uapi/linux/cxl_mem.h > @@ -0,0 +1,152 @@ > +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ > +/* > + * CXL IOCTLs for Memory Devices > + */ > + > +#ifndef _UAPI_CXL_MEM_H_ > +#define _UAPI_CXL_MEM_H_ > + > +#include <linux/types.h> > + > +/** > + * DOC: UAPI > + * > + * Not all of all commands that the driver supports are always available for use > + * by userspace. Userspace must check the results from the QUERY command in > + * order to determine the live set of commands. > + */ > + > +#define CXL_MEM_QUERY_COMMANDS _IOR(0xCE, 1, struct cxl_mem_query_commands) > +#define CXL_MEM_SEND_COMMAND _IOWR(0xCE, 2, struct cxl_send_command) > + > +#define CXL_CMDS \ > + ___C(INVALID, "Invalid Command"), \ > + ___C(IDENTIFY, "Identify Command"), \ > + ___C(MAX, "Last command") > + > +#define ___C(a, b) CXL_MEM_COMMAND_ID_##a > +enum { CXL_CMDS }; > + > +#undef ___C > +#define ___C(a, b) { b } > +static const struct { > + const char *name; > +} cxl_command_names[] = { CXL_CMDS }; > +#undef ___C Unless there are going to be a lot of these, I'd just write them out long hand as much more readable than the macro magic. enum { CXL_MEM_COMMAND_ID_INVALID, CXL_MEM_COMMAND_ID_IDENTIFY, CXL_MEM_COMMAND_ID_MAX }; static const struct { const char *name; } cxl_command_names[] = { [CXL_MEM_COMMAND_ID_INVALID] = { "Invalid Command" }, [CXL_MEM_COMMAND_ID_IDENTIFY] = { "Identify Comamnd" }, /* I hope you never need the Last command to exist in here as that sounds like a bug */ }; That's assuming I actually figured the macro fun out correctly. To my mind it's worth doing this stuff for 'lots' no so much for 3. > + > +/** > + * struct cxl_command_info - Command information returned from a query. > + * @id: ID number for the command. > + * @flags: Flags that specify command behavior. > + * > + * * %CXL_MEM_COMMAND_FLAG_KERNEL: This command is reserved for exclusive > + * kernel use. > + * * %CXL_MEM_COMMAND_FLAG_MUTEX: This command may require coordination with > + * the kernel in order to complete successfully. Doesn't correspond to the flags defined below. If introduced in a later patch then bring the docs in with the first use. > + * > + * @size_in: Expected input size, or -1 if variable length. > + * @size_out: Expected output size, or -1 if variable length. > + * > + * Represents a single command that is supported by both the driver and the > + * hardware. This is returned as part of an array from the query ioctl. The > + * following would be a command named "foobar" that takes a variable length > + * input and returns 0 bytes of output. Why give it a name? It's just an id! > + * > + * - @id = 10 > + * - @flags = CXL_MEM_COMMAND_FLAG_MUTEX That flag doesn't seem to be defined below. > + * - @size_in = -1 > + * - @size_out = 0 > + * > + * See struct cxl_mem_query_commands. > + */ > +struct cxl_command_info { > + __u32 id; > + > + __u32 flags; > +#define CXL_MEM_COMMAND_FLAG_NONE 0 > +#define CXL_MEM_COMMAND_FLAG_KERNEL BIT(0) > +#define CXL_MEM_COMMAND_FLAG_MASK GENMASK(1, 0) > + > + __s32 size_in; > + __s32 size_out; > +}; > + > +/** > + * struct cxl_mem_query_commands - Query supported commands. > + * @n_commands: In/out parameter. When @n_commands is > 0, the driver will > + * return min(num_support_commands, n_commands). When @n_commands > + * is 0, driver will return the number of total supported commands. > + * @rsvd: Reserved for future use. > + * @commands: Output array of supported commands. This array must be allocated > + * by userspace to be at least min(num_support_commands, @n_commands) > + * > + * Allow userspace to query the available commands supported by both the driver, > + * and the hardware. Commands that aren't supported by either the driver, or the > + * hardware are not returned in the query. > + * > + * Examples: > + * > + * - { .n_commands = 0 } // Get number of supported commands > + * - { .n_commands = 15, .commands = buf } // Return first 15 (or less) > + * supported commands > + * > + * See struct cxl_command_info. > + */ > +struct cxl_mem_query_commands { > + /* > + * Input: Number of commands to return (space allocated by user) > + * Output: Number of commands supported by the driver/hardware > + * > + * If n_commands is 0, kernel will only return number of commands and > + * not try to populate commands[], thus allowing userspace to know how > + * much space to allocate > + */ > + __u32 n_commands; > + __u32 rsvd; > + > + struct cxl_command_info __user commands[]; /* out: supported commands */ > +}; > + > +/** > + * struct cxl_send_command - Send a command to a memory device. > + * @id: The command to send to the memory device. This must be one of the > + * commands returned by the query command. > + * @flags: Flags for the command (input). > + * @rsvd: Must be zero. > + * @retval: Return value from the memory device (output). > + * @in.size: Size of the payload to provide to the device (input). > + * @in.rsvd: Must be zero. > + * @in.payload: Pointer to memory for payload input (little endian order). Silly point, but perhaps distinguish it's the payload that is in little endian order not the pointer. (I obviously haven't had enough coffee today and missread it) > + * @out.size: Size of the payload received from the device (input/output). This > + * field is filled in by userspace to let the driver know how much > + * space was allocated for output. It is populated by the driver to > + * let userspace know how large the output payload actually was. > + * @out.rsvd: Must be zero. > + * @out.payload: Pointer to memory for payload output (little endian order). > + * > + * Mechanism for userspace to send a command to the hardware for processing. The > + * driver will do basic validation on the command sizes. In some cases even the > + * payload may be introspected. Userspace is required to allocate large > + * enough buffers for size_out which can be variable length in certain > + * situations. > + */ > +struct cxl_send_command { > + __u32 id; > + __u32 flags; > + __u32 rsvd; > + __u32 retval; > + > + struct { > + __s32 size; > + __u32 rsvd; > + __u64 payload; > + } in; > + > + struct { > + __s32 size; > + __u32 rsvd; > + __u64 payload; > + } out; > +}; > + > +#endif
On Wed, Feb 10, 2021 at 10:53 AM Ben Widawsky <ben.widawsky@intel.com> wrote: [..] > > Christoph raised this in v1, and I agree with him that his would me more compact > > and readable as > > > > struct range pmem_range; > > struct range ram_range; > > > > The discussion seemed to get lost without getting resolved that I can see. > > > > I had been waiting for Dan to chime in, since he authored it. I'll change it and > he can yell if he cares. No concerns from me. > > > > + > > > + struct { > > > + struct range range; > > > + } ram; > > > > > +}; > > > + > > > +#endif /* __CXL_H__ */ > > > diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c > > > index 99a6571508df..0a868a15badc 100644 > > > --- a/drivers/cxl/mem.c > > > +++ b/drivers/cxl/mem.c > > > > > > ... > > > > > +static void cxl_mem_mbox_timeout(struct cxl_mem *cxlm, > > > + struct mbox_cmd *mbox_cmd) > > > +{ > > > + struct device *dev = &cxlm->pdev->dev; > > > + > > > + dev_dbg(dev, "Mailbox command (opcode: %#x size: %zub) timed out\n", > > > + mbox_cmd->opcode, mbox_cmd->size_in); > > > + > > > + if (IS_ENABLED(CONFIG_CXL_MEM_INSECURE_DEBUG)) { > > > > Hmm. Whilst I can see the advantage of this for debug, I'm not sure we want > > it upstream even under a rather evil looking CONFIG variable. > > > > Is there a bigger lock we can use to avoid chance of accidental enablement? > > Any suggestions? I'm told this functionality was extremely valuable for NVDIMM, > though I haven't personally experienced it. Yeah, there was no problem with the identical mechanism in LIBNVDIMM land. However, I notice that the useful feature for LIBNVDIMM is the option to dump all payloads. This one only fires on timeouts which is less useful. So I'd say fix it to dump all payloads on the argument that the safety mechanism was proven with the LIBNVDIMM precedent, or delete it altogether to maintain v5.12 momentum. Payload dumping can be added later. [..] > > > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > > > index e709ae8235e7..6267ca9ae683 100644 > > > --- a/include/uapi/linux/pci_regs.h > > > +++ b/include/uapi/linux/pci_regs.h > > > @@ -1080,6 +1080,7 @@ > > > > > > /* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */ > > > #define PCI_DVSEC_HEADER1 0x4 /* Designated Vendor-Specific Header1 */ > > > +#define PCI_DVSEC_HEADER1_LENGTH_MASK 0xFFF00000 > > > > Seems sensible to add the revision mask as well. > > The vendor id currently read using a word read rather than dword, but perhaps > > neater to add that as well for completeness? > > > > Having said that, given Bjorn's comment on clashes and the fact he'd rather see > > this stuff defined in drivers and combined later (see review patch 1 and follow > > the link) perhaps this series should not touch this header at all. > > I'm fine to move it back. Yeah, we're playing tennis now between Bjorn's and Christoph's comments, but I like Bjorn's suggestion of "deduplicate post merge" given the bloom of DVSEC infrastructure landing at the same time.
On Wed, Feb 10, 2021 at 10:47 AM Jonathan Cameron <Jonathan.Cameron@huawei.com> wrote: [..] > > +#define CXL_CMDS \ > > + ___C(INVALID, "Invalid Command"), \ > > + ___C(IDENTIFY, "Identify Command"), \ > > + ___C(MAX, "Last command") > > + > > +#define ___C(a, b) CXL_MEM_COMMAND_ID_##a > > +enum { CXL_CMDS }; > > + > > +#undef ___C > > +#define ___C(a, b) { b } > > +static const struct { > > + const char *name; > > +} cxl_command_names[] = { CXL_CMDS }; > > +#undef ___C > > Unless there are going to be a lot of these, I'd just write them out long hand > as much more readable than the macro magic. This macro magic isn't new to Linux it was introduced with ftrace: See "cpp tricks and treats": https://lwn.net/Articles/383362/ > > enum { > CXL_MEM_COMMAND_ID_INVALID, > CXL_MEM_COMMAND_ID_IDENTIFY, > CXL_MEM_COMMAND_ID_MAX > }; > > static const struct { > const char *name; > } cxl_command_names[] = { > [CXL_MEM_COMMAND_ID_INVALID] = { "Invalid Command" }, > [CXL_MEM_COMMAND_ID_IDENTIFY] = { "Identify Comamnd" }, > /* I hope you never need the Last command to exist in here as that sounds like a bug */ > }; > > That's assuming I actually figured the macro fun out correctly. > To my mind it's worth doing this stuff for 'lots' no so much for 3. The list will continue to expand, and it eliminates the "did you remember to update cxl_command_names" review burden permanently.
On Wed, 10 Feb 2021 10:16:05 -0800 Ben Widawsky <ben.widawsky@intel.com> wrote: > On 21-02-10 08:55:57, Ben Widawsky wrote: > > On 21-02-10 15:07:59, Jonathan Cameron wrote: > > > On Wed, 10 Feb 2021 13:32:52 +0000 > > > Jonathan Cameron <Jonathan.Cameron@Huawei.com> wrote: > > > > > > > On Tue, 9 Feb 2021 16:02:53 -0800 > > > > Ben Widawsky <ben.widawsky@intel.com> wrote: > > > > > > > > > Provide enough functionality to utilize the mailbox of a memory device. > > > > > The mailbox is used to interact with the firmware running on the memory > > > > > device. The flow is proven with one implemented command, "identify". > > > > > Because the class code has already told the driver this is a memory > > > > > device and the identify command is mandatory. > > > > > > > > > > CXL devices contain an array of capabilities that describe the > > > > > interactions software can have with the device or firmware running on > > > > > the device. A CXL compliant device must implement the device status and > > > > > the mailbox capability. Additionally, a CXL compliant memory device must > > > > > implement the memory device capability. Each of the capabilities can > > > > > [will] provide an offset within the MMIO region for interacting with the > > > > > CXL device. > > > > > > > > > > The capabilities tell the driver how to find and map the register space > > > > > for CXL Memory Devices. The registers are required to utilize the CXL > > > > > spec defined mailbox interface. The spec outlines two mailboxes, primary > > > > > and secondary. The secondary mailbox is earmarked for system firmware, > > > > > and not handled in this driver. > > > > > > > > > > Primary mailboxes are capable of generating an interrupt when submitting > > > > > a background command. That implementation is saved for a later time. > > > > > > > > > > Link: https://www.computeexpresslink.org/download-the-specification > > > > > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> > > > > > Reviewed-by: Dan Williams <dan.j.williams@intel.com> > > > > > > > > Hi Ben, > > > > > > > > > > > > > +/** > > > > > + * cxl_mem_mbox_send_cmd() - Send a mailbox command to a memory device. > > > > > + * @cxlm: The CXL memory device to communicate with. > > > > > + * @mbox_cmd: Command to send to the memory device. > > > > > + * > > > > > + * Context: Any context. Expects mbox_lock to be held. > > > > > + * Return: -ETIMEDOUT if timeout occurred waiting for completion. 0 on success. > > > > > + * Caller should check the return code in @mbox_cmd to make sure it > > > > > + * succeeded. > > > > > > > > cxl_xfer_log() doesn't check mbox_cmd->return_code and for my test it currently > > > > enters an infinite loop as a result. > > > > I meant to fix that. > > > > > > > > > > I haven't checked other paths, but to my mind it is not a good idea to require > > > > two levels of error checking - the example here proves how easy it is to forget > > > > one. > > > > Demonstrably, you're correct. I think it would be good to have a kernel only > > mbox command that does the error checking though. Let me type something up and > > see how it looks. > > Hi Jonathan. What do you think of this? The bit I'm on the fence about is if I > should validate output size too. I like the simplicity as it is, but it requires > every caller to possibly check output size, which is kind of the same problem > you're originally pointing out. The simplicity is good and this is pretty much what I expected you would end up with (always reassuring) For the output, perhaps just add another parameter to the wrapper for minimum output length expected? Now you mention the length question. It does rather feel like there should also be some protection on memcpy_fromio() copying too much data if the hardware happens to return an unexpectedly long length. Should never happen, but the hardening is worth adding anyway given it's easy to do. Jonathan > > diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c > index 55c5f5a6023f..ad7b2077ab28 100644 > --- a/drivers/cxl/mem.c > +++ b/drivers/cxl/mem.c > @@ -284,7 +284,7 @@ static void cxl_mem_mbox_timeout(struct cxl_mem *cxlm, > } > > /** > - * cxl_mem_mbox_send_cmd() - Send a mailbox command to a memory device. > + * __cxl_mem_mbox_send_cmd() - Execute a mailbox command > * @cxlm: The CXL memory device to communicate with. > * @mbox_cmd: Command to send to the memory device. > * > @@ -296,7 +296,8 @@ static void cxl_mem_mbox_timeout(struct cxl_mem *cxlm, > * This is a generic form of the CXL mailbox send command, thus the only I/O > * operations used are cxl_read_mbox_reg(). Memory devices, and perhaps other > * types of CXL devices may have further information available upon error > - * conditions. > + * conditions. Driver facilities wishing to send mailbox commands should use the > + * wrapper command. > * > * The CXL spec allows for up to two mailboxes. The intention is for the primary > * mailbox to be OS controlled and the secondary mailbox to be used by system > @@ -304,8 +305,8 @@ static void cxl_mem_mbox_timeout(struct cxl_mem *cxlm, > * not need to coordinate with each other. The driver only uses the primary > * mailbox. > */ > -static int cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, > - struct mbox_cmd *mbox_cmd) > +static int __cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, > + struct mbox_cmd *mbox_cmd) > { > void __iomem *payload = cxlm->mbox_regs + CXLDEV_MBOX_PAYLOAD_OFFSET; > u64 cmd_reg, status_reg; > @@ -469,6 +470,54 @@ static void cxl_mem_mbox_put(struct cxl_mem *cxlm) > mutex_unlock(&cxlm->mbox_mutex); > } > > +/** > + * cxl_mem_mbox_send_cmd() - Send a mailbox command to a memory device. > + * @cxlm: The CXL memory device to communicate with. > + * @opcode: Opcode for the mailbox command. > + * @in: The input payload for the mailbox command. > + * @in_size: The length of the input payload > + * @out: Caller allocated buffer for the output. > + * > + * Context: Any context. Will acquire and release mbox_mutex. > + * Return: > + * * %>=0 - Number of bytes returned in @out. > + * * %-EBUSY - Couldn't acquire exclusive mailbox access. > + * * %-EFAULT - Hardware error occurred. > + * * %-ENXIO - Command completed, but device reported an error. > + * > + * Mailbox commands may execute successfully yet the device itself reported an > + * error. While this distinction can be useful for commands from userspace, the > + * kernel will often only care when both are successful. > + * > + * See __cxl_mem_mbox_send_cmd() > + */ > +static int cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, u16 opcode, u8 *in, > + size_t in_size, u8 *out) > +{ > + struct mbox_cmd mbox_cmd = { > + .opcode = opcode, > + .payload_in = in, > + .size_in = in_size, > + .payload_out = out, > + }; > + int rc; > + > + rc = cxl_mem_mbox_get(cxlm); > + if (rc) > + return rc; > + > + rc = __cxl_mem_mbox_send_cmd(cxlm, &mbox_cmd); > + cxl_mem_mbox_put(cxlm); > + if (rc) > + return rc; > + > + /* TODO: Map return code to proper kernel style errno */ > + if (mbox_cmd.return_code != CXL_MBOX_SUCCESS) > + return -ENXIO; > + > + return mbox_cmd.size_out; > +} > + > /** > * handle_mailbox_cmd_from_user() - Dispatch a mailbox command. > * @cxlmd: The CXL memory device to communicate with. > @@ -1380,33 +1429,18 @@ static int cxl_mem_identify(struct cxl_mem *cxlm) > u8 poison_caps; > u8 qos_telemetry_caps; > } __packed id; > - struct mbox_cmd mbox_cmd = { > - .opcode = CXL_MBOX_OP_IDENTIFY, > - .payload_out = &id, > - .size_in = 0, > - }; > int rc; > > - /* Retrieve initial device memory map */ > - rc = cxl_mem_mbox_get(cxlm); > - if (rc) > - return rc; > - > - rc = cxl_mem_mbox_send_cmd(cxlm, &mbox_cmd); > - cxl_mem_mbox_put(cxlm); > - if (rc) > + rc = cxl_mem_mbox_send_cmd(cxlm, CXL_MBOX_OP_IDENTIFY, NULL, 0, > + (u8 *)&id); > + if (rc < 0) > return rc; > > - /* TODO: Handle retry or reset responses from firmware. */ > - if (mbox_cmd.return_code != CXL_MBOX_SUCCESS) { > - dev_err(&cxlm->pdev->dev, "Mailbox command failed (%d)\n", > - mbox_cmd.return_code); > + if (rc < sizeof(id)) { > + dev_err(&cxlm->pdev->dev, "Short identify data\n", > return -ENXIO; > } > > - if (mbox_cmd.size_out != sizeof(id)) > - return -ENXIO; > - > /* > * TODO: enumerate DPA map, as 'ram' and 'pmem' do not alias. > * For now, only the capacity is exported in sysfs > > > [snip] >
On Wed, 10 Feb 2021 11:54:29 -0800 Dan Williams <dan.j.williams@intel.com> wrote: > > > ... > > > > > > > +static void cxl_mem_mbox_timeout(struct cxl_mem *cxlm, > > > > + struct mbox_cmd *mbox_cmd) > > > > +{ > > > > + struct device *dev = &cxlm->pdev->dev; > > > > + > > > > + dev_dbg(dev, "Mailbox command (opcode: %#x size: %zub) timed out\n", > > > > + mbox_cmd->opcode, mbox_cmd->size_in); > > > > + > > > > + if (IS_ENABLED(CONFIG_CXL_MEM_INSECURE_DEBUG)) { > > > > > > Hmm. Whilst I can see the advantage of this for debug, I'm not sure we want > > > it upstream even under a rather evil looking CONFIG variable. > > > > > > Is there a bigger lock we can use to avoid chance of accidental enablement? > > > > Any suggestions? I'm told this functionality was extremely valuable for NVDIMM, > > though I haven't personally experienced it. > > Yeah, there was no problem with the identical mechanism in LIBNVDIMM > land. However, I notice that the useful feature for LIBNVDIMM is the > option to dump all payloads. This one only fires on timeouts which is > less useful. So I'd say fix it to dump all payloads on the argument > that the safety mechanism was proven with the LIBNVDIMM precedent, or > delete it altogether to maintain v5.12 momentum. Payload dumping can > be added later. I think I'd drop it for now - feels like a topic that needs more discussion. Also, dumping this data to the kernel log isn't exactly elegant - particularly if we dump a lot more of it. Perhaps tracepoints? > > [..] > > > > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > > > > index e709ae8235e7..6267ca9ae683 100644 > > > > --- a/include/uapi/linux/pci_regs.h > > > > +++ b/include/uapi/linux/pci_regs.h > > > > @@ -1080,6 +1080,7 @@ > > > > > > > > /* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */ > > > > #define PCI_DVSEC_HEADER1 0x4 /* Designated Vendor-Specific Header1 */ > > > > +#define PCI_DVSEC_HEADER1_LENGTH_MASK 0xFFF00000 > > > > > > Seems sensible to add the revision mask as well. > > > The vendor id currently read using a word read rather than dword, but perhaps > > > neater to add that as well for completeness? > > > > > > Having said that, given Bjorn's comment on clashes and the fact he'd rather see > > > this stuff defined in drivers and combined later (see review patch 1 and follow > > > the link) perhaps this series should not touch this header at all. > > > > I'm fine to move it back. > > Yeah, we're playing tennis now between Bjorn's and Christoph's > comments, but I like Bjorn's suggestion of "deduplicate post merge" > given the bloom of DVSEC infrastructure landing at the same time. I guess it may depend on timing of this. Personally I think 5.12 may be too aggressive. As long as Bjorn can take a DVSEC deduplication as an immutable branch then perhaps during 5.13 this tree can sit on top of that. Jonathan
On Wed, 10 Feb 2021 20:40:52 -0800 Dan Williams <dan.j.williams@intel.com> wrote: > On Wed, Feb 10, 2021 at 10:47 AM Jonathan Cameron > <Jonathan.Cameron@huawei.com> wrote: > [..] > > > +#define CXL_CMDS \ > > > + ___C(INVALID, "Invalid Command"), \ > > > + ___C(IDENTIFY, "Identify Command"), \ > > > + ___C(MAX, "Last command") > > > + > > > +#define ___C(a, b) CXL_MEM_COMMAND_ID_##a > > > +enum { CXL_CMDS }; > > > + > > > +#undef ___C > > > +#define ___C(a, b) { b } > > > +static const struct { > > > + const char *name; > > > +} cxl_command_names[] = { CXL_CMDS }; > > > +#undef ___C > > > > Unless there are going to be a lot of these, I'd just write them out long hand > > as much more readable than the macro magic. > > This macro magic isn't new to Linux it was introduced with ftrace: > > See "cpp tricks and treats": https://lwn.net/Articles/383362/ Yeah. I've dealt with that one a few times. It's very cleaver and compact but a PITA to debug build errors related to it. > > > > > enum { > > CXL_MEM_COMMAND_ID_INVALID, > > CXL_MEM_COMMAND_ID_IDENTIFY, > > CXL_MEM_COMMAND_ID_MAX > > }; > > > > static const struct { > > const char *name; > > } cxl_command_names[] = { > > [CXL_MEM_COMMAND_ID_INVALID] = { "Invalid Command" }, > > [CXL_MEM_COMMAND_ID_IDENTIFY] = { "Identify Comamnd" }, > > /* I hope you never need the Last command to exist in here as that sounds like a bug */ > > }; > > > > That's assuming I actually figured the macro fun out correctly. > > To my mind it's worth doing this stuff for 'lots' no so much for 3. > > The list will continue to expand, and it eliminates the "did you > remember to update cxl_command_names" review burden permanently. How about a compromise. Add a comment giving how the first entry expands to avoid people (me at least :) having to think their way through it every time? Jonathan
On Wed, 10 Feb 2021 18:17:25 +0000 Jonathan Cameron <Jonathan.Cameron@Huawei.com> wrote: > On Tue, 9 Feb 2021 16:02:54 -0800 > Ben Widawsky <ben.widawsky@intel.com> wrote: > > > From: Dan Williams <dan.j.williams@intel.com> > > > > Create the /sys/bus/cxl hierarchy to enumerate: > > > > * Memory Devices (per-endpoint control devices) > > > > * Memory Address Space Devices (platform address ranges with > > interleaving, performance, and persistence attributes) > > > > * Memory Regions (active provisioned memory from an address space device > > that is in use as System RAM or delegated to libnvdimm as Persistent > > Memory regions). > > > > For now, only the per-endpoint control devices are registered on the > > 'cxl' bus. However, going forward it will provide a mechanism to > > coordinate cross-device interleave. > > > > Signed-off-by: Dan Williams <dan.j.williams@intel.com> > > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> > > One stray header, and a request for a tiny bit of reordering to > make it easier to chase through creation and destruction. > > Either way with the header move to earlier patch I'm fine with this one. > > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Actually thinking more on this, what is the justification for the complexity + overhead of a percpu_refcount vs a refcount I don't think this is a high enough performance path for it to matter. Perhaps I'm missing a usecase where it does? Jonathan > > > --- > > Documentation/ABI/testing/sysfs-bus-cxl | 26 ++ > > .../driver-api/cxl/memory-devices.rst | 17 + > > drivers/cxl/Makefile | 3 + > > drivers/cxl/bus.c | 29 ++ > > drivers/cxl/cxl.h | 4 + > > drivers/cxl/mem.c | 301 +++++++++++++++++- > > 6 files changed, 378 insertions(+), 2 deletions(-) > > create mode 100644 Documentation/ABI/testing/sysfs-bus-cxl > > create mode 100644 drivers/cxl/bus.c > > > > > > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h > > index 745f5e0bfce3..b3c56fa6e126 100644 > > --- a/drivers/cxl/cxl.h > > +++ b/drivers/cxl/cxl.h > > @@ -3,6 +3,7 @@ > > > > #ifndef __CXL_H__ > > #define __CXL_H__ > > +#include <linux/range.h> > > Why is this coming in now? Feels like it should have been in earlier > patch that started using struct range > > > > > #include <linux/bitfield.h> > > #include <linux/bitops.h> > > @@ -55,6 +56,7 @@ > > (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \ > > CXLMDEV_RESET_NEEDED_NOT) > > > > +struct cxl_memdev; > > /** > > * struct cxl_mem - A CXL memory device > > * @pdev: The PCI device associated with this CXL device. > > @@ -72,6 +74,7 @@ > > struct cxl_mem { > > struct pci_dev *pdev; > > void __iomem *regs; > > + struct cxl_memdev *cxlmd; > > > > void __iomem *status_regs; > > void __iomem *mbox_regs; > > @@ -90,4 +93,5 @@ struct cxl_mem { > > } ram; > > }; > > > > +extern struct bus_type cxl_bus_type; > > #endif /* __CXL_H__ */ > > diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c > > index 0a868a15badc..8bbd2495e237 100644 > > --- a/drivers/cxl/mem.c > > +++ b/drivers/cxl/mem.c > > @@ -1,11 +1,36 @@ > > > > > + > > +static void cxl_memdev_release(struct device *dev) > > +{ > > + struct cxl_memdev *cxlmd = to_cxl_memdev(dev); > > + > > + percpu_ref_exit(&cxlmd->ops_active); > > + ida_free(&cxl_memdev_ida, cxlmd->id); > > + kfree(cxlmd); > > +} > > + > ... > > > +static int cxl_mem_add_memdev(struct cxl_mem *cxlm) > > +{ > > + struct pci_dev *pdev = cxlm->pdev; > > + struct cxl_memdev *cxlmd; > > + struct device *dev; > > + struct cdev *cdev; > > + int rc; > > + > > + cxlmd = kzalloc(sizeof(*cxlmd), GFP_KERNEL); > > + if (!cxlmd) > > + return -ENOMEM; > > + init_completion(&cxlmd->ops_dead); > > + > > + /* > > + * @cxlm is deallocated when the driver unbinds so operations > > + * that are using it need to hold a live reference. > > + */ > > + cxlmd->cxlm = cxlm; > > + rc = percpu_ref_init(&cxlmd->ops_active, cxlmdev_ops_active_release, 0, > > + GFP_KERNEL); > > + if (rc) > > + goto err_ref; > > + > > + rc = ida_alloc_range(&cxl_memdev_ida, 0, CXL_MEM_MAX_DEVS, GFP_KERNEL); > > + if (rc < 0) > > + goto err_id; > > + cxlmd->id = rc; > > + > > + dev = &cxlmd->dev; > > + device_initialize(dev); > > + dev->parent = &pdev->dev; > > + dev->bus = &cxl_bus_type; > > + dev->devt = MKDEV(cxl_mem_major, cxlmd->id); > > + dev->type = &cxl_memdev_type; > > + dev_set_name(dev, "mem%d", cxlmd->id); > > + > > + cdev = &cxlmd->cdev; > > + cdev_init(cdev, &cxl_memdev_fops); > > + > > + rc = cdev_device_add(cdev, dev); > > + if (rc) > > + goto err_add; > > + > > + return devm_add_action_or_reset(dev->parent, cxlmdev_unregister, cxlmd); > > This had me scratching my head. The cxlmdev_unregister() if called normally > or in the _or_reset() results in > > percpu_ref_kill(&cxlmd->ops_active); > cdev_device_del(&cxlmd->cdev, dev); > wait_for_completion(&cxlmd->ops_dead); > cxlmd->cxlm = NULL; > put_device(dev); > /* If last ref this will result in */ > percpu_ref_exit(&cxlmd->ops_active); > ida_free(&cxl_memdev_ida, cxlmd->id); > kfree(cxlmd); > > So it's doing all the correct things but not necessarily > in the obvious order. > > For simplicity of review perhaps it's worth reordering probe a bit > to get the ida immediately after the cxlmd alloc and > for the cxlmdev_unregister() perhaps reorder the cdev_device_del() > before the percpu_ref_kill(). > > Trivial obvious as the ordering has no affect but makes it > easy for reviewers to tick off setup vs tear down parts. > > > + > > +err_add: > > + ida_free(&cxl_memdev_ida, cxlmd->id); > > +err_id: > > + /* > > + * Theoretically userspace could have already entered the fops, > > + * so flush ops_active. > > + */ > > + percpu_ref_kill(&cxlmd->ops_active); > > + wait_for_completion(&cxlmd->ops_dead); > > + percpu_ref_exit(&cxlmd->ops_active); > > +err_ref: > > + kfree(cxlmd); > > + > > + return rc; > > +} > > + > > > >
On Tue, 9 Feb 2021 16:02:57 -0800 Ben Widawsky <ben.widawsky@intel.com> wrote: > CXL devices identified by the memory-device class code must implement > the Device Command Interface (described in 8.2.9 of the CXL 2.0 spec). > While the driver already maintains a list of commands it supports, there > is still a need to be able to distinguish between commands that the > driver knows about from commands that are optionally supported by the > hardware. > > The Command Effects Log (CEL) is specified in the CXL 2.0 specification. > The CEL is one of two types of logs, the other being vendor specific. I'd say "vendor specific debug" just so that no one thinks it has anything to do with the rest of this description (which mentioned vendor specific commands). > They are distinguished in hardware/spec via UUID. The CEL is useful for > 2 things: > 1. Determine which optional commands are supported by the CXL device. > 2. Enumerate any vendor specific commands > > The CEL is used by the driver to determine which commands are available > in the hardware and therefore which commands userspace is allowed to > execute. The set of enabled commands might be a subset of commands which > are advertised in UAPI via CXL_MEM_SEND_COMMAND IOCTL. > > The implementation leaves the statically defined table of commands and > supplements it with a bitmap to determine commands that are enabled. > This organization was chosen for the following reasons: > - Smaller memory footprint. Doesn't need a table per device. > - Reduce memory allocation complexity. > - Fixed command IDs to opcode mapping for all devices makes development > and debugging easier. > - Certain helpers are easily achievable, like cxl_for_each_cmd(). > > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> > Reviewed-by: Dan Williams <dan.j.williams@intel.com> > --- > drivers/cxl/cxl.h | 2 + > drivers/cxl/mem.c | 216 +++++++++++++++++++++++++++++++++++ > include/uapi/linux/cxl_mem.h | 1 + > 3 files changed, 219 insertions(+) > > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h > index b3c56fa6e126..9a5e595abfa4 100644 > --- a/drivers/cxl/cxl.h > +++ b/drivers/cxl/cxl.h > @@ -68,6 +68,7 @@ struct cxl_memdev; > * (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register) > * @mbox_mutex: Mutex to synchronize mailbox access. > * @firmware_version: Firmware version for the memory device. > + * @enabled_commands: Hardware commands found enabled in CEL. > * @pmem: Persistent memory capacity information. > * @ram: Volatile memory capacity information. > */ > @@ -83,6 +84,7 @@ struct cxl_mem { > size_t payload_size; > struct mutex mbox_mutex; /* Protects device mailbox and firmware */ > char firmware_version[0x10]; > + unsigned long *enabled_cmds; > > struct { > struct range range; > diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c > index 6d766a994dce..e9aa6ca18d99 100644 > --- a/drivers/cxl/mem.c > +++ b/drivers/cxl/mem.c > @@ -45,6 +45,8 @@ enum opcode { > CXL_MBOX_OP_INVALID = 0x0000, > CXL_MBOX_OP_RAW = CXL_MBOX_OP_INVALID, > CXL_MBOX_OP_ACTIVATE_FW = 0x0202, > + CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400, > + CXL_MBOX_OP_GET_LOG = 0x0401, > CXL_MBOX_OP_IDENTIFY = 0x4000, > CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101, > CXL_MBOX_OP_SET_LSA = 0x4103, > @@ -103,6 +105,19 @@ static DEFINE_IDA(cxl_memdev_ida); > static struct dentry *cxl_debugfs; > static bool raw_allow_all; > > +enum { > + CEL_UUID, > + VENDOR_DEBUG_UUID Who wants to take a bet this will get extended at somepoint in the future? Add a trailing comma to make that less noisy. They would never have used a UUID if this wasn't expected to expand. CXL spec calls out that "The following Log Identifier UUIDs are defined in _this_ specification" rather implying other specs may well define more. Fun for the future! > +}; > + > +/* See CXL 2.0 Table 170. Get Log Input Payload */ > +static const uuid_t log_uuid[] = { > + [CEL_UUID] = UUID_INIT(0xda9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 0x96, > + 0xb1, 0x62, 0x3b, 0x3f, 0x17), > + [VENDOR_DEBUG_UUID] = UUID_INIT(0xe1819d9, 0x11a9, 0x400c, 0x81, 0x1f, > + 0xd6, 0x07, 0x19, 0x40, 0x3d, 0x86) likewise on trailing comma > +}; > + > /** > * struct cxl_mem_command - Driver representation of a memory device command > * @info: Command information as it exists for the UAPI > @@ -111,6 +126,8 @@ static bool raw_allow_all; > * > * * %CXL_CMD_FLAG_MANDATORY: Hardware must support this command. This flag is > * only used internally by the driver for sanity checking. > + * * %CXL_CMD_INTERNAL_FLAG_PSEUDO: This is a pseudo command which doesn't have > + * a direct mapping to hardware. They are implicitly always enabled. Stale comment? > * > * The cxl_mem_command is the driver's internal representation of commands that > * are supported by the driver. Some of these commands may not be supported by > @@ -146,6 +163,7 @@ static struct cxl_mem_command mem_commands[] = { > #ifdef CONFIG_CXL_MEM_RAW_COMMANDS > CXL_CMD(RAW, NONE, ~0, ~0), > #endif > + CXL_CMD(GET_SUPPORTED_LOGS, NONE, 0, ~0), > }; > > /* > @@ -627,6 +645,10 @@ static int cxl_validate_cmd_from_user(struct cxl_mem *cxlm, > c = &mem_commands[send_cmd->id]; > info = &c->info; > > + /* Check that the command is enabled for hardware */ > + if (!test_bit(info->id, cxlm->enabled_cmds)) > + return -ENOTTY; > + > if (info->flags & CXL_MEM_COMMAND_FLAG_KERNEL) > return -EPERM; > > @@ -869,6 +891,14 @@ static struct cxl_mem *cxl_mem_create(struct pci_dev *pdev, u32 reg_lo, > mutex_init(&cxlm->mbox_mutex); > cxlm->pdev = pdev; > cxlm->regs = regs + offset; > + cxlm->enabled_cmds = > + devm_kmalloc_array(dev, BITS_TO_LONGS(cxl_cmd_count), > + sizeof(unsigned long), > + GFP_KERNEL | __GFP_ZERO); Hmm. There doesn't seem to be a devm_bitmap_zalloc Embarrassingly one of the google hits on the topic is me suggesting this in a previous review (that I'd long since forgotten) Perhaps one for a refactoring patch after this lands. > + if (!cxlm->enabled_cmds) { > + dev_err(dev, "No memory available for bitmap\n"); > + return NULL; > + } > > dev_dbg(dev, "Mapped CXL Memory Device resource\n"); > return cxlm; > @@ -1088,6 +1118,188 @@ static int cxl_mem_add_memdev(struct cxl_mem *cxlm) > return rc; > } > > +struct cxl_mbox_get_log { > + uuid_t uuid; > + __le32 offset; > + __le32 length; > +} __packed; > + > +static int cxl_xfer_log(struct cxl_mem *cxlm, uuid_t *uuid, u32 size, u8 *out) > +{ > + u32 remaining = size; > + u32 offset = 0; > + > + while (remaining) { > + u32 xfer_size = min_t(u32, remaining, cxlm->payload_size); > + struct cxl_mbox_get_log log = { > + .uuid = *uuid, > + .offset = cpu_to_le32(offset), > + .length = cpu_to_le32(xfer_size) > + }; > + struct mbox_cmd mbox_cmd = { > + .opcode = CXL_MBOX_OP_GET_LOG, > + .payload_in = &log, > + .payload_out = out, > + .size_in = sizeof(log), > + }; > + int rc; > + > + rc = cxl_mem_mbox_send_cmd(cxlm, &mbox_cmd); > + if (rc) > + return rc; > + > + WARN_ON(mbox_cmd.size_out != xfer_size); Just for completeness (as already addressed in one of Ben's replies to earlier patch) this is missing handling for the return code. > + > + out += xfer_size; > + remaining -= xfer_size; > + offset += xfer_size; > + } > + > + return 0; > +} > + > +static inline struct cxl_mem_command *cxl_mem_find_command(u16 opcode) > +{ > + struct cxl_mem_command *c; > + > + cxl_for_each_cmd(c) > + if (c->opcode == opcode) > + return c; > + > + return NULL; > +} > + > +static void cxl_enable_cmd(struct cxl_mem *cxlm, > + const struct cxl_mem_command *cmd) > +{ > + if (test_and_set_bit(cmd->info.id, cxlm->enabled_cmds)) > + dev_WARN_ONCE(&cxlm->pdev->dev, true, "cmd enabled twice\n"); > +} > + > +/** > + * cxl_walk_cel() - Walk through the Command Effects Log. > + * @cxlm: Device. > + * @size: Length of the Command Effects Log. > + * @cel: CEL > + * > + * Iterate over each entry in the CEL and determine if the driver supports the > + * command. If so, the command is enabled for the device and can be used later. > + */ > +static void cxl_walk_cel(struct cxl_mem *cxlm, size_t size, u8 *cel) > +{ > + struct cel_entry { > + __le16 opcode; > + __le16 effect; > + } *cel_entry; Driver is currently marking a bunch of other structures packed that don't need it. Perhaps do this one as well for consistency? > + const int cel_entries = size / sizeof(*cel_entry); > + int i; > + > + cel_entry = (struct cel_entry *)cel; > + > + for (i = 0; i < cel_entries; i++) { > + const struct cel_entry *ce = &cel_entry[i]; Given ce is only ever used to get the ce->opcode maybe better using that as the local variable? u16 opcode = le16_to_cpu(cel_entry[i].opcode) Obviously that might change depending on later patches though. > + const struct cxl_mem_command *cmd = > + cxl_mem_find_command(le16_to_cpu(ce->opcode)); > + > + if (!cmd) { > + dev_dbg(&cxlm->pdev->dev, "Unsupported opcode 0x%04x", Unsupported by who? (driver rather than hardware) > + le16_to_cpu(ce->opcode)); > + continue; > + } > + > + cxl_enable_cmd(cxlm, cmd); > + } > +} > + > +/** > + * cxl_mem_enumerate_cmds() - Enumerate commands for a device. > + * @cxlm: The device. > + * > + * Returns 0 if enumerate completed successfully. > + * > + * CXL devices have optional support for certain commands. This function will > + * determine the set of supported commands for the hardware and update the > + * enabled_cmds bitmap in the @cxlm. > + */ > +static int cxl_mem_enumerate_cmds(struct cxl_mem *cxlm) > +{ > + struct device *dev = &cxlm->pdev->dev; > + struct cxl_mbox_get_supported_logs { > + __le16 entries; > + u8 rsvd[6]; > + struct gsl_entry { > + uuid_t uuid; > + __le32 size; > + } __packed entry[2]; > + } __packed gsl; > + struct mbox_cmd mbox_cmd = { > + .opcode = CXL_MBOX_OP_GET_SUPPORTED_LOGS, > + .payload_out = &gsl, > + .size_in = 0, > + }; > + int i, rc; > + > + rc = cxl_mem_mbox_get(cxlm); > + if (rc) > + return rc; > + > + rc = cxl_mem_mbox_send_cmd(cxlm, &mbox_cmd); > + if (rc) > + goto out; > + > + if (mbox_cmd.return_code != CXL_MBOX_SUCCESS) { > + rc = -ENXIO; > + goto out; > + } > + > + if (mbox_cmd.size_out > sizeof(gsl)) { > + dev_warn(dev, "%zu excess logs\n", > + (mbox_cmd.size_out - sizeof(gsl)) / > + sizeof(struct gsl_entry)); This could well happen given spec seems to allow for other entries defined by other specs. Note that it's this path that I mentioned earlier as requiring we sanity check the output size available before calling mempcy_fromio into it with the hardware supported size. > + } > + > + for (i = 0; i < le16_to_cpu(gsl.entries); i++) { > + u32 size = le32_to_cpu(gsl.entry[i].size); > + uuid_t uuid = gsl.entry[i].uuid; > + u8 *log; > + > + dev_dbg(dev, "Found LOG type %pU of size %d", &uuid, size); > + > + if (!uuid_equal(&uuid, &log_uuid[CEL_UUID])) > + continue; > + > + /* > + * It's a hardware bug if the log size is less than the input > + * payload size because there are many mandatory commands. > + */ > + if (sizeof(struct cxl_mbox_get_log) > size) { If you are going to talk about less than in the comment, I'd flip the condition around so it lines up. Trivial obviously but nice to tidy up. > + dev_err(dev, "CEL log size reported was too small (%d)", > + size); > + rc = -ENOMEM; > + goto out; > + } > + > + log = kvmalloc(size, GFP_KERNEL); > + if (!log) { > + rc = -ENOMEM; > + goto out; > + } > + > + rc = cxl_xfer_log(cxlm, &uuid, size, log); > + if (rc) { > + kvfree(log); > + goto out; > + } > + > + cxl_walk_cel(cxlm, size, log); > + kvfree(log); > + } > + > +out: > + cxl_mem_mbox_put(cxlm); > + return rc; > +} > + > /** > * cxl_mem_identify() - Send the IDENTIFY command to the device. > * @cxlm: The device to identify. > @@ -1211,6 +1423,10 @@ static int cxl_mem_probe(struct pci_dev *pdev, const struct pci_device_id *id) > if (rc) > return rc; > > + rc = cxl_mem_enumerate_cmds(cxlm); > + if (rc) > + return rc; > + > rc = cxl_mem_identify(cxlm); > if (rc) > return rc; > diff --git a/include/uapi/linux/cxl_mem.h b/include/uapi/linux/cxl_mem.h > index 72d1eb601a5d..c5e75b9dad9d 100644 > --- a/include/uapi/linux/cxl_mem.h > +++ b/include/uapi/linux/cxl_mem.h > @@ -23,6 +23,7 @@ > ___C(INVALID, "Invalid Command"), \ > ___C(IDENTIFY, "Identify Command"), \ > ___C(RAW, "Raw device command"), \ > + ___C(GET_SUPPORTED_LOGS, "Get Supported Logs"), \ > ___C(MAX, "Last command") > > #define ___C(a, b) CXL_MEM_COMMAND_ID_##a
On 21-02-11 09:55:48, Jonathan Cameron wrote: > On Wed, 10 Feb 2021 10:16:05 -0800 > Ben Widawsky <ben.widawsky@intel.com> wrote: > > > On 21-02-10 08:55:57, Ben Widawsky wrote: > > > On 21-02-10 15:07:59, Jonathan Cameron wrote: > > > > On Wed, 10 Feb 2021 13:32:52 +0000 > > > > Jonathan Cameron <Jonathan.Cameron@Huawei.com> wrote: > > > > > > > > > On Tue, 9 Feb 2021 16:02:53 -0800 > > > > > Ben Widawsky <ben.widawsky@intel.com> wrote: > > > > > > > > > > > Provide enough functionality to utilize the mailbox of a memory device. > > > > > > The mailbox is used to interact with the firmware running on the memory > > > > > > device. The flow is proven with one implemented command, "identify". > > > > > > Because the class code has already told the driver this is a memory > > > > > > device and the identify command is mandatory. > > > > > > > > > > > > CXL devices contain an array of capabilities that describe the > > > > > > interactions software can have with the device or firmware running on > > > > > > the device. A CXL compliant device must implement the device status and > > > > > > the mailbox capability. Additionally, a CXL compliant memory device must > > > > > > implement the memory device capability. Each of the capabilities can > > > > > > [will] provide an offset within the MMIO region for interacting with the > > > > > > CXL device. > > > > > > > > > > > > The capabilities tell the driver how to find and map the register space > > > > > > for CXL Memory Devices. The registers are required to utilize the CXL > > > > > > spec defined mailbox interface. The spec outlines two mailboxes, primary > > > > > > and secondary. The secondary mailbox is earmarked for system firmware, > > > > > > and not handled in this driver. > > > > > > > > > > > > Primary mailboxes are capable of generating an interrupt when submitting > > > > > > a background command. That implementation is saved for a later time. > > > > > > > > > > > > Link: https://www.computeexpresslink.org/download-the-specification > > > > > > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> > > > > > > Reviewed-by: Dan Williams <dan.j.williams@intel.com> > > > > > > > > > > Hi Ben, > > > > > > > > > > > > > > > > +/** > > > > > > + * cxl_mem_mbox_send_cmd() - Send a mailbox command to a memory device. > > > > > > + * @cxlm: The CXL memory device to communicate with. > > > > > > + * @mbox_cmd: Command to send to the memory device. > > > > > > + * > > > > > > + * Context: Any context. Expects mbox_lock to be held. > > > > > > + * Return: -ETIMEDOUT if timeout occurred waiting for completion. 0 on success. > > > > > > + * Caller should check the return code in @mbox_cmd to make sure it > > > > > > + * succeeded. > > > > > > > > > > cxl_xfer_log() doesn't check mbox_cmd->return_code and for my test it currently > > > > > enters an infinite loop as a result. > > > > > > I meant to fix that. > > > > > > > > > > > > > I haven't checked other paths, but to my mind it is not a good idea to require > > > > > two levels of error checking - the example here proves how easy it is to forget > > > > > one. > > > > > > Demonstrably, you're correct. I think it would be good to have a kernel only > > > mbox command that does the error checking though. Let me type something up and > > > see how it looks. > > > > Hi Jonathan. What do you think of this? The bit I'm on the fence about is if I > > should validate output size too. I like the simplicity as it is, but it requires > > every caller to possibly check output size, which is kind of the same problem > > you're originally pointing out. > > The simplicity is good and this is pretty much what I expected you would end up with > (always reassuring) > > For the output, perhaps just add another parameter to the wrapper for minimum > output length expected? > > Now you mention the length question. It does rather feel like there should also > be some protection on memcpy_fromio() copying too much data if the hardware > happens to return an unexpectedly long length. Should never happen, but > the hardening is worth adding anyway given it's easy to do. > > Jonathan Some background because I forget what I've said previously... It's unfortunate that the spec maxes at 1M mailbox size but has enough bits in the length field to support 2M-1. I've made some requests to have this fixed, so maybe 3.0 won't be awkward like this. I think it makes sense to do as you suggested. One question though, do you have an opinion on we return to the caller as the output payload size, do we cap it at 1M also, or are we honest? - if (out_len && mbox_cmd->payload_out) - memcpy_fromio(mbox_cmd->payload_out, payload, out_len); + if (out_len && mbox_cmd->payload_out) { + size_t n = min_t(size_t, cxlm->payload_size, out_len); + memcpy_fromio(mbox_cmd->payload_out, payload, n); + } So... mbox_cmd->size_out = out_len; mbox_cmd->size_out = n; > > > > > > diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c > > index 55c5f5a6023f..ad7b2077ab28 100644 > > --- a/drivers/cxl/mem.c > > +++ b/drivers/cxl/mem.c > > @@ -284,7 +284,7 @@ static void cxl_mem_mbox_timeout(struct cxl_mem *cxlm, > > } > > > > /** > > - * cxl_mem_mbox_send_cmd() - Send a mailbox command to a memory device. > > + * __cxl_mem_mbox_send_cmd() - Execute a mailbox command > > * @cxlm: The CXL memory device to communicate with. > > * @mbox_cmd: Command to send to the memory device. > > * > > @@ -296,7 +296,8 @@ static void cxl_mem_mbox_timeout(struct cxl_mem *cxlm, > > * This is a generic form of the CXL mailbox send command, thus the only I/O > > * operations used are cxl_read_mbox_reg(). Memory devices, and perhaps other > > * types of CXL devices may have further information available upon error > > - * conditions. > > + * conditions. Driver facilities wishing to send mailbox commands should use the > > + * wrapper command. > > * > > * The CXL spec allows for up to two mailboxes. The intention is for the primary > > * mailbox to be OS controlled and the secondary mailbox to be used by system > > @@ -304,8 +305,8 @@ static void cxl_mem_mbox_timeout(struct cxl_mem *cxlm, > > * not need to coordinate with each other. The driver only uses the primary > > * mailbox. > > */ > > -static int cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, > > - struct mbox_cmd *mbox_cmd) > > +static int __cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, > > + struct mbox_cmd *mbox_cmd) > > { > > void __iomem *payload = cxlm->mbox_regs + CXLDEV_MBOX_PAYLOAD_OFFSET; > > u64 cmd_reg, status_reg; > > @@ -469,6 +470,54 @@ static void cxl_mem_mbox_put(struct cxl_mem *cxlm) > > mutex_unlock(&cxlm->mbox_mutex); > > } > > > > +/** > > + * cxl_mem_mbox_send_cmd() - Send a mailbox command to a memory device. > > + * @cxlm: The CXL memory device to communicate with. > > + * @opcode: Opcode for the mailbox command. > > + * @in: The input payload for the mailbox command. > > + * @in_size: The length of the input payload > > + * @out: Caller allocated buffer for the output. > > + * > > + * Context: Any context. Will acquire and release mbox_mutex. > > + * Return: > > + * * %>=0 - Number of bytes returned in @out. > > + * * %-EBUSY - Couldn't acquire exclusive mailbox access. > > + * * %-EFAULT - Hardware error occurred. > > + * * %-ENXIO - Command completed, but device reported an error. > > + * > > + * Mailbox commands may execute successfully yet the device itself reported an > > + * error. While this distinction can be useful for commands from userspace, the > > + * kernel will often only care when both are successful. > > + * > > + * See __cxl_mem_mbox_send_cmd() > > + */ > > +static int cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, u16 opcode, u8 *in, > > + size_t in_size, u8 *out) > > +{ > > + struct mbox_cmd mbox_cmd = { > > + .opcode = opcode, > > + .payload_in = in, > > + .size_in = in_size, > > + .payload_out = out, > > + }; > > + int rc; > > + > > + rc = cxl_mem_mbox_get(cxlm); > > + if (rc) > > + return rc; > > + > > + rc = __cxl_mem_mbox_send_cmd(cxlm, &mbox_cmd); > > + cxl_mem_mbox_put(cxlm); > > + if (rc) > > + return rc; > > + > > + /* TODO: Map return code to proper kernel style errno */ > > + if (mbox_cmd.return_code != CXL_MBOX_SUCCESS) > > + return -ENXIO; > > + > > + return mbox_cmd.size_out; > > +} > > + > > /** > > * handle_mailbox_cmd_from_user() - Dispatch a mailbox command. > > * @cxlmd: The CXL memory device to communicate with. > > @@ -1380,33 +1429,18 @@ static int cxl_mem_identify(struct cxl_mem *cxlm) > > u8 poison_caps; > > u8 qos_telemetry_caps; > > } __packed id; > > - struct mbox_cmd mbox_cmd = { > > - .opcode = CXL_MBOX_OP_IDENTIFY, > > - .payload_out = &id, > > - .size_in = 0, > > - }; > > int rc; > > > > - /* Retrieve initial device memory map */ > > - rc = cxl_mem_mbox_get(cxlm); > > - if (rc) > > - return rc; > > - > > - rc = cxl_mem_mbox_send_cmd(cxlm, &mbox_cmd); > > - cxl_mem_mbox_put(cxlm); > > - if (rc) > > + rc = cxl_mem_mbox_send_cmd(cxlm, CXL_MBOX_OP_IDENTIFY, NULL, 0, > > + (u8 *)&id); > > + if (rc < 0) > > return rc; > > > > - /* TODO: Handle retry or reset responses from firmware. */ > > - if (mbox_cmd.return_code != CXL_MBOX_SUCCESS) { > > - dev_err(&cxlm->pdev->dev, "Mailbox command failed (%d)\n", > > - mbox_cmd.return_code); > > + if (rc < sizeof(id)) { > > + dev_err(&cxlm->pdev->dev, "Short identify data\n", > > return -ENXIO; > > } > > > > - if (mbox_cmd.size_out != sizeof(id)) > > - return -ENXIO; > > - > > /* > > * TODO: enumerate DPA map, as 'ram' and 'pmem' do not alias. > > * For now, only the capacity is exported in sysfs > > > > > > [snip] > > >
On 21-02-11 10:01:52, Jonathan Cameron wrote: > On Wed, 10 Feb 2021 11:54:29 -0800 > Dan Williams <dan.j.williams@intel.com> wrote: > > > > > ... > > > > > > > > > +static void cxl_mem_mbox_timeout(struct cxl_mem *cxlm, > > > > > + struct mbox_cmd *mbox_cmd) > > > > > +{ > > > > > + struct device *dev = &cxlm->pdev->dev; > > > > > + > > > > > + dev_dbg(dev, "Mailbox command (opcode: %#x size: %zub) timed out\n", > > > > > + mbox_cmd->opcode, mbox_cmd->size_in); > > > > > + > > > > > + if (IS_ENABLED(CONFIG_CXL_MEM_INSECURE_DEBUG)) { > > > > > > > > Hmm. Whilst I can see the advantage of this for debug, I'm not sure we want > > > > it upstream even under a rather evil looking CONFIG variable. > > > > > > > > Is there a bigger lock we can use to avoid chance of accidental enablement? > > > > > > Any suggestions? I'm told this functionality was extremely valuable for NVDIMM, > > > though I haven't personally experienced it. > > > > Yeah, there was no problem with the identical mechanism in LIBNVDIMM > > land. However, I notice that the useful feature for LIBNVDIMM is the > > option to dump all payloads. This one only fires on timeouts which is > > less useful. So I'd say fix it to dump all payloads on the argument > > that the safety mechanism was proven with the LIBNVDIMM precedent, or > > delete it altogether to maintain v5.12 momentum. Payload dumping can > > be added later. > > I think I'd drop it for now - feels like a topic that needs more discussion. > > Also, dumping this data to the kernel log isn't exactly elegant - particularly > if we dump a lot more of it. Perhaps tracepoints? > I'll drop it. It's also a small enough bit to add on for developers. When I post v3, I will add that bit on top as an RFC. My personal preference FWIW is to use debugfs to store the payload of the last executed command. We went with this because of the mechanism's provenance (libnvdimm) > > > > [..] > > > > > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > > > > > index e709ae8235e7..6267ca9ae683 100644 > > > > > --- a/include/uapi/linux/pci_regs.h > > > > > +++ b/include/uapi/linux/pci_regs.h > > > > > @@ -1080,6 +1080,7 @@ > > > > > > > > > > /* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */ > > > > > #define PCI_DVSEC_HEADER1 0x4 /* Designated Vendor-Specific Header1 */ > > > > > +#define PCI_DVSEC_HEADER1_LENGTH_MASK 0xFFF00000 > > > > > > > > Seems sensible to add the revision mask as well. > > > > The vendor id currently read using a word read rather than dword, but perhaps > > > > neater to add that as well for completeness? > > > > > > > > Having said that, given Bjorn's comment on clashes and the fact he'd rather see > > > > this stuff defined in drivers and combined later (see review patch 1 and follow > > > > the link) perhaps this series should not touch this header at all. > > > > > > I'm fine to move it back. > > > > Yeah, we're playing tennis now between Bjorn's and Christoph's > > comments, but I like Bjorn's suggestion of "deduplicate post merge" > > given the bloom of DVSEC infrastructure landing at the same time. > I guess it may depend on timing of this. Personally I think 5.12 may be too aggressive. > > As long as Bjorn can take a DVSEC deduplication as an immutable branch then perhaps > during 5.13 this tree can sit on top of that. > > Jonathan > >
On 21-02-11 10:06:46, Jonathan Cameron wrote: > On Wed, 10 Feb 2021 20:40:52 -0800 > Dan Williams <dan.j.williams@intel.com> wrote: > > > On Wed, Feb 10, 2021 at 10:47 AM Jonathan Cameron > > <Jonathan.Cameron@huawei.com> wrote: > > [..] > > > > +#define CXL_CMDS \ > > > > + ___C(INVALID, "Invalid Command"), \ > > > > + ___C(IDENTIFY, "Identify Command"), \ > > > > + ___C(MAX, "Last command") > > > > + > > > > +#define ___C(a, b) CXL_MEM_COMMAND_ID_##a > > > > +enum { CXL_CMDS }; > > > > + > > > > +#undef ___C > > > > +#define ___C(a, b) { b } > > > > +static const struct { > > > > + const char *name; > > > > +} cxl_command_names[] = { CXL_CMDS }; > > > > +#undef ___C > > > > > > Unless there are going to be a lot of these, I'd just write them out long hand > > > as much more readable than the macro magic. > > > > This macro magic isn't new to Linux it was introduced with ftrace: > > > > See "cpp tricks and treats": https://lwn.net/Articles/383362/ > > Yeah. I've dealt with that one a few times. It's very cleaver and compact > but a PITA to debug build errors related to it. > > > > > > > > > enum { > > > CXL_MEM_COMMAND_ID_INVALID, > > > CXL_MEM_COMMAND_ID_IDENTIFY, > > > CXL_MEM_COMMAND_ID_MAX > > > }; > > > > > > static const struct { > > > const char *name; > > > } cxl_command_names[] = { > > > [CXL_MEM_COMMAND_ID_INVALID] = { "Invalid Command" }, > > > [CXL_MEM_COMMAND_ID_IDENTIFY] = { "Identify Comamnd" }, > > > /* I hope you never need the Last command to exist in here as that sounds like a bug */ > > > }; > > > > > > That's assuming I actually figured the macro fun out correctly. > > > To my mind it's worth doing this stuff for 'lots' no so much for 3. > > > > The list will continue to expand, and it eliminates the "did you > > remember to update cxl_command_names" review burden permanently. > > How about a compromise. Add a comment giving how the first entry expands to > avoid people (me at least :) having to think their way through it every time? > > Jonathan > A minor tweak while here... diff --git a/include/uapi/linux/cxl_mem.h b/include/uapi/linux/cxl_mem.h index 655fbfde97fd..dac0adb879ec 100644 --- a/include/uapi/linux/cxl_mem.h +++ b/include/uapi/linux/cxl_mem.h @@ -22,7 +22,7 @@ #define CXL_CMDS \ ___C(INVALID, "Invalid Command"), \ ___C(IDENTIFY, "Identify Command"), \ - ___C(MAX, "Last command") + ___C(MAX, "invalid / last command") #define ___C(a, b) CXL_MEM_COMMAND_ID_##a enum { CXL_CMDS }; @@ -32,6 +32,17 @@ enum { CXL_CMDS }; static const struct { const char *name; } cxl_command_names[] = { CXL_CMDS }; + +/* + * Here's how this actually breaks out: + * cxl_command_names[] = { + * [CXL_MEM_COMMAND_ID_INVALID] = { "Invalid Command" }, + * [CXL_MEM_COMMAND_ID_IDENTIFY] = { "Identify Comamnd" }, + * ... + * [CXL_MEM_COMMAND_ID_MAX] = { "invalid / last command" }, + * }; + */ +
On 21-02-11 12:02:15, Jonathan Cameron wrote: > On Tue, 9 Feb 2021 16:02:57 -0800 > Ben Widawsky <ben.widawsky@intel.com> wrote: > > > CXL devices identified by the memory-device class code must implement > > the Device Command Interface (described in 8.2.9 of the CXL 2.0 spec). > > While the driver already maintains a list of commands it supports, there > > is still a need to be able to distinguish between commands that the > > driver knows about from commands that are optionally supported by the > > hardware. > > > > The Command Effects Log (CEL) is specified in the CXL 2.0 specification. > > The CEL is one of two types of logs, the other being vendor specific. > > I'd say "vendor specific debug" just so that no one thinks it has anything > to do with the rest of this description (which mentioned vendor specific > commands). > > > They are distinguished in hardware/spec via UUID. The CEL is useful for > > 2 things: > > 1. Determine which optional commands are supported by the CXL device. > > 2. Enumerate any vendor specific commands > > > > The CEL is used by the driver to determine which commands are available > > in the hardware and therefore which commands userspace is allowed to > > execute. The set of enabled commands might be a subset of commands which > > are advertised in UAPI via CXL_MEM_SEND_COMMAND IOCTL. > > > > The implementation leaves the statically defined table of commands and > > supplements it with a bitmap to determine commands that are enabled. > > This organization was chosen for the following reasons: > > - Smaller memory footprint. Doesn't need a table per device. > > - Reduce memory allocation complexity. > > - Fixed command IDs to opcode mapping for all devices makes development > > and debugging easier. > > - Certain helpers are easily achievable, like cxl_for_each_cmd(). > > > > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> > > Reviewed-by: Dan Williams <dan.j.williams@intel.com> > > --- > > drivers/cxl/cxl.h | 2 + > > drivers/cxl/mem.c | 216 +++++++++++++++++++++++++++++++++++ > > include/uapi/linux/cxl_mem.h | 1 + > > 3 files changed, 219 insertions(+) > > > > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h > > index b3c56fa6e126..9a5e595abfa4 100644 > > --- a/drivers/cxl/cxl.h > > +++ b/drivers/cxl/cxl.h > > @@ -68,6 +68,7 @@ struct cxl_memdev; > > * (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register) > > * @mbox_mutex: Mutex to synchronize mailbox access. > > * @firmware_version: Firmware version for the memory device. > > + * @enabled_commands: Hardware commands found enabled in CEL. > > * @pmem: Persistent memory capacity information. > > * @ram: Volatile memory capacity information. > > */ > > @@ -83,6 +84,7 @@ struct cxl_mem { > > size_t payload_size; > > struct mutex mbox_mutex; /* Protects device mailbox and firmware */ > > char firmware_version[0x10]; > > + unsigned long *enabled_cmds; > > > > struct { > > struct range range; > > diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c > > index 6d766a994dce..e9aa6ca18d99 100644 > > --- a/drivers/cxl/mem.c > > +++ b/drivers/cxl/mem.c > > @@ -45,6 +45,8 @@ enum opcode { > > CXL_MBOX_OP_INVALID = 0x0000, > > CXL_MBOX_OP_RAW = CXL_MBOX_OP_INVALID, > > CXL_MBOX_OP_ACTIVATE_FW = 0x0202, > > + CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400, > > + CXL_MBOX_OP_GET_LOG = 0x0401, > > CXL_MBOX_OP_IDENTIFY = 0x4000, > > CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101, > > CXL_MBOX_OP_SET_LSA = 0x4103, > > @@ -103,6 +105,19 @@ static DEFINE_IDA(cxl_memdev_ida); > > static struct dentry *cxl_debugfs; > > static bool raw_allow_all; > > > > +enum { > > + CEL_UUID, > > + VENDOR_DEBUG_UUID > > Who wants to take a bet this will get extended at somepoint in the future? > Add a trailing comma to make that less noisy. > > They would never have used a UUID if this wasn't expected to expand. > CXL spec calls out that "The following Log Identifier UUIDs are defined in _this_ > specification" rather implying other specs may well define more. > Fun for the future! > > > +}; > > + > > +/* See CXL 2.0 Table 170. Get Log Input Payload */ > > +static const uuid_t log_uuid[] = { > > + [CEL_UUID] = UUID_INIT(0xda9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 0x96, > > + 0xb1, 0x62, 0x3b, 0x3f, 0x17), > > + [VENDOR_DEBUG_UUID] = UUID_INIT(0xe1819d9, 0x11a9, 0x400c, 0x81, 0x1f, > > + 0xd6, 0x07, 0x19, 0x40, 0x3d, 0x86) > > likewise on trailing comma > > > +}; > > + > > /** > > * struct cxl_mem_command - Driver representation of a memory device command > > * @info: Command information as it exists for the UAPI > > @@ -111,6 +126,8 @@ static bool raw_allow_all; > > * > > * * %CXL_CMD_FLAG_MANDATORY: Hardware must support this command. This flag is > > * only used internally by the driver for sanity checking. > > + * * %CXL_CMD_INTERNAL_FLAG_PSEUDO: This is a pseudo command which doesn't have > > + * a direct mapping to hardware. They are implicitly always enabled. > > Stale comment? > > > * > > * The cxl_mem_command is the driver's internal representation of commands that > > * are supported by the driver. Some of these commands may not be supported by > > @@ -146,6 +163,7 @@ static struct cxl_mem_command mem_commands[] = { > > #ifdef CONFIG_CXL_MEM_RAW_COMMANDS > > CXL_CMD(RAW, NONE, ~0, ~0), > > #endif > > + CXL_CMD(GET_SUPPORTED_LOGS, NONE, 0, ~0), > > }; > > > > /* > > @@ -627,6 +645,10 @@ static int cxl_validate_cmd_from_user(struct cxl_mem *cxlm, > > c = &mem_commands[send_cmd->id]; > > info = &c->info; > > > > + /* Check that the command is enabled for hardware */ > > + if (!test_bit(info->id, cxlm->enabled_cmds)) > > + return -ENOTTY; > > + > > if (info->flags & CXL_MEM_COMMAND_FLAG_KERNEL) > > return -EPERM; > > > > @@ -869,6 +891,14 @@ static struct cxl_mem *cxl_mem_create(struct pci_dev *pdev, u32 reg_lo, > > mutex_init(&cxlm->mbox_mutex); > > cxlm->pdev = pdev; > > cxlm->regs = regs + offset; > > + cxlm->enabled_cmds = > > + devm_kmalloc_array(dev, BITS_TO_LONGS(cxl_cmd_count), > > + sizeof(unsigned long), > > + GFP_KERNEL | __GFP_ZERO); > > Hmm. There doesn't seem to be a devm_bitmap_zalloc > > Embarrassingly one of the google hits on the topic is me suggesting > this in a previous review (that I'd long since forgotten) > > Perhaps one for a refactoring patch after this lands. > > > > + if (!cxlm->enabled_cmds) { > > + dev_err(dev, "No memory available for bitmap\n"); > > + return NULL; > > + } > > > > dev_dbg(dev, "Mapped CXL Memory Device resource\n"); > > return cxlm; > > @@ -1088,6 +1118,188 @@ static int cxl_mem_add_memdev(struct cxl_mem *cxlm) > > return rc; > > } > > > > +struct cxl_mbox_get_log { > > + uuid_t uuid; > > + __le32 offset; > > + __le32 length; > > +} __packed; > > + > > +static int cxl_xfer_log(struct cxl_mem *cxlm, uuid_t *uuid, u32 size, u8 *out) > > +{ > > + u32 remaining = size; > > + u32 offset = 0; > > + > > + while (remaining) { > > + u32 xfer_size = min_t(u32, remaining, cxlm->payload_size); > > + struct cxl_mbox_get_log log = { > > + .uuid = *uuid, > > + .offset = cpu_to_le32(offset), > > + .length = cpu_to_le32(xfer_size) > > + }; > > + struct mbox_cmd mbox_cmd = { > > + .opcode = CXL_MBOX_OP_GET_LOG, > > + .payload_in = &log, > > + .payload_out = out, > > + .size_in = sizeof(log), > > + }; > > + int rc; > > + > > + rc = cxl_mem_mbox_send_cmd(cxlm, &mbox_cmd); > > + if (rc) > > + return rc; > > + > > + WARN_ON(mbox_cmd.size_out != xfer_size); > > Just for completeness (as already addressed in one of Ben's replies > to earlier patch) this is missing handling for the return code. > > > + > > + out += xfer_size; > > + remaining -= xfer_size; > > + offset += xfer_size; > > + } > > + > > + return 0; > > +} > > + > > +static inline struct cxl_mem_command *cxl_mem_find_command(u16 opcode) > > +{ > > + struct cxl_mem_command *c; > > + > > + cxl_for_each_cmd(c) > > + if (c->opcode == opcode) > > + return c; > > + > > + return NULL; > > +} > > + > > +static void cxl_enable_cmd(struct cxl_mem *cxlm, > > + const struct cxl_mem_command *cmd) > > +{ > > + if (test_and_set_bit(cmd->info.id, cxlm->enabled_cmds)) > > + dev_WARN_ONCE(&cxlm->pdev->dev, true, "cmd enabled twice\n"); > > +} > > + > > +/** > > + * cxl_walk_cel() - Walk through the Command Effects Log. > > + * @cxlm: Device. > > + * @size: Length of the Command Effects Log. > > + * @cel: CEL > > + * > > + * Iterate over each entry in the CEL and determine if the driver supports the > > + * command. If so, the command is enabled for the device and can be used later. > > + */ > > +static void cxl_walk_cel(struct cxl_mem *cxlm, size_t size, u8 *cel) > > +{ > > + struct cel_entry { > > + __le16 opcode; > > + __le16 effect; > > + } *cel_entry; > > Driver is currently marking a bunch of other structures packed that don't > need it. Perhaps do this one as well for consistency? > Just for my memory later... I don't actually recall the history here. I had no intention originally to use __packed, but they just kind of got in there, and it doesn't really hurt so we've left them. There are a few CXL structures which need packed (which is unfortunate), but this isn't one of them. > > + const int cel_entries = size / sizeof(*cel_entry); > > + int i; > > + > > + cel_entry = (struct cel_entry *)cel; > > + > > + for (i = 0; i < cel_entries; i++) { > > + const struct cel_entry *ce = &cel_entry[i]; > > Given ce is only ever used to get the ce->opcode maybe better using that > as the local variable? > > u16 opcode = le16_to_cpu(cel_entry[i].opcode) > > Obviously that might change depending on later patches though. > Thanks. I did this and got rid of the const below and was able to remove the line split below. You'll learn I'm a little const-happy. > > > + const struct cxl_mem_command *cmd = > > + cxl_mem_find_command(le16_to_cpu(ce->opcode)); > > + > > + if (!cmd) { > > + dev_dbg(&cxlm->pdev->dev, "Unsupported opcode 0x%04x", > > Unsupported by who? (driver rather than hardware) > > > + le16_to_cpu(ce->opcode)); > > + continue; > > + } > > + > > + cxl_enable_cmd(cxlm, cmd); > > + } > > +} > > + > > +/** > > + * cxl_mem_enumerate_cmds() - Enumerate commands for a device. > > + * @cxlm: The device. > > + * > > + * Returns 0 if enumerate completed successfully. > > + * > > + * CXL devices have optional support for certain commands. This function will > > + * determine the set of supported commands for the hardware and update the > > + * enabled_cmds bitmap in the @cxlm. > > + */ > > +static int cxl_mem_enumerate_cmds(struct cxl_mem *cxlm) > > +{ > > + struct device *dev = &cxlm->pdev->dev; > > + struct cxl_mbox_get_supported_logs { > > + __le16 entries; > > + u8 rsvd[6]; > > + struct gsl_entry { > > + uuid_t uuid; > > + __le32 size; > > + } __packed entry[2]; > > + } __packed gsl; > > + struct mbox_cmd mbox_cmd = { > > + .opcode = CXL_MBOX_OP_GET_SUPPORTED_LOGS, > > + .payload_out = &gsl, > > + .size_in = 0, > > + }; > > + int i, rc; > > + > > + rc = cxl_mem_mbox_get(cxlm); > > + if (rc) > > + return rc; > > + > > + rc = cxl_mem_mbox_send_cmd(cxlm, &mbox_cmd); > > + if (rc) > > + goto out; > > + > > + if (mbox_cmd.return_code != CXL_MBOX_SUCCESS) { > > + rc = -ENXIO; > > + goto out; > > + } > > + > > + if (mbox_cmd.size_out > sizeof(gsl)) { > > + dev_warn(dev, "%zu excess logs\n", > > + (mbox_cmd.size_out - sizeof(gsl)) / > > + sizeof(struct gsl_entry)); > > This could well happen given spec seems to allow for other > entries defined by other specs. Interesting. When I read the spec before (multiple times) I was certain it said other UUIDs aren't allowed. You're correct though that the way it is worded, this is a bad check. AIUI, the spec permits any UUID and as such I think we should remove tainting for unknown UUIDs. Let me put the exact words: Table 169 & 170 "Log Identifier: UUID representing the log to retrieve data for. The following Log Identifier UUIDs are defined in this specification" To me this implies UUIDs from other (not "this") specifications are permitted. Dan, I'd like your opinion here. I'm tempted to change the current WARN to a dev_dbg or somesuch. > > Note that it's this path that I mentioned earlier as requiring we sanity > check the output size available before calling mempcy_fromio into it > with the hardware supported size. Since posting, I've already reworked this somewhat based on the other changes and it should be safe now. > > > > + } > > + > > + for (i = 0; i < le16_to_cpu(gsl.entries); i++) { > > + u32 size = le32_to_cpu(gsl.entry[i].size); > > + uuid_t uuid = gsl.entry[i].uuid; > > + u8 *log; > > + > > + dev_dbg(dev, "Found LOG type %pU of size %d", &uuid, size); > > + > > + if (!uuid_equal(&uuid, &log_uuid[CEL_UUID])) > > + continue; > > + > > + /* > > + * It's a hardware bug if the log size is less than the input > > + * payload size because there are many mandatory commands. > > + */ > > + if (sizeof(struct cxl_mbox_get_log) > size) { > > If you are going to talk about less than in the comment, I'd flip the condition > around so it lines up. Trivial obviously but nice to tidy up. > > > + dev_err(dev, "CEL log size reported was too small (%d)", > > + size); > > + rc = -ENOMEM; > > + goto out; > > + } > > + > > + log = kvmalloc(size, GFP_KERNEL); > > + if (!log) { > > + rc = -ENOMEM; > > + goto out; > > + } > > + > > + rc = cxl_xfer_log(cxlm, &uuid, size, log); > > + if (rc) { > > + kvfree(log); > > + goto out; > > + } > > + > > + cxl_walk_cel(cxlm, size, log); > > + kvfree(log); > > + } > > + > > +out: > > + cxl_mem_mbox_put(cxlm); > > + return rc; > > +} > > + > > /** > > * cxl_mem_identify() - Send the IDENTIFY command to the device. > > * @cxlm: The device to identify. > > @@ -1211,6 +1423,10 @@ static int cxl_mem_probe(struct pci_dev *pdev, const struct pci_device_id *id) > > if (rc) > > return rc; > > > > + rc = cxl_mem_enumerate_cmds(cxlm); > > + if (rc) > > + return rc; > > + > > rc = cxl_mem_identify(cxlm); > > if (rc) > > return rc; > > diff --git a/include/uapi/linux/cxl_mem.h b/include/uapi/linux/cxl_mem.h > > index 72d1eb601a5d..c5e75b9dad9d 100644 > > --- a/include/uapi/linux/cxl_mem.h > > +++ b/include/uapi/linux/cxl_mem.h > > @@ -23,6 +23,7 @@ > > ___C(INVALID, "Invalid Command"), \ > > ___C(IDENTIFY, "Identify Command"), \ > > ___C(RAW, "Raw device command"), \ > > + ___C(GET_SUPPORTED_LOGS, "Get Supported Logs"), \ > > ___C(MAX, "Last command") > > > > #define ___C(a, b) CXL_MEM_COMMAND_ID_##a >
On 21-02-11 09:55:48, Jonathan Cameron wrote: > On Wed, 10 Feb 2021 10:16:05 -0800 > Ben Widawsky <ben.widawsky@intel.com> wrote: > > > On 21-02-10 08:55:57, Ben Widawsky wrote: > > > On 21-02-10 15:07:59, Jonathan Cameron wrote: > > > > On Wed, 10 Feb 2021 13:32:52 +0000 > > > > Jonathan Cameron <Jonathan.Cameron@Huawei.com> wrote: > > > > > > > > > On Tue, 9 Feb 2021 16:02:53 -0800 > > > > > Ben Widawsky <ben.widawsky@intel.com> wrote: > > > > > > > > > > > Provide enough functionality to utilize the mailbox of a memory device. > > > > > > The mailbox is used to interact with the firmware running on the memory > > > > > > device. The flow is proven with one implemented command, "identify". > > > > > > Because the class code has already told the driver this is a memory > > > > > > device and the identify command is mandatory. > > > > > > > > > > > > CXL devices contain an array of capabilities that describe the > > > > > > interactions software can have with the device or firmware running on > > > > > > the device. A CXL compliant device must implement the device status and > > > > > > the mailbox capability. Additionally, a CXL compliant memory device must > > > > > > implement the memory device capability. Each of the capabilities can > > > > > > [will] provide an offset within the MMIO region for interacting with the > > > > > > CXL device. > > > > > > > > > > > > The capabilities tell the driver how to find and map the register space > > > > > > for CXL Memory Devices. The registers are required to utilize the CXL > > > > > > spec defined mailbox interface. The spec outlines two mailboxes, primary > > > > > > and secondary. The secondary mailbox is earmarked for system firmware, > > > > > > and not handled in this driver. > > > > > > > > > > > > Primary mailboxes are capable of generating an interrupt when submitting > > > > > > a background command. That implementation is saved for a later time. > > > > > > > > > > > > Link: https://www.computeexpresslink.org/download-the-specification > > > > > > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> > > > > > > Reviewed-by: Dan Williams <dan.j.williams@intel.com> > > > > > > > > > > Hi Ben, > > > > > > > > > > > > > > > > +/** > > > > > > + * cxl_mem_mbox_send_cmd() - Send a mailbox command to a memory device. > > > > > > + * @cxlm: The CXL memory device to communicate with. > > > > > > + * @mbox_cmd: Command to send to the memory device. > > > > > > + * > > > > > > + * Context: Any context. Expects mbox_lock to be held. > > > > > > + * Return: -ETIMEDOUT if timeout occurred waiting for completion. 0 on success. > > > > > > + * Caller should check the return code in @mbox_cmd to make sure it > > > > > > + * succeeded. > > > > > > > > > > cxl_xfer_log() doesn't check mbox_cmd->return_code and for my test it currently > > > > > enters an infinite loop as a result. > > > > > > I meant to fix that. > > > > > > > > > > > > > I haven't checked other paths, but to my mind it is not a good idea to require > > > > > two levels of error checking - the example here proves how easy it is to forget > > > > > one. > > > > > > Demonstrably, you're correct. I think it would be good to have a kernel only > > > mbox command that does the error checking though. Let me type something up and > > > see how it looks. > > > > Hi Jonathan. What do you think of this? The bit I'm on the fence about is if I > > should validate output size too. I like the simplicity as it is, but it requires > > every caller to possibly check output size, which is kind of the same problem > > you're originally pointing out. > > The simplicity is good and this is pretty much what I expected you would end up with > (always reassuring) > > For the output, perhaps just add another parameter to the wrapper for minimum > output length expected? > > Now you mention the length question. It does rather feel like there should also > be some protection on memcpy_fromio() copying too much data if the hardware > happens to return an unexpectedly long length. Should never happen, but > the hardening is worth adding anyway given it's easy to do. > > Jonathan > I like it. diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index 2e199b05f686..58071a203212 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -293,7 +293,7 @@ static void cxl_mem_mbox_put(struct cxl_mem *cxlm) * See __cxl_mem_mbox_send_cmd() */ static int cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, u16 opcode, u8 *in, - size_t in_size, u8 *out) + size_t in_size, u8 *out, size_t out_min_size) { struct mbox_cmd mbox_cmd = { .opcode = opcode, @@ -303,6 +303,9 @@ static int cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, u16 opcode, u8 *in, }; int rc; + if (out_min_size > cxlm->payload_size) + return -E2BIG; + rc = cxl_mem_mbox_get(cxlm); if (rc) return rc; @@ -316,6 +319,9 @@ static int cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, u16 opcode, u8 *in, if (mbox_cmd.return_code != CXL_MBOX_SUCCESS) return -ENXIO; + if (mbox_cmd.size_out < out_min_size) + return -ENODATA; + return mbox_cmd.size_out; } @@ -505,15 +511,10 @@ static int cxl_mem_identify(struct cxl_mem *cxlm) int rc; rc = cxl_mem_mbox_send_cmd(cxlm, CXL_MBOX_OP_IDENTIFY, NULL, 0, - (u8 *)&id); + (u8 *)&id, sizeof(id)); if (rc < 0) return rc; - if (rc < sizeof(id)) { - dev_err(&cxlm->pdev->dev, "Short identify data\n"); - return -ENXIO; - } - /* * TODO: enumerate DPA map, as 'ram' and 'pmem' do not alias. * For now, only the capacity is exported in sysfs > > > > > diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c > > index 55c5f5a6023f..ad7b2077ab28 100644 > > --- a/drivers/cxl/mem.c > > +++ b/drivers/cxl/mem.c > > @@ -284,7 +284,7 @@ static void cxl_mem_mbox_timeout(struct cxl_mem *cxlm, > > } > > > > /** > > - * cxl_mem_mbox_send_cmd() - Send a mailbox command to a memory device. > > + * __cxl_mem_mbox_send_cmd() - Execute a mailbox command > > * @cxlm: The CXL memory device to communicate with. > > * @mbox_cmd: Command to send to the memory device. > > * > > @@ -296,7 +296,8 @@ static void cxl_mem_mbox_timeout(struct cxl_mem *cxlm, > > * This is a generic form of the CXL mailbox send command, thus the only I/O > > * operations used are cxl_read_mbox_reg(). Memory devices, and perhaps other > > * types of CXL devices may have further information available upon error > > - * conditions. > > + * conditions. Driver facilities wishing to send mailbox commands should use the > > + * wrapper command. > > * > > * The CXL spec allows for up to two mailboxes. The intention is for the primary > > * mailbox to be OS controlled and the secondary mailbox to be used by system > > @@ -304,8 +305,8 @@ static void cxl_mem_mbox_timeout(struct cxl_mem *cxlm, > > * not need to coordinate with each other. The driver only uses the primary > > * mailbox. > > */ > > -static int cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, > > - struct mbox_cmd *mbox_cmd) > > +static int __cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, > > + struct mbox_cmd *mbox_cmd) > > { > > void __iomem *payload = cxlm->mbox_regs + CXLDEV_MBOX_PAYLOAD_OFFSET; > > u64 cmd_reg, status_reg; > > @@ -469,6 +470,54 @@ static void cxl_mem_mbox_put(struct cxl_mem *cxlm) > > mutex_unlock(&cxlm->mbox_mutex); > > } > > > > +/** > > + * cxl_mem_mbox_send_cmd() - Send a mailbox command to a memory device. > > + * @cxlm: The CXL memory device to communicate with. > > + * @opcode: Opcode for the mailbox command. > > + * @in: The input payload for the mailbox command. > > + * @in_size: The length of the input payload > > + * @out: Caller allocated buffer for the output. > > + * > > + * Context: Any context. Will acquire and release mbox_mutex. > > + * Return: > > + * * %>=0 - Number of bytes returned in @out. > > + * * %-EBUSY - Couldn't acquire exclusive mailbox access. > > + * * %-EFAULT - Hardware error occurred. > > + * * %-ENXIO - Command completed, but device reported an error. > > + * > > + * Mailbox commands may execute successfully yet the device itself reported an > > + * error. While this distinction can be useful for commands from userspace, the > > + * kernel will often only care when both are successful. > > + * > > + * See __cxl_mem_mbox_send_cmd() > > + */ > > +static int cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, u16 opcode, u8 *in, > > + size_t in_size, u8 *out) > > +{ > > + struct mbox_cmd mbox_cmd = { > > + .opcode = opcode, > > + .payload_in = in, > > + .size_in = in_size, > > + .payload_out = out, > > + }; > > + int rc; > > + > > + rc = cxl_mem_mbox_get(cxlm); > > + if (rc) > > + return rc; > > + > > + rc = __cxl_mem_mbox_send_cmd(cxlm, &mbox_cmd); > > + cxl_mem_mbox_put(cxlm); > > + if (rc) > > + return rc; > > + > > + /* TODO: Map return code to proper kernel style errno */ > > + if (mbox_cmd.return_code != CXL_MBOX_SUCCESS) > > + return -ENXIO; > > + > > + return mbox_cmd.size_out; > > +} > > + > > /** > > * handle_mailbox_cmd_from_user() - Dispatch a mailbox command. > > * @cxlmd: The CXL memory device to communicate with. > > @@ -1380,33 +1429,18 @@ static int cxl_mem_identify(struct cxl_mem *cxlm) > > u8 poison_caps; > > u8 qos_telemetry_caps; > > } __packed id; > > - struct mbox_cmd mbox_cmd = { > > - .opcode = CXL_MBOX_OP_IDENTIFY, > > - .payload_out = &id, > > - .size_in = 0, > > - }; > > int rc; > > > > - /* Retrieve initial device memory map */ > > - rc = cxl_mem_mbox_get(cxlm); > > - if (rc) > > - return rc; > > - > > - rc = cxl_mem_mbox_send_cmd(cxlm, &mbox_cmd); > > - cxl_mem_mbox_put(cxlm); > > - if (rc) > > + rc = cxl_mem_mbox_send_cmd(cxlm, CXL_MBOX_OP_IDENTIFY, NULL, 0, > > + (u8 *)&id); > > + if (rc < 0) > > return rc; > > > > - /* TODO: Handle retry or reset responses from firmware. */ > > - if (mbox_cmd.return_code != CXL_MBOX_SUCCESS) { > > - dev_err(&cxlm->pdev->dev, "Mailbox command failed (%d)\n", > > - mbox_cmd.return_code); > > + if (rc < sizeof(id)) { > > + dev_err(&cxlm->pdev->dev, "Short identify data\n", > > return -ENXIO; > > } > > > > - if (mbox_cmd.size_out != sizeof(id)) > > - return -ENXIO; > > - > > /* > > * TODO: enumerate DPA map, as 'ram' and 'pmem' do not alias. > > * For now, only the capacity is exported in sysfs > > > > > > [snip] > > >
On Thu, Feb 11, 2021 at 9:45 AM Ben Widawsky <ben.widawsky@intel.com> wrote: [..] > > > + if (mbox_cmd.size_out > sizeof(gsl)) { > > > + dev_warn(dev, "%zu excess logs\n", > > > + (mbox_cmd.size_out - sizeof(gsl)) / > > > + sizeof(struct gsl_entry)); > > > > This could well happen given spec seems to allow for other > > entries defined by other specs. > > Interesting. When I read the spec before (multiple times) I was certain it said > other UUIDs aren't allowed. You're correct though that the way it is worded, > this is a bad check. AIUI, the spec permits any UUID and as such I think we > should remove tainting for unknown UUIDs. Let me put the exact words: > > Table 169 & 170 > "Log Identifier: UUID representing the log to retrieve data for. The following > Log Identifier UUIDs are defined in this specification" > > To me this implies UUIDs from other (not "this") specifications are permitted. > > Dan, I'd like your opinion here. I'm tempted to change the current WARN to a > dev_dbg or somesuch. Yeah, sounds ok, and the command is well defined to be a read-only, zero-side-effect affair. If a vendor did really want to sneak in a proprietary protocol over this interface it would be quite awkward.
On Thu, Feb 11, 2021 at 2:19 AM Jonathan Cameron <Jonathan.Cameron@huawei.com> wrote: > > On Wed, 10 Feb 2021 18:17:25 +0000 > Jonathan Cameron <Jonathan.Cameron@Huawei.com> wrote: > > > On Tue, 9 Feb 2021 16:02:54 -0800 > > Ben Widawsky <ben.widawsky@intel.com> wrote: > > > > > From: Dan Williams <dan.j.williams@intel.com> > > > > > > Create the /sys/bus/cxl hierarchy to enumerate: > > > > > > * Memory Devices (per-endpoint control devices) > > > > > > * Memory Address Space Devices (platform address ranges with > > > interleaving, performance, and persistence attributes) > > > > > > * Memory Regions (active provisioned memory from an address space device > > > that is in use as System RAM or delegated to libnvdimm as Persistent > > > Memory regions). > > > > > > For now, only the per-endpoint control devices are registered on the > > > 'cxl' bus. However, going forward it will provide a mechanism to > > > coordinate cross-device interleave. > > > > > > Signed-off-by: Dan Williams <dan.j.williams@intel.com> > > > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> > > > > One stray header, and a request for a tiny bit of reordering to > > make it easier to chase through creation and destruction. > > > > Either way with the header move to earlier patch I'm fine with this one. > > > > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > > Actually thinking more on this, what is the justification for the > complexity + overhead of a percpu_refcount vs a refcount A typical refcount does not have the block and drain semantics of a percpu_ref. I'm planning to circle back and make this a first class facility of the cdev interface borrowing the debugfs approach [1], but for now percpu_ref fits the bill locally. > I don't think this is a high enough performance path for it to matter. > Perhaps I'm missing a usecase where it does? It's less about percpu_ref performance and more about the percpu_ref_tryget_live() facility. [1]: http://lore.kernel.org/r/CAPcyv4jEYPsyh0bhbtKGRbK3bgp=_+=2rjx4X0gLi5-25VvDyg@mail.gmail.com
On Thu, 11 Feb 2021 10:27:41 -0800 Ben Widawsky <ben.widawsky@intel.com> wrote: > On 21-02-11 09:55:48, Jonathan Cameron wrote: > > On Wed, 10 Feb 2021 10:16:05 -0800 > > Ben Widawsky <ben.widawsky@intel.com> wrote: > > > > > On 21-02-10 08:55:57, Ben Widawsky wrote: > > > > On 21-02-10 15:07:59, Jonathan Cameron wrote: > > > > > On Wed, 10 Feb 2021 13:32:52 +0000 > > > > > Jonathan Cameron <Jonathan.Cameron@Huawei.com> wrote: > > > > > > > > > > > On Tue, 9 Feb 2021 16:02:53 -0800 > > > > > > Ben Widawsky <ben.widawsky@intel.com> wrote: > > > > > > > > > > > > > Provide enough functionality to utilize the mailbox of a memory device. > > > > > > > The mailbox is used to interact with the firmware running on the memory > > > > > > > device. The flow is proven with one implemented command, "identify". > > > > > > > Because the class code has already told the driver this is a memory > > > > > > > device and the identify command is mandatory. > > > > > > > > > > > > > > CXL devices contain an array of capabilities that describe the > > > > > > > interactions software can have with the device or firmware running on > > > > > > > the device. A CXL compliant device must implement the device status and > > > > > > > the mailbox capability. Additionally, a CXL compliant memory device must > > > > > > > implement the memory device capability. Each of the capabilities can > > > > > > > [will] provide an offset within the MMIO region for interacting with the > > > > > > > CXL device. > > > > > > > > > > > > > > The capabilities tell the driver how to find and map the register space > > > > > > > for CXL Memory Devices. The registers are required to utilize the CXL > > > > > > > spec defined mailbox interface. The spec outlines two mailboxes, primary > > > > > > > and secondary. The secondary mailbox is earmarked for system firmware, > > > > > > > and not handled in this driver. > > > > > > > > > > > > > > Primary mailboxes are capable of generating an interrupt when submitting > > > > > > > a background command. That implementation is saved for a later time. > > > > > > > > > > > > > > Link: https://www.computeexpresslink.org/download-the-specification > > > > > > > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> > > > > > > > Reviewed-by: Dan Williams <dan.j.williams@intel.com> > > > > > > > > > > > > Hi Ben, > > > > > > > > > > > > > > > > > > > +/** > > > > > > > + * cxl_mem_mbox_send_cmd() - Send a mailbox command to a memory device. > > > > > > > + * @cxlm: The CXL memory device to communicate with. > > > > > > > + * @mbox_cmd: Command to send to the memory device. > > > > > > > + * > > > > > > > + * Context: Any context. Expects mbox_lock to be held. > > > > > > > + * Return: -ETIMEDOUT if timeout occurred waiting for completion. 0 on success. > > > > > > > + * Caller should check the return code in @mbox_cmd to make sure it > > > > > > > + * succeeded. > > > > > > > > > > > > cxl_xfer_log() doesn't check mbox_cmd->return_code and for my test it currently > > > > > > enters an infinite loop as a result. > > > > > > > > I meant to fix that. > > > > > > > > > > > > > > > > I haven't checked other paths, but to my mind it is not a good idea to require > > > > > > two levels of error checking - the example here proves how easy it is to forget > > > > > > one. > > > > > > > > Demonstrably, you're correct. I think it would be good to have a kernel only > > > > mbox command that does the error checking though. Let me type something up and > > > > see how it looks. > > > > > > Hi Jonathan. What do you think of this? The bit I'm on the fence about is if I > > > should validate output size too. I like the simplicity as it is, but it requires > > > every caller to possibly check output size, which is kind of the same problem > > > you're originally pointing out. > > > > The simplicity is good and this is pretty much what I expected you would end up with > > (always reassuring) > > > > For the output, perhaps just add another parameter to the wrapper for minimum > > output length expected? > > > > Now you mention the length question. It does rather feel like there should also > > be some protection on memcpy_fromio() copying too much data if the hardware > > happens to return an unexpectedly long length. Should never happen, but > > the hardening is worth adding anyway given it's easy to do. > > > > Jonathan > > > > I like it. > > diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c > index 2e199b05f686..58071a203212 100644 > --- a/drivers/cxl/mem.c > +++ b/drivers/cxl/mem.c > @@ -293,7 +293,7 @@ static void cxl_mem_mbox_put(struct cxl_mem *cxlm) > * See __cxl_mem_mbox_send_cmd() > */ > static int cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, u16 opcode, u8 *in, > - size_t in_size, u8 *out) > + size_t in_size, u8 *out, size_t out_min_size) This is kind of the opposite of what I was expecting. What I'm worried about is not so much that we receive at least enough data, but rather that we receive too much. Buggy hardware or potentially a spec change being most likely causes. So something like int __cxl_mem_mbox_send_cmd(struct cxl_mem..., struct mbox_cmd, u8 *out, size_t out_sz) //Or put the max size in the .size_out element of the command and make that inout rather //than just out direction. { ... /* #8 */ if (out_len && mbox_cmd->payload_out) { if (outlen > out_sz) //or just copy what we can fit in payload_out and return that size. return -E2BIG; memcpy_fromio(mbox_cmd->payload_out, payload, out_len); } } Fine to also check the returned length is at least a minimum size. > { > struct mbox_cmd mbox_cmd = { > .opcode = opcode, > @@ -303,6 +303,9 @@ static int cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, u16 opcode, u8 *in, > }; > int rc; > > + if (out_min_size > cxlm->payload_size) > + return -E2BIG; > + > rc = cxl_mem_mbox_get(cxlm); > if (rc) > return rc; > @@ -316,6 +319,9 @@ static int cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, u16 opcode, u8 *in, > if (mbox_cmd.return_code != CXL_MBOX_SUCCESS) > return -ENXIO; > > + if (mbox_cmd.size_out < out_min_size) > + return -ENODATA; > + > return mbox_cmd.size_out; > } > > @@ -505,15 +511,10 @@ static int cxl_mem_identify(struct cxl_mem *cxlm) > int rc; > > rc = cxl_mem_mbox_send_cmd(cxlm, CXL_MBOX_OP_IDENTIFY, NULL, 0, > - (u8 *)&id); > + (u8 *)&id, sizeof(id)); > if (rc < 0) > return rc; > > - if (rc < sizeof(id)) { > - dev_err(&cxlm->pdev->dev, "Short identify data\n"); > - return -ENXIO; > - } > - > /* > * TODO: enumerate DPA map, as 'ram' and 'pmem' do not alias. > * For now, only the capacity is exported in sysfs > > > > > > > > > > diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c > > > index 55c5f5a6023f..ad7b2077ab28 100644 > > > --- a/drivers/cxl/mem.c > > > +++ b/drivers/cxl/mem.c > > > @@ -284,7 +284,7 @@ static void cxl_mem_mbox_timeout(struct cxl_mem *cxlm, > > > } > > > > > > /** > > > - * cxl_mem_mbox_send_cmd() - Send a mailbox command to a memory device. > > > + * __cxl_mem_mbox_send_cmd() - Execute a mailbox command > > > * @cxlm: The CXL memory device to communicate with. > > > * @mbox_cmd: Command to send to the memory device. > > > * > > > @@ -296,7 +296,8 @@ static void cxl_mem_mbox_timeout(struct cxl_mem *cxlm, > > > * This is a generic form of the CXL mailbox send command, thus the only I/O > > > * operations used are cxl_read_mbox_reg(). Memory devices, and perhaps other > > > * types of CXL devices may have further information available upon error > > > - * conditions. > > > + * conditions. Driver facilities wishing to send mailbox commands should use the > > > + * wrapper command. > > > * > > > * The CXL spec allows for up to two mailboxes. The intention is for the primary > > > * mailbox to be OS controlled and the secondary mailbox to be used by system > > > @@ -304,8 +305,8 @@ static void cxl_mem_mbox_timeout(struct cxl_mem *cxlm, > > > * not need to coordinate with each other. The driver only uses the primary > > > * mailbox. > > > */ > > > -static int cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, > > > - struct mbox_cmd *mbox_cmd) > > > +static int __cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, > > > + struct mbox_cmd *mbox_cmd) > > > { > > > void __iomem *payload = cxlm->mbox_regs + CXLDEV_MBOX_PAYLOAD_OFFSET; > > > u64 cmd_reg, status_reg; > > > @@ -469,6 +470,54 @@ static void cxl_mem_mbox_put(struct cxl_mem *cxlm) > > > mutex_unlock(&cxlm->mbox_mutex); > > > } > > > > > > +/** > > > + * cxl_mem_mbox_send_cmd() - Send a mailbox command to a memory device. > > > + * @cxlm: The CXL memory device to communicate with. > > > + * @opcode: Opcode for the mailbox command. > > > + * @in: The input payload for the mailbox command. > > > + * @in_size: The length of the input payload > > > + * @out: Caller allocated buffer for the output. > > > + * > > > + * Context: Any context. Will acquire and release mbox_mutex. > > > + * Return: > > > + * * %>=0 - Number of bytes returned in @out. > > > + * * %-EBUSY - Couldn't acquire exclusive mailbox access. > > > + * * %-EFAULT - Hardware error occurred. > > > + * * %-ENXIO - Command completed, but device reported an error. > > > + * > > > + * Mailbox commands may execute successfully yet the device itself reported an > > > + * error. While this distinction can be useful for commands from userspace, the > > > + * kernel will often only care when both are successful. > > > + * > > > + * See __cxl_mem_mbox_send_cmd() > > > + */ > > > +static int cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, u16 opcode, u8 *in, > > > + size_t in_size, u8 *out) > > > +{ > > > + struct mbox_cmd mbox_cmd = { > > > + .opcode = opcode, > > > + .payload_in = in, > > > + .size_in = in_size, > > > + .payload_out = out, > > > + }; > > > + int rc; > > > + > > > + rc = cxl_mem_mbox_get(cxlm); > > > + if (rc) > > > + return rc; > > > + > > > + rc = __cxl_mem_mbox_send_cmd(cxlm, &mbox_cmd); > > > + cxl_mem_mbox_put(cxlm); > > > + if (rc) > > > + return rc; > > > + > > > + /* TODO: Map return code to proper kernel style errno */ > > > + if (mbox_cmd.return_code != CXL_MBOX_SUCCESS) > > > + return -ENXIO; > > > + > > > + return mbox_cmd.size_out; > > > +} > > > + > > > /** > > > * handle_mailbox_cmd_from_user() - Dispatch a mailbox command. > > > * @cxlmd: The CXL memory device to communicate with. > > > @@ -1380,33 +1429,18 @@ static int cxl_mem_identify(struct cxl_mem *cxlm) > > > u8 poison_caps; > > > u8 qos_telemetry_caps; > > > } __packed id; > > > - struct mbox_cmd mbox_cmd = { > > > - .opcode = CXL_MBOX_OP_IDENTIFY, > > > - .payload_out = &id, > > > - .size_in = 0, > > > - }; > > > int rc; > > > > > > - /* Retrieve initial device memory map */ > > > - rc = cxl_mem_mbox_get(cxlm); > > > - if (rc) > > > - return rc; > > > - > > > - rc = cxl_mem_mbox_send_cmd(cxlm, &mbox_cmd); > > > - cxl_mem_mbox_put(cxlm); > > > - if (rc) > > > + rc = cxl_mem_mbox_send_cmd(cxlm, CXL_MBOX_OP_IDENTIFY, NULL, 0, > > > + (u8 *)&id); > > > + if (rc < 0) > > > return rc; > > > > > > - /* TODO: Handle retry or reset responses from firmware. */ > > > - if (mbox_cmd.return_code != CXL_MBOX_SUCCESS) { > > > - dev_err(&cxlm->pdev->dev, "Mailbox command failed (%d)\n", > > > - mbox_cmd.return_code); > > > + if (rc < sizeof(id)) { > > > + dev_err(&cxlm->pdev->dev, "Short identify data\n", > > > return -ENXIO; > > > } > > > > > > - if (mbox_cmd.size_out != sizeof(id)) > > > - return -ENXIO; > > > - > > > /* > > > * TODO: enumerate DPA map, as 'ram' and 'pmem' do not alias. > > > * For now, only the capacity is exported in sysfs > > > > > > > > > [snip] > > > > >
On Thu, 11 Feb 2021 07:55:29 -0800 Ben Widawsky <ben.widawsky@intel.com> wrote: > On 21-02-11 09:55:48, Jonathan Cameron wrote: > > On Wed, 10 Feb 2021 10:16:05 -0800 > > Ben Widawsky <ben.widawsky@intel.com> wrote: > > > > > On 21-02-10 08:55:57, Ben Widawsky wrote: > > > > On 21-02-10 15:07:59, Jonathan Cameron wrote: > > > > > On Wed, 10 Feb 2021 13:32:52 +0000 > > > > > Jonathan Cameron <Jonathan.Cameron@Huawei.com> wrote: > > > > > > > > > > > On Tue, 9 Feb 2021 16:02:53 -0800 > > > > > > Ben Widawsky <ben.widawsky@intel.com> wrote: > > > > > > > > > > > > > Provide enough functionality to utilize the mailbox of a memory device. > > > > > > > The mailbox is used to interact with the firmware running on the memory > > > > > > > device. The flow is proven with one implemented command, "identify". > > > > > > > Because the class code has already told the driver this is a memory > > > > > > > device and the identify command is mandatory. > > > > > > > > > > > > > > CXL devices contain an array of capabilities that describe the > > > > > > > interactions software can have with the device or firmware running on > > > > > > > the device. A CXL compliant device must implement the device status and > > > > > > > the mailbox capability. Additionally, a CXL compliant memory device must > > > > > > > implement the memory device capability. Each of the capabilities can > > > > > > > [will] provide an offset within the MMIO region for interacting with the > > > > > > > CXL device. > > > > > > > > > > > > > > The capabilities tell the driver how to find and map the register space > > > > > > > for CXL Memory Devices. The registers are required to utilize the CXL > > > > > > > spec defined mailbox interface. The spec outlines two mailboxes, primary > > > > > > > and secondary. The secondary mailbox is earmarked for system firmware, > > > > > > > and not handled in this driver. > > > > > > > > > > > > > > Primary mailboxes are capable of generating an interrupt when submitting > > > > > > > a background command. That implementation is saved for a later time. > > > > > > > > > > > > > > Link: https://www.computeexpresslink.org/download-the-specification > > > > > > > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> > > > > > > > Reviewed-by: Dan Williams <dan.j.williams@intel.com> > > > > > > > > > > > > Hi Ben, > > > > > > > > > > > > > > > > > > > +/** > > > > > > > + * cxl_mem_mbox_send_cmd() - Send a mailbox command to a memory device. > > > > > > > + * @cxlm: The CXL memory device to communicate with. > > > > > > > + * @mbox_cmd: Command to send to the memory device. > > > > > > > + * > > > > > > > + * Context: Any context. Expects mbox_lock to be held. > > > > > > > + * Return: -ETIMEDOUT if timeout occurred waiting for completion. 0 on success. > > > > > > > + * Caller should check the return code in @mbox_cmd to make sure it > > > > > > > + * succeeded. > > > > > > > > > > > > cxl_xfer_log() doesn't check mbox_cmd->return_code and for my test it currently > > > > > > enters an infinite loop as a result. > > > > > > > > I meant to fix that. > > > > > > > > > > > > > > > > I haven't checked other paths, but to my mind it is not a good idea to require > > > > > > two levels of error checking - the example here proves how easy it is to forget > > > > > > one. > > > > > > > > Demonstrably, you're correct. I think it would be good to have a kernel only > > > > mbox command that does the error checking though. Let me type something up and > > > > see how it looks. > > > > > > Hi Jonathan. What do you think of this? The bit I'm on the fence about is if I > > > should validate output size too. I like the simplicity as it is, but it requires > > > every caller to possibly check output size, which is kind of the same problem > > > you're originally pointing out. > > > > The simplicity is good and this is pretty much what I expected you would end up with > > (always reassuring) > > > > For the output, perhaps just add another parameter to the wrapper for minimum > > output length expected? > > > > Now you mention the length question. It does rather feel like there should also > > be some protection on memcpy_fromio() copying too much data if the hardware > > happens to return an unexpectedly long length. Should never happen, but > > the hardening is worth adding anyway given it's easy to do. > > > > Jonathan > > Some background because I forget what I've said previously... It's unfortunate > that the spec maxes at 1M mailbox size but has enough bits in the length field > to support 2M-1. I've made some requests to have this fixed, so maybe 3.0 won't > be awkward like this. Agreed spec should be tighter here, but I'd argue over 1M indicates buggy hardware. > > I think it makes sense to do as you suggested. One question though, do you have > an opinion on we return to the caller as the output payload size, do we cap it > at 1M also, or are we honest? > > - if (out_len && mbox_cmd->payload_out) > - memcpy_fromio(mbox_cmd->payload_out, payload, out_len); > + if (out_len && mbox_cmd->payload_out) { > + size_t n = min_t(size_t, cxlm->payload_size, out_len); > + memcpy_fromio(mbox_cmd->payload_out, payload, n); > + } Ah, I read emails in wrong order. What you have is what I expected and got confused about in your other email. > > So... > mbox_cmd->size_out = out_len; > mbox_cmd->size_out = n; Good question. My gut says the second one. Maybe it's worth a warning print to let us know something unexpected happened. > > > > > > > > > > > > diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c > > > index 55c5f5a6023f..ad7b2077ab28 100644 > > > --- a/drivers/cxl/mem.c > > > +++ b/drivers/cxl/mem.c > > > @@ -284,7 +284,7 @@ static void cxl_mem_mbox_timeout(struct cxl_mem *cxlm, > > > } > > > > > > /** > > > - * cxl_mem_mbox_send_cmd() - Send a mailbox command to a memory device. > > > + * __cxl_mem_mbox_send_cmd() - Execute a mailbox command > > > * @cxlm: The CXL memory device to communicate with. > > > * @mbox_cmd: Command to send to the memory device. > > > * > > > @@ -296,7 +296,8 @@ static void cxl_mem_mbox_timeout(struct cxl_mem *cxlm, > > > * This is a generic form of the CXL mailbox send command, thus the only I/O > > > * operations used are cxl_read_mbox_reg(). Memory devices, and perhaps other > > > * types of CXL devices may have further information available upon error > > > - * conditions. > > > + * conditions. Driver facilities wishing to send mailbox commands should use the > > > + * wrapper command. > > > * > > > * The CXL spec allows for up to two mailboxes. The intention is for the primary > > > * mailbox to be OS controlled and the secondary mailbox to be used by system > > > @@ -304,8 +305,8 @@ static void cxl_mem_mbox_timeout(struct cxl_mem *cxlm, > > > * not need to coordinate with each other. The driver only uses the primary > > > * mailbox. > > > */ > > > -static int cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, > > > - struct mbox_cmd *mbox_cmd) > > > +static int __cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, > > > + struct mbox_cmd *mbox_cmd) > > > { > > > void __iomem *payload = cxlm->mbox_regs + CXLDEV_MBOX_PAYLOAD_OFFSET; > > > u64 cmd_reg, status_reg; > > > @@ -469,6 +470,54 @@ static void cxl_mem_mbox_put(struct cxl_mem *cxlm) > > > mutex_unlock(&cxlm->mbox_mutex); > > > } > > > > > > +/** > > > + * cxl_mem_mbox_send_cmd() - Send a mailbox command to a memory device. > > > + * @cxlm: The CXL memory device to communicate with. > > > + * @opcode: Opcode for the mailbox command. > > > + * @in: The input payload for the mailbox command. > > > + * @in_size: The length of the input payload > > > + * @out: Caller allocated buffer for the output. > > > + * > > > + * Context: Any context. Will acquire and release mbox_mutex. > > > + * Return: > > > + * * %>=0 - Number of bytes returned in @out. > > > + * * %-EBUSY - Couldn't acquire exclusive mailbox access. > > > + * * %-EFAULT - Hardware error occurred. > > > + * * %-ENXIO - Command completed, but device reported an error. > > > + * > > > + * Mailbox commands may execute successfully yet the device itself reported an > > > + * error. While this distinction can be useful for commands from userspace, the > > > + * kernel will often only care when both are successful. > > > + * > > > + * See __cxl_mem_mbox_send_cmd() > > > + */ > > > +static int cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, u16 opcode, u8 *in, > > > + size_t in_size, u8 *out) > > > +{ > > > + struct mbox_cmd mbox_cmd = { > > > + .opcode = opcode, > > > + .payload_in = in, > > > + .size_in = in_size, > > > + .payload_out = out, > > > + }; > > > + int rc; > > > + > > > + rc = cxl_mem_mbox_get(cxlm); > > > + if (rc) > > > + return rc; > > > + > > > + rc = __cxl_mem_mbox_send_cmd(cxlm, &mbox_cmd); > > > + cxl_mem_mbox_put(cxlm); > > > + if (rc) > > > + return rc; > > > + > > > + /* TODO: Map return code to proper kernel style errno */ > > > + if (mbox_cmd.return_code != CXL_MBOX_SUCCESS) > > > + return -ENXIO; > > > + > > > + return mbox_cmd.size_out; > > > +} > > > + > > > /** > > > * handle_mailbox_cmd_from_user() - Dispatch a mailbox command. > > > * @cxlmd: The CXL memory device to communicate with. > > > @@ -1380,33 +1429,18 @@ static int cxl_mem_identify(struct cxl_mem *cxlm) > > > u8 poison_caps; > > > u8 qos_telemetry_caps; > > > } __packed id; > > > - struct mbox_cmd mbox_cmd = { > > > - .opcode = CXL_MBOX_OP_IDENTIFY, > > > - .payload_out = &id, > > > - .size_in = 0, > > > - }; > > > int rc; > > > > > > - /* Retrieve initial device memory map */ > > > - rc = cxl_mem_mbox_get(cxlm); > > > - if (rc) > > > - return rc; > > > - > > > - rc = cxl_mem_mbox_send_cmd(cxlm, &mbox_cmd); > > > - cxl_mem_mbox_put(cxlm); > > > - if (rc) > > > + rc = cxl_mem_mbox_send_cmd(cxlm, CXL_MBOX_OP_IDENTIFY, NULL, 0, > > > + (u8 *)&id); > > > + if (rc < 0) > > > return rc; > > > > > > - /* TODO: Handle retry or reset responses from firmware. */ > > > - if (mbox_cmd.return_code != CXL_MBOX_SUCCESS) { > > > - dev_err(&cxlm->pdev->dev, "Mailbox command failed (%d)\n", > > > - mbox_cmd.return_code); > > > + if (rc < sizeof(id)) { > > > + dev_err(&cxlm->pdev->dev, "Short identify data\n", > > > return -ENXIO; > > > } > > > > > > - if (mbox_cmd.size_out != sizeof(id)) > > > - return -ENXIO; > > > - > > > /* > > > * TODO: enumerate DPA map, as 'ram' and 'pmem' do not alias. > > > * For now, only the capacity is exported in sysfs > > > > > > > > > [snip] > > > > >
On Thu, 11 Feb 2021 12:40:45 -0800 Dan Williams <dan.j.williams@intel.com> wrote: > On Thu, Feb 11, 2021 at 2:19 AM Jonathan Cameron > <Jonathan.Cameron@huawei.com> wrote: > > > > On Wed, 10 Feb 2021 18:17:25 +0000 > > Jonathan Cameron <Jonathan.Cameron@Huawei.com> wrote: > > > > > On Tue, 9 Feb 2021 16:02:54 -0800 > > > Ben Widawsky <ben.widawsky@intel.com> wrote: > > > > > > > From: Dan Williams <dan.j.williams@intel.com> > > > > > > > > Create the /sys/bus/cxl hierarchy to enumerate: > > > > > > > > * Memory Devices (per-endpoint control devices) > > > > > > > > * Memory Address Space Devices (platform address ranges with > > > > interleaving, performance, and persistence attributes) > > > > > > > > * Memory Regions (active provisioned memory from an address space device > > > > that is in use as System RAM or delegated to libnvdimm as Persistent > > > > Memory regions). > > > > > > > > For now, only the per-endpoint control devices are registered on the > > > > 'cxl' bus. However, going forward it will provide a mechanism to > > > > coordinate cross-device interleave. > > > > > > > > Signed-off-by: Dan Williams <dan.j.williams@intel.com> > > > > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> > > > > > > One stray header, and a request for a tiny bit of reordering to > > > make it easier to chase through creation and destruction. > > > > > > Either way with the header move to earlier patch I'm fine with this one. > > > > > > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > > > > Actually thinking more on this, what is the justification for the > > complexity + overhead of a percpu_refcount vs a refcount > > A typical refcount does not have the block and drain semantics of a > percpu_ref. I'm planning to circle back and make this a first class > facility of the cdev interface borrowing the debugfs approach [1], but > for now percpu_ref fits the bill locally. > > > I don't think this is a high enough performance path for it to matter. > > Perhaps I'm missing a usecase where it does? > > It's less about percpu_ref performance and more about the > percpu_ref_tryget_live() facility. > > [1]: http://lore.kernel.org/r/CAPcyv4jEYPsyh0bhbtKGRbK3bgp=_+=2rjx4X0gLi5-25VvDyg@mail.gmail.com Thanks for the reference. Definitely a nasty corner to clean up so I'll keep an eye open for a new version of that series. Jonathan
On 21-02-12 13:27:06, Jonathan Cameron wrote: > On Thu, 11 Feb 2021 07:55:29 -0800 > Ben Widawsky <ben.widawsky@intel.com> wrote: > > > On 21-02-11 09:55:48, Jonathan Cameron wrote: > > > On Wed, 10 Feb 2021 10:16:05 -0800 > > > Ben Widawsky <ben.widawsky@intel.com> wrote: > > > > > > > On 21-02-10 08:55:57, Ben Widawsky wrote: > > > > > On 21-02-10 15:07:59, Jonathan Cameron wrote: > > > > > > On Wed, 10 Feb 2021 13:32:52 +0000 > > > > > > Jonathan Cameron <Jonathan.Cameron@Huawei.com> wrote: > > > > > > > > > > > > > On Tue, 9 Feb 2021 16:02:53 -0800 > > > > > > > Ben Widawsky <ben.widawsky@intel.com> wrote: > > > > > > > > > > > > > > > Provide enough functionality to utilize the mailbox of a memory device. > > > > > > > > The mailbox is used to interact with the firmware running on the memory > > > > > > > > device. The flow is proven with one implemented command, "identify". > > > > > > > > Because the class code has already told the driver this is a memory > > > > > > > > device and the identify command is mandatory. > > > > > > > > > > > > > > > > CXL devices contain an array of capabilities that describe the > > > > > > > > interactions software can have with the device or firmware running on > > > > > > > > the device. A CXL compliant device must implement the device status and > > > > > > > > the mailbox capability. Additionally, a CXL compliant memory device must > > > > > > > > implement the memory device capability. Each of the capabilities can > > > > > > > > [will] provide an offset within the MMIO region for interacting with the > > > > > > > > CXL device. > > > > > > > > > > > > > > > > The capabilities tell the driver how to find and map the register space > > > > > > > > for CXL Memory Devices. The registers are required to utilize the CXL > > > > > > > > spec defined mailbox interface. The spec outlines two mailboxes, primary > > > > > > > > and secondary. The secondary mailbox is earmarked for system firmware, > > > > > > > > and not handled in this driver. > > > > > > > > > > > > > > > > Primary mailboxes are capable of generating an interrupt when submitting > > > > > > > > a background command. That implementation is saved for a later time. > > > > > > > > > > > > > > > > Link: https://www.computeexpresslink.org/download-the-specification > > > > > > > > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> > > > > > > > > Reviewed-by: Dan Williams <dan.j.williams@intel.com> > > > > > > > > > > > > > > Hi Ben, > > > > > > > > > > > > > > > > > > > > > > +/** > > > > > > > > + * cxl_mem_mbox_send_cmd() - Send a mailbox command to a memory device. > > > > > > > > + * @cxlm: The CXL memory device to communicate with. > > > > > > > > + * @mbox_cmd: Command to send to the memory device. > > > > > > > > + * > > > > > > > > + * Context: Any context. Expects mbox_lock to be held. > > > > > > > > + * Return: -ETIMEDOUT if timeout occurred waiting for completion. 0 on success. > > > > > > > > + * Caller should check the return code in @mbox_cmd to make sure it > > > > > > > > + * succeeded. > > > > > > > > > > > > > > cxl_xfer_log() doesn't check mbox_cmd->return_code and for my test it currently > > > > > > > enters an infinite loop as a result. > > > > > > > > > > I meant to fix that. > > > > > > > > > > > > > > > > > > > I haven't checked other paths, but to my mind it is not a good idea to require > > > > > > > two levels of error checking - the example here proves how easy it is to forget > > > > > > > one. > > > > > > > > > > Demonstrably, you're correct. I think it would be good to have a kernel only > > > > > mbox command that does the error checking though. Let me type something up and > > > > > see how it looks. > > > > > > > > Hi Jonathan. What do you think of this? The bit I'm on the fence about is if I > > > > should validate output size too. I like the simplicity as it is, but it requires > > > > every caller to possibly check output size, which is kind of the same problem > > > > you're originally pointing out. > > > > > > The simplicity is good and this is pretty much what I expected you would end up with > > > (always reassuring) > > > > > > For the output, perhaps just add another parameter to the wrapper for minimum > > > output length expected? > > > > > > Now you mention the length question. It does rather feel like there should also > > > be some protection on memcpy_fromio() copying too much data if the hardware > > > happens to return an unexpectedly long length. Should never happen, but > > > the hardening is worth adding anyway given it's easy to do. > > > > > > Jonathan > > > > Some background because I forget what I've said previously... It's unfortunate > > that the spec maxes at 1M mailbox size but has enough bits in the length field > > to support 2M-1. I've made some requests to have this fixed, so maybe 3.0 won't > > be awkward like this. > > Agreed spec should be tighter here, but I'd argue over 1M indicates buggy hardware. > > > > > I think it makes sense to do as you suggested. One question though, do you have > > an opinion on we return to the caller as the output payload size, do we cap it > > at 1M also, or are we honest? > > > > - if (out_len && mbox_cmd->payload_out) > > - memcpy_fromio(mbox_cmd->payload_out, payload, out_len); > > + if (out_len && mbox_cmd->payload_out) { > > + size_t n = min_t(size_t, cxlm->payload_size, out_len); > > + memcpy_fromio(mbox_cmd->payload_out, payload, n); > > + } > > Ah, I read emails in wrong order. What you have is what I expected and got > confused about in your other email. > > > > > So... > > mbox_cmd->size_out = out_len; > > mbox_cmd->size_out = n; > > Good question. My gut says the second one. > Maybe it's worth a warning print to let us know something > unexpected happened. > I also prefer 'n', It's unfortunate though if userspace hits this condition, it would have to scrape kernel logs to find out. Perhaps though userspace wouldn't ever really care. > > > > > > > > > > > > > > > > > > diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c > > > > index 55c5f5a6023f..ad7b2077ab28 100644 > > > > --- a/drivers/cxl/mem.c > > > > +++ b/drivers/cxl/mem.c > > > > @@ -284,7 +284,7 @@ static void cxl_mem_mbox_timeout(struct cxl_mem *cxlm, > > > > } > > > > > > > > /** > > > > - * cxl_mem_mbox_send_cmd() - Send a mailbox command to a memory device. > > > > + * __cxl_mem_mbox_send_cmd() - Execute a mailbox command > > > > * @cxlm: The CXL memory device to communicate with. > > > > * @mbox_cmd: Command to send to the memory device. > > > > * > > > > @@ -296,7 +296,8 @@ static void cxl_mem_mbox_timeout(struct cxl_mem *cxlm, > > > > * This is a generic form of the CXL mailbox send command, thus the only I/O > > > > * operations used are cxl_read_mbox_reg(). Memory devices, and perhaps other > > > > * types of CXL devices may have further information available upon error > > > > - * conditions. > > > > + * conditions. Driver facilities wishing to send mailbox commands should use the > > > > + * wrapper command. > > > > * > > > > * The CXL spec allows for up to two mailboxes. The intention is for the primary > > > > * mailbox to be OS controlled and the secondary mailbox to be used by system > > > > @@ -304,8 +305,8 @@ static void cxl_mem_mbox_timeout(struct cxl_mem *cxlm, > > > > * not need to coordinate with each other. The driver only uses the primary > > > > * mailbox. > > > > */ > > > > -static int cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, > > > > - struct mbox_cmd *mbox_cmd) > > > > +static int __cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, > > > > + struct mbox_cmd *mbox_cmd) > > > > { > > > > void __iomem *payload = cxlm->mbox_regs + CXLDEV_MBOX_PAYLOAD_OFFSET; > > > > u64 cmd_reg, status_reg; > > > > @@ -469,6 +470,54 @@ static void cxl_mem_mbox_put(struct cxl_mem *cxlm) > > > > mutex_unlock(&cxlm->mbox_mutex); > > > > } > > > > > > > > +/** > > > > + * cxl_mem_mbox_send_cmd() - Send a mailbox command to a memory device. > > > > + * @cxlm: The CXL memory device to communicate with. > > > > + * @opcode: Opcode for the mailbox command. > > > > + * @in: The input payload for the mailbox command. > > > > + * @in_size: The length of the input payload > > > > + * @out: Caller allocated buffer for the output. > > > > + * > > > > + * Context: Any context. Will acquire and release mbox_mutex. > > > > + * Return: > > > > + * * %>=0 - Number of bytes returned in @out. > > > > + * * %-EBUSY - Couldn't acquire exclusive mailbox access. > > > > + * * %-EFAULT - Hardware error occurred. > > > > + * * %-ENXIO - Command completed, but device reported an error. > > > > + * > > > > + * Mailbox commands may execute successfully yet the device itself reported an > > > > + * error. While this distinction can be useful for commands from userspace, the > > > > + * kernel will often only care when both are successful. > > > > + * > > > > + * See __cxl_mem_mbox_send_cmd() > > > > + */ > > > > +static int cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, u16 opcode, u8 *in, > > > > + size_t in_size, u8 *out) > > > > +{ > > > > + struct mbox_cmd mbox_cmd = { > > > > + .opcode = opcode, > > > > + .payload_in = in, > > > > + .size_in = in_size, > > > > + .payload_out = out, > > > > + }; > > > > + int rc; > > > > + > > > > + rc = cxl_mem_mbox_get(cxlm); > > > > + if (rc) > > > > + return rc; > > > > + > > > > + rc = __cxl_mem_mbox_send_cmd(cxlm, &mbox_cmd); > > > > + cxl_mem_mbox_put(cxlm); > > > > + if (rc) > > > > + return rc; > > > > + > > > > + /* TODO: Map return code to proper kernel style errno */ > > > > + if (mbox_cmd.return_code != CXL_MBOX_SUCCESS) > > > > + return -ENXIO; > > > > + > > > > + return mbox_cmd.size_out; > > > > +} > > > > + > > > > /** > > > > * handle_mailbox_cmd_from_user() - Dispatch a mailbox command. > > > > * @cxlmd: The CXL memory device to communicate with. > > > > @@ -1380,33 +1429,18 @@ static int cxl_mem_identify(struct cxl_mem *cxlm) > > > > u8 poison_caps; > > > > u8 qos_telemetry_caps; > > > > } __packed id; > > > > - struct mbox_cmd mbox_cmd = { > > > > - .opcode = CXL_MBOX_OP_IDENTIFY, > > > > - .payload_out = &id, > > > > - .size_in = 0, > > > > - }; > > > > int rc; > > > > > > > > - /* Retrieve initial device memory map */ > > > > - rc = cxl_mem_mbox_get(cxlm); > > > > - if (rc) > > > > - return rc; > > > > - > > > > - rc = cxl_mem_mbox_send_cmd(cxlm, &mbox_cmd); > > > > - cxl_mem_mbox_put(cxlm); > > > > - if (rc) > > > > + rc = cxl_mem_mbox_send_cmd(cxlm, CXL_MBOX_OP_IDENTIFY, NULL, 0, > > > > + (u8 *)&id); > > > > + if (rc < 0) > > > > return rc; > > > > > > > > - /* TODO: Handle retry or reset responses from firmware. */ > > > > - if (mbox_cmd.return_code != CXL_MBOX_SUCCESS) { > > > > - dev_err(&cxlm->pdev->dev, "Mailbox command failed (%d)\n", > > > > - mbox_cmd.return_code); > > > > + if (rc < sizeof(id)) { > > > > + dev_err(&cxlm->pdev->dev, "Short identify data\n", > > > > return -ENXIO; > > > > } > > > > > > > > - if (mbox_cmd.size_out != sizeof(id)) > > > > - return -ENXIO; > > > > - > > > > /* > > > > * TODO: enumerate DPA map, as 'ram' and 'pmem' do not alias. > > > > * For now, only the capacity is exported in sysfs > > > > > > > > > > > > [snip] > > > > > > > >
On Thu, Feb 11, 2021 at 1:12 PM Jonathan Cameron <Jonathan.Cameron@huawei.com> wrote: > [snip!] > > > > @@ -869,6 +891,14 @@ static struct cxl_mem *cxl_mem_create(struct pci_dev *pdev, u32 reg_lo, > > mutex_init(&cxlm->mbox_mutex); > > cxlm->pdev = pdev; > > cxlm->regs = regs + offset; > > + cxlm->enabled_cmds = > > + devm_kmalloc_array(dev, BITS_TO_LONGS(cxl_cmd_count), > > + sizeof(unsigned long), > > + GFP_KERNEL | __GFP_ZERO); > > Hmm. There doesn't seem to be a devm_bitmap_zalloc > FYI I've implemented both devm_bitmap_zalloc() as well as devm_bitmap_alloc() and made them part of a series I sent out to linux-gpio two weeks ago (surprisingly - it's nowhere to be found on lkml or spinics or even patchwork :/). The patches didn't make it for v5.12 but I'll respin them after the merge window, so we'll have those devres helpers for v5.13. Bartosz
# Changes since v1 [1] * Squash together several other patches (Ben) * Make register locator only search the DVSEC size. Bug fix. (Ben) * Get rid of anonymous structs in send UAPI (Ben) * Rename "MB" to "MBOX" in defines (Ben) * Dynamically allocate enable_cmds bitmask (Ben) * Async probe (Dan) * Remove get_live_device() (Dan) * CXL_MAILBOX_TIMEOUT_MS 2*HZ instead of runtime conversion (Dan) * Reword RAW Kconfig help (Dan) * Move IOCTL handlers to their own functions (Dan) * Remove HIDDEN flag (Dan) * Remove MUTEX flag (Dan) * Get rid of const info in mem_command (Dan) * Remove useless mbox initialiazation in user commands (Dan) * Rename DEBUG_UUID to VENDOR_DEBUG_UUID (Dan) * Remove dev_info of enabled commands (Dan) * Get rid of MANDATORY and PSEUDO flags (Dan) * Clarify cmd vs. mbox_cmd in send by removing cmd (Dan) * This results in removal of some very unlikely debug messages. * Reword Kconfig (David) * Cap payload size max to 1M to match spec (David) * * Driver still binds, but IOCTls fail if too large. * s/US/MS for timeout (David) * Fix comment indenting to denote, not part of spec (David) * Use struct initializer for mailbox command (David) * Add units to sysfs ABI documentation (David) * Use FIELD_GET for register locator parsing (hch) * Use FIELD_GET/SET directly instead of wrappers (hch) * Remove cpp guards (hch) * Drop register read/write helpers (hch) * Squash together device capability patches (hch) * Move PCI_CLASS_MEMORY_CXL to pci_ids.h (hch) * Use file_inode instead of file->private_data (hch) * Hide RAW commands behind CONFIG option (Konrad) * Include security_locked_down() check (Konrad) * Extend past 80 characters in certain places (Konrad) * Remove magic numbers of register locator enumeration (Konrad) * Fix packing for send UAPI (Konrad) --- In addition to the mailing list, please feel free to use #cxl on oftc IRC for discussion. --- # Summary Introduce support for “type-3” memory devices defined in the Compute Express Link (CXL) 2.0 specification [2]. Specifically, these are the memory devices defined by section 8.2.8.5 of the CXL 2.0 spec. A reference implementation emulating these devices has been submitted to the QEMU mailing list [3] and is available on gitlab [4], but will move to a shared tree on kernel.org after initial acceptance. “Type-3” is a CXL device that acts as a memory expander for RAM or Persistent Memory. The device might be interleaved with other CXL devices in a given physical address range. In addition to the core functionality of discovering the spec defined registers and resources, introduce a CXL device model that will be the foundation for translating CXL capabilities into existing Linux infrastructure for Persistent Memory and other memory devices. For now, this only includes support for the management command mailbox the surfacing of type-3 devices. These control devices fill the role of “DIMMs” / nmemX memory-devices in LIBNVDIMM terms. ## Userspace Interaction Interaction with the driver and type-3 devices via the CXL drivers is introduced in this patch series and considered stable ABI. They include * sysfs - Documentation/ABI/testing/sysfs-bus-cxl * IOCTL - Documentation/driver-api/cxl/memory-devices.rst * debugfs - Documentation/ABI/testing/debugfs-debug Work is in process to add support for CXL interactions to the ndctl project [5] ### Development plans One of the unique challenges that CXL imposes on the Linux driver model is that it requires the operating system to perform physical address space management interleaved across devices and bridges. Whereas LIBNVDIMM handles a list of established static persistent memory address ranges (for example from the ACPI NFIT), CXL introduces hotplug and the concept of allocating address space to instantiate persistent memory ranges. This is similar to PCI in the sense that the platform establishes the MMIO range for PCI BARs to be allocated, but it is significantly complicated by the fact that a given device can optionally be interleaved with other devices and can participate in several interleave-sets at once. LIBNVDIMM handled something like this with the aliasing between PMEM and BLOCK-WINDOW mode, but CXL adds flexibility to alias DEVICE MEMORY through up to 10 decoders per device. All of the above needs to be enabled with respect to PCI hotplug events on Type-3 memory device which needs hooks to determine if a given device is contributing to a "System RAM" address range that is unable to be unplugged. In other words CXL ties PCI hotplug to Memory Hotplug and PCI hotplug needs to be able to negotiate with memory hotplug. In the medium term the implications of CXL hotplug vs ACPI SRAT/SLIT/HMAT need to be reconciled. One capability that seems to be needed is either the dynamic allocation of new memory nodes, or default initializing extra pgdat instances beyond what is enumerated in ACPI SRAT to accommodate hot-added CXL memory. Patches welcome, questions welcome as the development effort on the post v5.12 capabilities proceeds. ## Running in QEMU The incantation to get CXL support in QEMU [4] is considered unstable at this time. Future readers of this cover letter should verify if any changes are needed. For the novice QEMU user, the following can be copy/pasted into a working QEMU commandline. It is enough to make the simplest topology possible. The topology would consist of a single memory window, single type3 device, single root port, and single host bridge. +-------------+ | CXL PXB | | | | +-------+ |<----------+ | |CXL RP | | | +--+-------+--+ v | +----------+ | | "window" | | +----------+ v ^ +-------------+ | | CXL Type 3 | | | Device |<----------+ +-------------+ // Memory backend for "window" -object memory-backend-file,id=cxl-mem1,share,mem-path=cxl-type3,size=512M // Memory backend for LSA -object memory-backend-file,id=cxl-mem1-lsa,share,mem-path=cxl-mem1-lsa,size=1K // Host Bridge -device pxb-cxl id=cxl.0,bus=pcie.0,bus_nr=52,uid=0 len-window-base=1,window-base[0]=0x4c0000000 memdev[0]=cxl-mem1 // Single root port -device cxl rp,id=rp0,bus=cxl.0,addr=0.0,chassis=0,slot=0,memdev=cxl-mem1 // Single type3 device -device cxl-type3,bus=rp0,memdev=cxl-mem1,id=cxl-pmem0,size=256M -device cxl-type3,bus=rp1,memdev=cxl-mem1,id=cxl-pmem1,size=256M,lsa=cxl-mem1-lsa --- [1]: https://lore.kernel.org/linux-cxl/20210130002438.1872527-1-ben.widawsky@intel.com/ [2]: https://www.computeexpresslink.org/](https://www.computeexpresslink.org/) [3]: https://lore.kernel.org/qemu-devel/20210202005948.241655-1-ben.widawsky@intel.com/ [4]: https://gitlab.com/bwidawsk/qemu/-/tree/cxl-2.0v4 [5]: https://github.com/pmem/ndctl/tree/cxl-2.0v2 --- Ben Widawsky (6): cxl/mem: Find device capabilities cxl/mem: Add basic IOCTL interface cxl/mem: Add a "RAW" send command cxl/mem: Enable commands via CEL cxl/mem: Add set of informational commands MAINTAINERS: Add maintainers of the CXL driver Dan Williams (2): cxl/mem: Introduce a driver for CXL-2.0-Type-3 endpoints cxl/mem: Register CXL memX devices .clang-format | 1 + Documentation/ABI/testing/sysfs-bus-cxl | 26 + Documentation/driver-api/cxl/index.rst | 12 + .../driver-api/cxl/memory-devices.rst | 46 + Documentation/driver-api/index.rst | 1 + .../userspace-api/ioctl/ioctl-number.rst | 1 + MAINTAINERS | 11 + drivers/Kconfig | 1 + drivers/Makefile | 1 + drivers/cxl/Kconfig | 67 + drivers/cxl/Makefile | 7 + drivers/cxl/bus.c | 29 + drivers/cxl/cxl.h | 99 ++ drivers/cxl/mem.c | 1544 +++++++++++++++++ drivers/cxl/pci.h | 31 + include/linux/pci_ids.h | 1 + include/uapi/linux/cxl_mem.h | 168 ++ include/uapi/linux/pci_regs.h | 1 + 18 files changed, 2047 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-cxl create mode 100644 Documentation/driver-api/cxl/index.rst create mode 100644 Documentation/driver-api/cxl/memory-devices.rst create mode 100644 drivers/cxl/Kconfig create mode 100644 drivers/cxl/Makefile create mode 100644 drivers/cxl/bus.c create mode 100644 drivers/cxl/cxl.h create mode 100644 drivers/cxl/mem.c create mode 100644 drivers/cxl/pci.h create mode 100644 include/uapi/linux/cxl_mem.h Cc: linux-acpi@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-nvdimm@lists.01.org Cc: linux-pci@vger.kernel.org Cc: Bjorn Helgaas <helgaas@kernel.org> Cc: Chris Browy <cbrowy@avery-design.com> Cc: Christoph Hellwig <hch@infradead.org> Cc: Dan Williams <dan.j.williams@intel.com> Cc: David Hildenbrand <david@redhat.com> Cc: David Rientjes <rientjes@google.com> Cc: Ira Weiny <ira.weiny@intel.com> Cc: Jon Masters <jcm@jonmasters.org> Cc: Jonathan Cameron <Jonathan.Cameron@Huawei.com> Cc: Rafael Wysocki <rafael.j.wysocki@intel.com> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Vishal Verma <vishal.l.verma@intel.com> Cc: "John Groves (jgroves)" <jgroves@micron.com> Cc: "Kelley, Sean V" <sean.v.kelley@intel.com>