| Message ID | 1611648234-15043-1-git-send-email-henryc.chen@mediatek.com |
|---|---|
| Headers | show |
| Series | Add driver for dvfsrc, support for interconnect | expand |
On Tue, Jan 26, 2021 at 04:03:43PM +0800, Henry Chen wrote: > Document the binding for enabling dvfsrc on MediaTek SoC. > > Signed-off-by: Henry Chen <henryc.chen@mediatek.com> > --- > .../devicetree/bindings/soc/mediatek/dvfsrc.yaml | 67 ++++++++++++++++++++++ > include/dt-bindings/interconnect/mtk,mt8183-emi.h | 21 +++++++ > 2 files changed, 88 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml > create mode 100644 include/dt-bindings/interconnect/mtk,mt8183-emi.h > > diff --git a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml > new file mode 100644 > index 0000000..0b746a8 > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml > @@ -0,0 +1,67 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/soc/mediatek/dvfsrc.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: MediaTek dynamic voltage and frequency scaling resource collector (DVFSRC) > + > +description: | > + The Dynamic Voltage and Frequency Scaling Resource Collector (DVFSRC) is a > + HW module which is used to collect all the requests from both software and > + hardware and turn into the decision of minimum operating voltage and minimum > + DRAM frequency to fulfill those requests. > + > +maintainers: > + - henryc.chen <henryc.chen@mediatek.com> > + > +properties: > + reg: > + description: DVFSRC common register address and length. maxItems: 1 > + > + compatible: > + enum: > + - mediatek,mt6873-dvfsrc > + - mediatek,mt8183-dvfsrc > + - mediatek,mt8192-dvfsrc > + > + '#interconnect-cells': > + const: 1 > + > +patternProperties: > + dvfsrc-vcore: Not a pattern. Move to 'properties'. > + type: object > + description: > + The DVFSRC regulator is modelled as a subdevice of the DVFSRC. > + Because DVFSRC can request power directly via register read/write, likes > + vcore which is a core power of mt8183. As such, the DVFSRC regulator > + requires that DVFSRC nodes be present. > + $ref: /schemas/regulator/regulator.yaml# > + > +required: > + - compatible > + - reg > + - "#interconnect-cells" > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interconnect/mtk,mt8183-emi.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + dvfsrc@10012000 { > + compatible = "mediatek,mt8183-dvfsrc"; > + reg = <0 0x10012000 0 0x1000>; > + #interconnect-cells = <1>; > + dvfsrc_vcore: dvfsrc-vcore { > + regulator-name = "dvfsrc-vcore"; > + regulator-min-microvolt = <725000>; > + regulator-max-microvolt = <800000>; > + regulator-always-on; > + }; > + }; > + }; > diff --git a/include/dt-bindings/interconnect/mtk,mt8183-emi.h b/include/dt-bindings/interconnect/mtk,mt8183-emi.h > new file mode 100644 > index 0000000..dfd143f > --- /dev/null > +++ b/include/dt-bindings/interconnect/mtk,mt8183-emi.h > @@ -0,0 +1,21 @@ > +/* SPDX-License-Identifier: GPL-2.0 > + * > + * Copyright (c) 2021 MediaTek Inc. > + */ > + > +#ifndef __DT_BINDINGS_INTERCONNECT_MTK_MT8183_EMI_H > +#define __DT_BINDINGS_INTERCONNECT_MTK_MT8183_EMI_H > + > +#define MT8183_SLAVE_DDR_EMI 0 > +#define MT8183_MASTER_MCUSYS 1 > +#define MT8183_MASTER_GPU 2 > +#define MT8183_MASTER_MMSYS 3 > +#define MT8183_MASTER_MM_VPU 4 > +#define MT8183_MASTER_MM_DISP 5 > +#define MT8183_MASTER_MM_VDEC 6 > +#define MT8183_MASTER_MM_VENC 7 > +#define MT8183_MASTER_MM_CAM 8 > +#define MT8183_MASTER_MM_IMG 9 > +#define MT8183_MASTER_MM_MDP 10 > + > +#endif > -- > 1.9.1 >
On Tue, Jan 26, 2021 at 04:03:49PM +0800, Henry Chen wrote: > Add interconnect provider dt-bindings for MT6873. > > Signed-off-by: Henry Chen <henryc.chen@mediatek.com> > --- > include/dt-bindings/interconnect/mtk,mt6873-emi.h | 41 +++++++++++++++++++++++ > 1 file changed, 41 insertions(+) > create mode 100644 include/dt-bindings/interconnect/mtk,mt6873-emi.h Odd that you put one header in patch 1 and this one separate. > > diff --git a/include/dt-bindings/interconnect/mtk,mt6873-emi.h b/include/dt-bindings/interconnect/mtk,mt6873-emi.h > new file mode 100644 > index 0000000..0b20011 > --- /dev/null > +++ b/include/dt-bindings/interconnect/mtk,mt6873-emi.h > @@ -0,0 +1,41 @@ > +/* SPDX-License-Identifier: GPL-2.0 Don't care about non-GPL users? > + * > + * Copyright (c) 2021 MediaTek Inc. > + */ > + > +#ifndef __DT_BINDINGS_INTERCONNECT_MTK_MT6873_EMI_H > +#define __DT_BINDINGS_INTERCONNECT_MTK_MT6873_EMI_H > + > +#define MT6873_SLAVE_DDR_EMI 0 > +#define MT6873_MASTER_MCUSYS 1 > +#define MT6873_MASTER_GPUSYS 2 > +#define MT6873_MASTER_MMSYS 3 > +#define MT6873_MASTER_MM_VPU 4 > +#define MT6873_MASTER_MM_DISP 5 > +#define MT6873_MASTER_MM_VDEC 6 > +#define MT6873_MASTER_MM_VENC 7 > +#define MT6873_MASTER_MM_CAM 8 > +#define MT6873_MASTER_MM_IMG 9 > +#define MT6873_MASTER_MM_MDP 10 > +#define MT6873_MASTER_VPUSYS 11 > +#define MT6873_MASTER_VPU_0 12 > +#define MT6873_MASTER_VPU_1 13 > +#define MT6873_MASTER_MDLASYS 14 > +#define MT6873_MASTER_MDLA_0 15 > +#define MT6873_MASTER_UFS 16 > +#define MT6873_MASTER_PCIE 17 > +#define MT6873_MASTER_USB 18 > +#define MT6873_MASTER_DBGIF 19 > +#define MT6873_SLAVE_HRT_DDR_EMI 20 > +#define MT6873_MASTER_HRT_MMSYS 21 > +#define MT6873_MASTER_HRT_MM_DISP 22 > +#define MT6873_MASTER_HRT_MM_VDEC 23 > +#define MT6873_MASTER_HRT_MM_VENC 24 > +#define MT6873_MASTER_HRT_MM_CAM 25 > +#define MT6873_MASTER_HRT_MM_IMG 26 > +#define MT6873_MASTER_HRT_MM_MDP 27 > +#define MT6873_MASTER_HRT_DBGIF 28 > +#define MT6873_MASTER_WIFI 29 > +#define MT6873_MASTER_BT 30 > +#define MT6873_MASTER_NETSYS 31 > +#endif > -- > 1.9.1 >