| Message ID | 20210121195250.492500-1-angelogioacchino.delregno@somainline.org |
|---|---|
| Headers | show |
| Series | cpufreq-qcom-hw: Implement full OSM programming | expand |
On 21-01-21, 20:52, AngeloGioacchino Del Regno wrote: > ** > ** NOTE: To "view the full picture", please look at the following > ** patch series: > ** https://patchwork.kernel.org/project/linux-arm-msm/list/?series=413355 > ** This is a subset of that series. > ** > > Changes in v5: > - Fixed OPP table API abuse, in conjunction with the CPR3 driver > - Some minor cleanups Tanya had some comments about the driver in the previous version, please let such discussions close before sending any new versions. I haven't seen any reviews for the major driver changes until this version and we are already on V5. Please wait for some time for people to review the patches. -- viresh
Il 22/01/21 10:46, Viresh Kumar ha scritto: > On 21-01-21, 20:52, AngeloGioacchino Del Regno wrote: >> ** >> ** NOTE: To "view the full picture", please look at the following >> ** patch series: >> ** https://patchwork.kernel.org/project/linux-arm-msm/list/?series=413355 >> ** This is a subset of that series. >> ** >> >> Changes in v5: >> - Fixed OPP table API abuse, in conjunction with the CPR3 driver >> - Some minor cleanups > > Tanya had some comments about the driver in the previous version, > please let such discussions close before sending any new versions. I > haven't seen any reviews for the major driver changes until this > version and we are already on V5. Please wait for some time for people > to review the patches. > Well, okay... it's just that I didn't want reviewers to lose time with something that had to be fixed, as it wasn't working anymore on the newest RC, due to a commit that was (rightfully!) blocking the abuse of the OPP API. I know that it may be not practical to send a new version while a discussion is in progress, but this looked like being a critical fix for the driver that I'm sending. In any case, this time it is a "final" version and will not get any more changes unless requested by reviewers/maintainers. -- Angelo
On Thu, Jan 21, 2021 at 08:52:46PM +0100, AngeloGioacchino Del Regno wrote: > From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > Add devicetree documentation for 'qcom,freq-domain' property specific > to Qualcomm CPUs. This property is used to reference the CPUFREQ node > along with Domain ID (0/1). > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > --- > Documentation/devicetree/bindings/arm/cpus.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml > index 14cd727d3c4b..1d60975df23a 100644 > --- a/Documentation/devicetree/bindings/arm/cpus.yaml > +++ b/Documentation/devicetree/bindings/arm/cpus.yaml > @@ -290,6 +290,12 @@ properties: > > * arm/msm/qcom,kpss-acc.txt > > + qcom,freq-domain: What happened to having a standard property here? There were 1 or 2 other cases of doing the same thing. > + $ref: '/schemas/types.yaml#/definitions/phandle-array' > + description: | > + CPUs supporting freq-domain must set their "qcom,freq-domain" property > + with phandle to a cpufreq_hw node followed by the Domain ID(0/1). > + > rockchip,pmu: > $ref: '/schemas/types.yaml#/definitions/phandle' > description: | > -- > 2.30.0 >
On Thu, Jan 21, 2021 at 08:52:50PM +0100, AngeloGioacchino Del Regno wrote: > The OSM programming addition has been done under the > qcom,cpufreq-hw-8998 compatible name: specify the requirement > of two additional register spaces for this functionality. > This implementation, with the same compatible, has been > tested on MSM8998 and SDM630. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > --- > .../bindings/cpufreq/cpufreq-qcom-hw.yaml | 66 +++++++++++++++---- > 1 file changed, 52 insertions(+), 14 deletions(-) > > diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml > index bc81b6203e27..17fd6a6cefb0 100644 > --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml > +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml > @@ -18,6 +18,10 @@ description: | > properties: > compatible: > oneOf: > + - description: Non-secure v1 of CPUFREQ HW > + items: > + - const: qcom,cpufreq-hw-8998 > + > - description: v1 of CPUFREQ HW > items: > - const: qcom,cpufreq-hw > @@ -28,21 +32,9 @@ properties: > - qcom,sm8250-cpufreq-epss > - const: qcom,cpufreq-epss > > - reg: > - minItems: 2 > - maxItems: 3 > - items: > - - description: Frequency domain 0 register region > - - description: Frequency domain 1 register region > - - description: Frequency domain 2 register region > + reg: {} > > - reg-names: > - minItems: 2 > - maxItems: 3 > - items: > - - const: freq-domain0 > - - const: freq-domain1 > - - const: freq-domain2 > + reg-names: {} > > clocks: > items: > @@ -57,6 +49,52 @@ properties: > '#freq-domain-cells': > const: 1 > > +if: > + properties: > + compatible: > + contains: > + const: qcom,cpufreq-hw-8998 > +then: > + properties: > + reg: > + minItems: 2 > + maxItems: 6 > + items: > + - description: Frequency domain 0 register region > + - description: Operating State Manager domain 0 register region > + - description: Frequency domain 1 register region > + - description: Operating State Manager domain 1 register region > + - description: PLL ACD domain 0 register region (if ACD programming required) > + - description: PLL ACD domain 1 register region (if ACD programming required) > + > + reg-names: > + minItems: 2 > + maxItems: 6 > + items: > + - const: "osm-domain0" > + - const: "freq-domain0" > + - const: "osm-domain1" > + - const: "freq-domain1" > + - const: "osm-acd0" > + - const: "osm-acd1" Don't need quotes. > + > +else: > + properties: > + reg: > + minItems: 2 > + maxItems: 3 > + items: > + - description: Frequency domain 0 register region > + - description: Frequency domain 1 register region > + - description: Frequency domain 2 register region > + reg-names: > + minItems: 2 > + maxItems: 3 > + items: > + - const: "freq-domain0" > + - const: "freq-domain1" > + - const: "freq-domain2" > + > required: > - compatible > - reg > -- > 2.30.0 >
Il 05/02/21 22:51, Rob Herring ha scritto: > On Thu, Jan 21, 2021 at 08:52:50PM +0100, AngeloGioacchino Del Regno wrote: >> The OSM programming addition has been done under the >> qcom,cpufreq-hw-8998 compatible name: specify the requirement >> of two additional register spaces for this functionality. >> This implementation, with the same compatible, has been >> tested on MSM8998 and SDM630. >> >> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> >> --- >> .../bindings/cpufreq/cpufreq-qcom-hw.yaml | 66 +++++++++++++++---- >> 1 file changed, 52 insertions(+), 14 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml >> index bc81b6203e27..17fd6a6cefb0 100644 >> --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml >> +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml >> @@ -18,6 +18,10 @@ description: | >> properties: >> compatible: >> oneOf: >> + - description: Non-secure v1 of CPUFREQ HW >> + items: >> + - const: qcom,cpufreq-hw-8998 >> + >> - description: v1 of CPUFREQ HW >> items: >> - const: qcom,cpufreq-hw >> @@ -28,21 +32,9 @@ properties: >> - qcom,sm8250-cpufreq-epss >> - const: qcom,cpufreq-epss >> >> - reg: >> - minItems: 2 >> - maxItems: 3 >> - items: >> - - description: Frequency domain 0 register region >> - - description: Frequency domain 1 register region >> - - description: Frequency domain 2 register region >> + reg: {} >> >> - reg-names: >> - minItems: 2 >> - maxItems: 3 >> - items: >> - - const: freq-domain0 >> - - const: freq-domain1 >> - - const: freq-domain2 >> + reg-names: {} >> >> clocks: >> items: >> @@ -57,6 +49,52 @@ properties: >> '#freq-domain-cells': >> const: 1 >> >> +if: >> + properties: >> + compatible: >> + contains: >> + const: qcom,cpufreq-hw-8998 >> +then: >> + properties: >> + reg: >> + minItems: 2 >> + maxItems: 6 >> + items: >> + - description: Frequency domain 0 register region >> + - description: Operating State Manager domain 0 register region >> + - description: Frequency domain 1 register region >> + - description: Operating State Manager domain 1 register region >> + - description: PLL ACD domain 0 register region (if ACD programming required) >> + - description: PLL ACD domain 1 register region (if ACD programming required) >> + >> + reg-names: >> + minItems: 2 >> + maxItems: 6 >> + items: >> + - const: "osm-domain0" >> + - const: "freq-domain0" >> + - const: "osm-domain1" >> + - const: "freq-domain1" >> + - const: "osm-acd0" >> + - const: "osm-acd1" > > Don't need quotes. > Ack >> + >> +else: >> + properties: >> + reg: >> + minItems: 2 >> + maxItems: 3 >> + items: >> + - description: Frequency domain 0 register region >> + - description: Frequency domain 1 register region >> + - description: Frequency domain 2 register region >> + reg-names: >> + minItems: 2 >> + maxItems: 3 >> + items: >> + - const: "freq-domain0" >> + - const: "freq-domain1" >> + - const: "freq-domain2" >> + >> required: >> - compatible >> - reg >> -- >> 2.30.0 >>
** ** NOTE: To "view the full picture", please look at the following ** patch series: ** https://patchwork.kernel.org/project/linux-arm-msm/list/?series=413355 ** This is a subset of that series. ** Changes in v5: - Fixed OPP table API abuse, in conjunction with the CPR3 driver - Some minor cleanups Changes in v4: - Huge patch series has been split for better reviewability, as suggested by Bjorn - Rebased code on top of 266991721c15 ("cpufreq: qcom-hw: enable boost support") Changes in v3: - Fixed a test robot build failure for ARCH=arm - Fixed dt_binding_check YAML doc issues Changes in v2: - Rebased dt-binding on top of Manivannan's patches - Added MSM8998 to cpufreq-dt-platdev blacklist - Implemented dynamic Memory Accelerator corners support, needed by MSM8998 - Implemented ACD programming, needed by MSM8998 Tested on the following smartphones: - Sony Xperia XA2 (SDM630) - Sony Xperia XA2 Ultra (SDM630) - Sony Xperia 10 (SDM630) - Sony Xperia XZ Premium (MSM8998) - F(x)Tec Pro 1 (MSM8998)