| Message ID | cover.1611224800.git.michal.simek@xilinx.com |
|---|---|
| Headers | show |
| Series | arm64: dts: zynqmp: DT updates to match latest drivers | expand |
On 1/21/21 11:26 AM, Michal Simek wrote: > Hi, > > I am sending this series to reflect the latest drivers which have been > merged to mainline kernel. I have boot it on zcu102-rev1.0 and also > zcu104-rev1.0. That's why I have also added DT for this newer revision. > > The series is based on https://github.com/Xilinx/linux-xlnx/tree/zynqmp/dt. > And mio-bank patch requires update in dt-binding which has been posted here > https://lore.kernel.org/r/5fa17dfe4b42abefd84b4cbb7b8bcd4d31398f40.1606914986.git.michal.simek@xilinx.com > > Thanks, > Michal > > Changes in v2: > - Remove reset description for IPs from this patch. IPs will be enabled > separately with DT binding update. > - Change patch subject > > Michal Simek (12): > arm64: dts: zynqmp: Fix u48 si5382 chip on zcu111 > arm64: dts: zynqmp: Add DT description for si5328 for zcu102/zcu106 > arm64: dts: zynqmp: Enable si5341 driver for zcu102/106/111 > arm64: dts: zynqmp: Enable reset controller driver > arm64: dts: zynqmp: Enable phy driver for Sata on zcu102/zcu104/zcu106 > arm64: dts: zynqmp: Add label for zynqmp_ipi > arm64: dts: zynqmp: Add missing mio-bank properties to sdhcis > arm64: dts: zynqmp: Wire arasan nand controller > arm64: dts: zynqmp: Wire zynqmp qspi controller > arm64: dts: zynqmp: Add missing lpd watchdog node > arm64: dts: zynqmp: Add missing iommu IDs > arm64: dts: zynqmp: Add description for zcu104 revC > > arch/arm64/boot/dts/xilinx/Makefile | 1 + > .../arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 12 + > .../boot/dts/xilinx/zynqmp-zcu100-revC.dts | 2 + > .../boot/dts/xilinx/zynqmp-zcu102-revA.dts | 84 +++++- > .../boot/dts/xilinx/zynqmp-zcu104-revA.dts | 29 ++ > .../boot/dts/xilinx/zynqmp-zcu104-revC.dts | 282 ++++++++++++++++++ > .../boot/dts/xilinx/zynqmp-zcu106-revA.dts | 78 +++++ > .../boot/dts/xilinx/zynqmp-zcu111-revA.dts | 59 +++- > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 94 +++++- > 9 files changed, 637 insertions(+), 4 deletions(-) > create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts > Applied all. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
On 1/21/21 11:27 AM, Michal Simek wrote: > Xilinx ZynqMP zcu104 revC and newer board revisions have different i2c > structure compare to revA. The rest of the board is the same from software > perspective. > Also enable DMAs and QSPI. > > Signed-off-by: Michal Simek <michal.simek@xilinx.com> > --- > > Changes in v2: None > > arch/arm64/boot/dts/xilinx/Makefile | 1 + > .../boot/dts/xilinx/zynqmp-zcu104-revC.dts | 282 ++++++++++++++++++ > 2 files changed, 283 insertions(+) > create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts > > diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile > index 60f5443f3ef4..11fb4fd3ebd4 100644 > --- a/arch/arm64/boot/dts/xilinx/Makefile > +++ b/arch/arm64/boot/dts/xilinx/Makefile > @@ -13,5 +13,6 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb > dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb > dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb > dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb > +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revC.dtb > dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu106-revA.dtb > dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu111-revA.dtb > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts > new file mode 100644 > index 000000000000..414f98f1831e > --- /dev/null > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts > @@ -0,0 +1,282 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * dts file for Xilinx ZynqMP ZCU104 > + * > + * (C) Copyright 2017 - 2020, Xilinx, Inc. > + * > + * Michal Simek <michal.simek@xilinx.com> > + */ > + > +/dts-v1/; > + > +#include "zynqmp.dtsi" > +#include "zynqmp-clk-ccf.dtsi" > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/phy/phy.h> > + > +/ { > + model = "ZynqMP ZCU104 RevC"; > + compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; > + > + aliases { > + ethernet0 = &gem3; > + i2c0 = &i2c1; > + mmc0 = &sdhci1; > + rtc0 = &rtc; > + serial0 = &uart0; > + serial1 = &uart1; > + serial2 = &dcc; > + }; > + > + chosen { > + bootargs = "earlycon"; > + stdout-path = "serial0:115200n8"; > + }; > + > + memory@0 { > + device_type = "memory"; > + reg = <0x0 0x0 0x0 0x80000000>; > + }; > + > + ina226 { > + compatible = "iio-hwmon"; > + io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>; > + }; > + > + clock_8t49n287_5: clk125 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <125000000>; > + }; > + > + clock_8t49n287_2: clk26 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <26000000>; > + }; > + > + clock_8t49n287_3: clk27 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <27000000>; > + }; > +}; > + > +&can1 { > + status = "okay"; > +}; > + > +&dcc { > + status = "okay"; > +}; > + > +&fpd_dma_chan1 { > + status = "okay"; > +}; > + > +&fpd_dma_chan2 { > + status = "okay"; > +}; > + > +&fpd_dma_chan3 { > + status = "okay"; > +}; > + > +&fpd_dma_chan4 { > + status = "okay"; > +}; > + > +&fpd_dma_chan5 { > + status = "okay"; > +}; > + > +&fpd_dma_chan6 { > + status = "okay"; > +}; > + > +&fpd_dma_chan7 { > + status = "okay"; > +}; > + > +&fpd_dma_chan8 { > + status = "okay"; > +}; > + > +&gem3 { > + status = "okay"; > + phy-handle = <&phy0>; > + phy-mode = "rgmii-id"; > + phy0: ethernet-phy@c { > + reg = <0xc>; > + ti,rx-internal-delay = <0x8>; > + ti,tx-internal-delay = <0xa>; > + ti,fifo-depth = <0x1>; > + ti,dp83867-rxctrl-strap-quirk; > + }; > +}; > + > +&gpio { > + status = "okay"; > +}; > + > +&i2c1 { > + status = "okay"; > + clock-frequency = <400000>; > + > + tca6416_u97: gpio@20 { > + compatible = "ti,tca6416"; > + reg = <0x20>; > + gpio-controller; > + #gpio-cells = <2>; > + /* > + * IRQ not connected > + * Lines: > + * 0 - IRPS5401_ALERT_B > + * 1 - HDMI_8T49N241_INT_ALM > + * 2 - MAX6643_OT_B > + * 3 - MAX6643_FANFAIL_B > + * 5 - IIC_MUX_RESET_B > + * 6 - GEM3_EXP_RESET_B > + * 7 - FMC_LPC_PRSNT_M2C_B > + * 4, 10 - 17 - not connected > + */ > + }; > + > + /* Another connection to this bus via PL i2c via PCA9306 - u45 */ > + i2c-mux@74 { /* u34 */ > + compatible = "nxp,pca9548"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x74>; > + i2c@0 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0>; > + /* > + * IIC_EEPROM 1kB memory which uses 256B blocks > + * where every block has different address. > + * 0 - 256B address 0x54 > + * 256B - 512B address 0x55 > + * 512B - 768B address 0x56 > + * 768B - 1024B address 0x57 > + */ > + eeprom: eeprom@54 { /* u23 */ > + compatible = "atmel,24c08"; > + reg = <0x54>; > + #address-cells = <1>; > + #size-cells = <1>; > + }; > + }; > + > + i2c@1 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <1>; > + clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ > + reg = <0x6c>; > + }; > + }; > + > + i2c@2 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <2>; > + irps5401_43: irps5401@43 { /* IRPS5401 - u175 */ > + compatible = "infineon,irps5401"; > + reg = <0x43>; /* pmbus / i2c 0x13 */ > + }; > + irps5401_44: irps5401@44 { /* IRPS5401 - u180 */ > + compatible = "infineon,irps5401"; > + reg = <0x44>; /* pmbus / i2c 0x14 */ > + }; > + }; > + > + i2c@3 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <3>; > + u183: ina226@40 { /* u183 */ > + compatible = "ti,ina226"; > + #io-channel-cells = <1>; > + reg = <0x40>; > + shunt-resistor = <5000>; > + }; > + }; > + > + i2c@5 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <5>; > + }; > + > + i2c@7 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <7>; > + }; > + > + /* 4, 6 not connected */ > + }; > +}; > + > +&qspi { > + status = "okay"; > + flash@0 { > + compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x0>; > + }; > +}; > + > +&rtc { > + status = "okay"; > +}; > + > +&psgtr { > + status = "okay"; > + /* nc, sata, usb3, dp */ > + clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; > + clock-names = "ref1", "ref2", "ref3"; > +}; > + > +&sata { > + status = "okay"; > + /* SATA OOB timing settings */ > + ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; > + ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; > + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; > + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; > + ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; > + ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; > + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; > + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; > + phy-names = "sata-phy"; > + phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; > +}; > + > +/* SD1 with level shifter */ > +&sdhci1 { > + status = "okay"; > + no-1-8-v; > + xlnx,mio-bank = <1>; > + disable-wp; > +}; > + > +&uart0 { > + status = "okay"; > +}; > + > +&uart1 { > + status = "okay"; > +}; > + > +/* ULPI SMSC USB3320 */ > +&usb0 { > + status = "okay"; > + dr_mode = "host"; > +}; > + > +&watchdog0 { > + status = "okay"; > +}; > As I said I applied this but also added revC to Documentation/devicetree/bindings/arm/xilinx.yaml to be listed. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs