| Message ID | 1611747815-1934-11-git-send-email-stefanc@marvell.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v4,net-next,01/19] doc: marvell: add cm3-mem device tree bindings description | expand |
> > > From: Stefan Chulski <stefanc@marvell.com> > > > > RXQ non occupied descriptor threshold would be used by Flow Control > > Firmware feature to move to the XOFF mode. > > RXQ non occupied threshold would change interrupt cause that polled by > > CM3 Firmware. > > Actual non occupied interrupt masked and won't trigger interrupt. > > Does this mean that this change enables a feature, but it is unused due to a > masked interrupt? Firmware poll RXQ non occupied cause register to indicate if number of registers bellow threshold. We do not trigger any interrupt, just poll this bit in CM3. So this cause always masked. > > > > Signed-off-by: Stefan Chulski <stefanc@marvell.com> > > --- > > drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 3 ++ > > drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 46 > > +++++++++++++++++--- > > 2 files changed, 42 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h > > b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h > > index 73f087c..9d8993f 100644 > > --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h > > +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h > > @@ -295,6 +295,8 @@ > > #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK > 0x3fc00000 > > #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31) > > #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0 > > +#define MVPP2_ISR_RX_ERR_CAUSE_REG(port) (0x5520 + 4 * (port)) > > +#define MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK 0x00ff > > The indentation in this file is inconsistent. Here even between the two newly > introduced lines. Ok, I would fix this. > > /* If the thread isn't used, don't do anything */ > > - if (smp_processor_id() > port->priv->nthreads) > > + if (cpu >= port->priv->nthreads) > > return; > > Here and below, the change from greater than to greater than is really a > (standalone) fix? Ok, I would move this to separate patch. > > +/* Routine set the number of non-occupied descriptors threshold that > > +change > > + * interrupt error cause polled by FW Flow Control */ > > nit: no need for "Routine". Also, does "change .. cause" mean "that triggers > an interrupt"? Ok. Thanks, Stefan.
On Wed, Jan 27, 2021 at 06:41:32PM +0000, Stefan Chulski wrote: > > > > > > From: Stefan Chulski <stefanc@marvell.com> > > > > > > RXQ non occupied descriptor threshold would be used by Flow Control > > > Firmware feature to move to the XOFF mode. > > > RXQ non occupied threshold would change interrupt cause that polled by > > > CM3 Firmware. > > > Actual non occupied interrupt masked and won't trigger interrupt. > > > > Does this mean that this change enables a feature, but it is unused due to a > > masked interrupt? > > Firmware poll RXQ non occupied cause register to indicate if number of registers bellow threshold. > We do not trigger any interrupt, just poll this bit in CM3. So this cause always masked. The functional spec for A8040 says that the register at 0xF2005520 is "RX Exceptions Interrupt Mask" and the bit description talks about it controlling interrupt signal generation. However, the bit that allows RX Exceptions to be raised in MVPP2_ISR_RX_TX_MASK_REG is clear, so it won't proceed beyond the next level up. So, I think the commit description needs to say something like: "The firmware needs to monitor the RX Non-occupied descriptor bits for flow control to move to XOFF mode. These bits need to be unmasked to be functional, but they will not raise interrupts as we leave the RX exception summary bit in MVPP2_ISR_RX_TX_MASK_REG clear." I think that's essentially what you're trying to describe - please change if not. -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h index 73f087c..9d8993f 100644 --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h @@ -295,6 +295,8 @@ #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000 #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31) #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0 +#define MVPP2_ISR_RX_ERR_CAUSE_REG(port) (0x5520 + 4 * (port)) +#define MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK 0x00ff /* Buffer Manager registers */ #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4)) @@ -764,6 +766,7 @@ #define MSS_SRAM_SIZE 0x800 #define FC_QUANTA 0xFFFF #define FC_CLK_DIVIDER 100 +#define MSS_THRESHOLD_STOP 768 /* RX buffer constants */ #define MVPP2_SKB_SHINFO_SIZE \ diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c index 8f40293a..a4933c4 100644 --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c @@ -1144,14 +1144,19 @@ static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec) static void mvpp2_interrupts_mask(void *arg) { struct mvpp2_port *port = arg; + int cpu = smp_processor_id(); + u32 thread; /* If the thread isn't used, don't do anything */ - if (smp_processor_id() > port->priv->nthreads) + if (cpu >= port->priv->nthreads) return; - mvpp2_thread_write(port->priv, - mvpp2_cpu_to_thread(port->priv, smp_processor_id()), + thread = mvpp2_cpu_to_thread(port->priv, cpu); + + mvpp2_thread_write(port->priv, thread, MVPP2_ISR_RX_TX_MASK_REG(port->id), 0); + mvpp2_thread_write(port->priv, thread, + MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), 0); } /* Unmask the current thread's Rx/Tx interrupts. @@ -1161,20 +1166,25 @@ static void mvpp2_interrupts_mask(void *arg) static void mvpp2_interrupts_unmask(void *arg) { struct mvpp2_port *port = arg; - u32 val; + int cpu = smp_processor_id(); + u32 val, thread; /* If the thread isn't used, don't do anything */ - if (smp_processor_id() > port->priv->nthreads) + if (cpu >= port->priv->nthreads) return; + thread = mvpp2_cpu_to_thread(port->priv, cpu); + val = MVPP2_CAUSE_MISC_SUM_MASK | MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version); if (port->has_tx_irqs) val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; - mvpp2_thread_write(port->priv, - mvpp2_cpu_to_thread(port->priv, smp_processor_id()), + mvpp2_thread_write(port->priv, thread, MVPP2_ISR_RX_TX_MASK_REG(port->id), val); + mvpp2_thread_write(port->priv, thread, + MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), + MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK); } static void @@ -1199,6 +1209,9 @@ static void mvpp2_interrupts_unmask(void *arg) mvpp2_thread_write(port->priv, v->sw_thread_id, MVPP2_ISR_RX_TX_MASK_REG(port->id), val); + mvpp2_thread_write(port->priv, v->sw_thread_id, + MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), + MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK); } } @@ -2404,6 +2417,22 @@ static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port) } } +/* Routine set the number of non-occupied descriptors threshold that change + * interrupt error cause polled by FW Flow Control + */ +static void mvpp2_set_rxq_free_tresh(struct mvpp2_port *port, + struct mvpp2_rx_queue *rxq) +{ + u32 val; + + mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id); + + val = mvpp2_read(port->priv, MVPP2_RXQ_THRESH_REG); + val &= ~MVPP2_RXQ_NON_OCCUPIED_MASK; + val |= MSS_THRESHOLD_STOP << MVPP2_RXQ_NON_OCCUPIED_OFFSET; + mvpp2_write(port->priv, MVPP2_RXQ_THRESH_REG, val); +} + /* Set the number of packets that will be received before Rx interrupt * will be generated by HW. */ @@ -2659,6 +2688,9 @@ static int mvpp2_rxq_init(struct mvpp2_port *port, mvpp2_rx_pkts_coal_set(port, rxq); mvpp2_rx_time_coal_set(port, rxq); + /* Set the number of non occupied descriptors threshold */ + mvpp2_set_rxq_free_tresh(port, rxq); + /* Add number of descriptors ready for receiving packets */ mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);