| Message ID | 20210126110826.24221-1-alexandru.ardelean@analog.com |
|---|---|
| Headers | show |
| Series | clk: clk-axiclgen: add support for ZynqMP | expand |
On 1/26/21 3:08 AM, Alexandru Ardelean wrote: > Previous set: > https://lore.kernel.org/linux-clk/20201221144224.50814-1-alexandru.ardelean@analog.com/ > > Changelog v1 -> v2: > * split patch 'clk: axi-clkgen: add support for ZynqMP (UltraScale)' > into: > - clk: axi-clkgen: remove ARCH dependency in Kconfig > - clk: clk-axiclkgen: add ZynqMP PFD and VCO limits > * essentially removed the 'adi,zynq-axi-clkgen-2.00.a' compat string > * removed architecture dependency on build for driver; the driver should > be usable also on PCIe setups > > Alexandru Ardelean (3): > clk: axi-clkgen: remove ARCH dependency in Kconfig > clk: clk-axiclkgen: add ZynqMP PFD and VCO limits > dt-bindings: clock: adi,axi-clkgen: add compatible string for ZynqMP > support > > .../devicetree/bindings/clock/adi,axi-clkgen.yaml | 1 + > drivers/clk/Kconfig | 1 - > drivers/clk/clk-axi-clkgen.c | 11 +++++++++++ > 3 files changed, 12 insertions(+), 1 deletion(-) This whole set looks fine. Reviewed-by: Tom Rix <trix@redhat.com>
Alexandru, On Tue, Jan 26, 2021 at 01:08:24PM +0200, Alexandru Ardelean wrote: > The intent is to be able to run this driver to access the IP core in setups > where FPGA board is also connected via a PCIe bus. In such cases the number > of combinations explodes, where the host system can be an x86 with Xilinx > Zynq/ZynqMP/Microblaze board connected via PCIe. > Or even a ZynqMP board with a ZynqMP/Zynq/Microblaze connected via PCIe. > > To accommodate for these cases, this change removes the limitation for this > driver to be compilable only on Zynq/Microblaze architectures. > > Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com> > Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> > --- > drivers/clk/Kconfig | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig > index 85856cff506c..d8c2d4593926 100644 > --- a/drivers/clk/Kconfig > +++ b/drivers/clk/Kconfig > @@ -247,7 +247,6 @@ config CLK_TWL6040 > > config COMMON_CLK_AXI_CLKGEN > tristate "AXI clkgen driver" > - depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST Umhhh ... no dependencies? How are you accessing your registers? You seem to be using device tree, probably: depends on HAS_IOMEM || COMPILE_TEST depends on OF at least? Please double check your dependencies. > help > Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx > FPGAs. It is commonly used in Analog Devices' reference designs. > -- > 2.17.1 > - Moritz
> -----Original Message----- > From: Moritz Fischer <mdf@kernel.org> > Sent: Wednesday, January 27, 2021 4:39 AM > To: Ardelean, Alexandru <alexandru.Ardelean@analog.com> > Cc: linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux- > kernel@vger.kernel.org; mturquette@baylibre.com; sboyd@kernel.org; > robh+dt@kernel.org; lars@metafoo.de; linux-fpga@vger.kernel.org; > mdf@kernel.org; Bogdan, Dragos <Dragos.Bogdan@analog.com> > Subject: Re: [PATCH v2 1/3] clk: axi-clkgen: remove ARCH dependency in Kconfig > > Alexandru, > > On Tue, Jan 26, 2021 at 01:08:24PM +0200, Alexandru Ardelean wrote: > > The intent is to be able to run this driver to access the IP core in > > setups where FPGA board is also connected via a PCIe bus. In such > > cases the number of combinations explodes, where the host system can > > be an x86 with Xilinx Zynq/ZynqMP/Microblaze board connected via PCIe. > > Or even a ZynqMP board with a ZynqMP/Zynq/Microblaze connected via PCIe. > > > > To accommodate for these cases, this change removes the limitation for > > this driver to be compilable only on Zynq/Microblaze architectures. > > > > Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com> > > Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> > > --- > > drivers/clk/Kconfig | 1 - > > 1 file changed, 1 deletion(-) > > > > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index > > 85856cff506c..d8c2d4593926 100644 > > --- a/drivers/clk/Kconfig > > +++ b/drivers/clk/Kconfig > > @@ -247,7 +247,6 @@ config CLK_TWL6040 > > > > config COMMON_CLK_AXI_CLKGEN > > tristate "AXI clkgen driver" > > - depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST > Umhhh ... no dependencies? How are you accessing your registers? You seem to > be using device tree, probably: > > depends on HAS_IOMEM || COMPILE_TEST > depends on OF > > at least? Please double check your dependencies. Agreed. Will re-spin. This is a n00b mistake on my part Thanks > > help > > Support for the Analog Devices axi-clkgen pcore clock generator for > Xilinx > > FPGAs. It is commonly used in Analog Devices' reference designs. > > -- > > 2.17.1 > > > > - Moritz
Previous set: https://lore.kernel.org/linux-clk/20201221144224.50814-1-alexandru.ardelean@analog.com/ Changelog v1 -> v2: * split patch 'clk: axi-clkgen: add support for ZynqMP (UltraScale)' into: - clk: axi-clkgen: remove ARCH dependency in Kconfig - clk: clk-axiclkgen: add ZynqMP PFD and VCO limits * essentially removed the 'adi,zynq-axi-clkgen-2.00.a' compat string * removed architecture dependency on build for driver; the driver should be usable also on PCIe setups Alexandru Ardelean (3): clk: axi-clkgen: remove ARCH dependency in Kconfig clk: clk-axiclkgen: add ZynqMP PFD and VCO limits dt-bindings: clock: adi,axi-clkgen: add compatible string for ZynqMP support .../devicetree/bindings/clock/adi,axi-clkgen.yaml | 1 + drivers/clk/Kconfig | 1 - drivers/clk/clk-axi-clkgen.c | 11 +++++++++++ 3 files changed, 12 insertions(+), 1 deletion(-)