diff mbox

[1/6] arm/imx6q: add device tree source

Message ID 1315303120-24203-2-git-send-email-shawn.guo@linaro.org
State New
Headers show

Commit Message

Shawn Guo Sept. 6, 2011, 9:58 a.m. UTC 
It adds device tree source and documentation for imx6q platform.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
 Documentation/devicetree/bindings/arm/fsl.txt |    6 +
 arch/arm/boot/dts/imx6q-sabreauto.dts         |   49 +++
 arch/arm/boot/dts/imx6q.dtsi                  |  570 +++++++++++++++++++++++++
 3 files changed, 625 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/fsl.txt
 create mode 100644 arch/arm/boot/dts/imx6q-sabreauto.dts
 create mode 100644 arch/arm/boot/dts/imx6q.dtsi

Comments

Arnd Bergmann Sept. 6, 2011, 6:31 p.m. UTC | #1 
On Tuesday 06 September 2011 17:58:35 Shawn Guo wrote:
> +
> +       aips-bus@02000000 { /* AIPS1 */
> +               compatible = "fsl,aips-bus", "simple-bus";
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +               reg = <0x02000000 0x100000>;
> +               ranges;
> +
> +               spba-bus@02000000 {
> +                       compatible = "fsl,spba-bus", "simple-bus";
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       reg = <0x02000000 0x40000>;
> +                       ranges;

Wouldn't it be better to have the ranges property translate bus-local addresses
to global addresses, rather than having an empty ranges property?

	Arnd
Shawn Guo Sept. 7, 2011, 11:16 a.m. UTC | #2 
On Tue, Sep 06, 2011 at 08:31:47PM +0200, Arnd Bergmann wrote:
> On Tuesday 06 September 2011 17:58:35 Shawn Guo wrote:
> > +
> > +       aips-bus@02000000 { /* AIPS1 */
> > +               compatible = "fsl,aips-bus", "simple-bus";
> > +               #address-cells = <1>;
> > +               #size-cells = <1>;
> > +               reg = <0x02000000 0x100000>;
> > +               ranges;
> > +
> > +               spba-bus@02000000 {
> > +                       compatible = "fsl,spba-bus", "simple-bus";
> > +                       #address-cells = <1>;
> > +                       #size-cells = <1>;
> > +                       reg = <0x02000000 0x40000>;
> > +                       ranges;
> 
> Wouldn't it be better to have the ranges property translate bus-local addresses
> to global addresses, rather than having an empty ranges property?
> 
All the bus-local addresses are directly mapped into cpu address
space.  Looking at the i.MX Reference Manual memory map chapter,
the base address of each block is given in global address other than
bus address + offset.  Writing a global address in device tree is
relatively easy to match the addresses defined in hardware document.
diff mbox

Patch

diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
new file mode 100644
index 0000000..345bfc0
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -0,0 +1,6 @@ 
+Freescale i.MX Platforms Device Tree Bindings
+-----------------------------------------------
+
+i.MX6 Quad SABRE Automotive Board
+Required root node properties:
+    - compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts
new file mode 100644
index 0000000..2b31ecb
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-sabreauto.dts
@@ -0,0 +1,49 @@ 
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "imx6q.dtsi"
+
+/ {
+	model = "Freescale i.MX6 Quad SABRE Automotive Board";
+	compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
+
+	chosen {
+		bootargs = "console=ttymxc3,115200 root=/dev/mmcblk3p3 rootwait";
+	};
+
+	memory {
+		reg = <0x10000000 0x80000000>;
+	};
+
+	aips-bus@02100000 { /* AIPS2 */
+		enet@02188000 {
+			phy-mode = "rgmii";
+			local-mac-address = [00 04 9F 01 1B 61];
+			status = "okay";
+		};
+
+		uart3: uart@021f0000 { /* UART4 */
+			status = "okay";
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		debug-led {
+			label = "Heartbeat";
+			gpios = <&gpio2 25 0>; /* GPIO3_25 */
+			linux,default-trigger = "heartbeat";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
new file mode 100644
index 0000000..7864ee9
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -0,0 +1,570 @@ 
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	interrupt-parent = <&intc>;
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+		serial4 = &uart4;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "arm,cortex-a9";
+			reg = <0>;
+			next-level-cache = <&L2>;
+		};
+
+		cpu@1 {
+			compatible = "arm,cortex-a9";
+			reg = <1>;
+			next-level-cache = <&L2>;
+		};
+
+		cpu@2 {
+			compatible = "arm,cortex-a9";
+			reg = <2>;
+			next-level-cache = <&L2>;
+		};
+
+		cpu@3 {
+			compatible = "arm,cortex-a9";
+			reg = <3>;
+			next-level-cache = <&L2>;
+		};
+	};
+
+	intc: interrupt-controller@00a01000 {
+		compatible = "arm,cortex-a9-gic";
+		#interrupt-cells = <2>;
+		#size-cells = <0>;
+		#address-cells = <1>;
+		interrupt-controller;
+		reg = <0x00a01000 0x1000>,
+		      <0x00a00100 0x100>;
+
+		gicppi0: gic-ppi@0 {
+			compatible = "arm,cortex-a9-gic-ppi";
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			reg = <0>;
+		};
+
+		gicppi1: gic-ppi@1 {
+			compatible = "arm,cortex-a9-gic-ppi";
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			reg = <1>;
+
+		};
+		gicppi2: gic-ppi@2 {
+			compatible = "arm,cortex-a9-gic-ppi";
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			reg = <2>;
+		};
+
+		gicppi3: gic-ppi@3 {
+			compatible = "arm,cortex-a9-gic-ppi";
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			reg = <3>;
+		};
+	};
+
+	timer@00a00600 {
+		compatible = "arm,smp-twd";
+		reg = <0x00a00600 0x100>;
+		interrupt-parent = <&gicppi0>;
+		interrupts = <29>;
+	};
+
+	L2: l2-cache@00a02000 {
+		compatible = "arm,pl310-cache";
+		reg = <0x00a02000 0x1000>;
+		interrupts = <124 4>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
+	aips-bus@02000000 { /* AIPS1 */
+		compatible = "fsl,aips-bus", "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x02000000 0x100000>;
+		ranges;
+
+		spba-bus@02000000 {
+			compatible = "fsl,spba-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x02000000 0x40000>;
+			ranges;
+
+			spdif@02004000 {
+				reg = <0x02004000 0x4000>;
+				interrupts = <84 4>;
+			};
+
+			ecspi@02008000 { /* eCSPI1 */
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
+				reg = <0x02008000 0x4000>;
+				interrupts = <63 4>;
+				status = "disabled";
+			};
+
+			ecspi@0200c000 { /* eCSPI2 */
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
+				reg = <0x0200c000 0x4000>;
+				interrupts = <64 4>;
+				status = "disabled";
+			};
+
+			ecspi@02010000 { /* eCSPI3 */
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
+				reg = <0x02010000 0x4000>;
+				interrupts = <65 4>;
+				status = "disabled";
+			};
+
+			ecspi@02014000 { /* eCSPI4 */
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
+				reg = <0x02014000 0x4000>;
+				interrupts = <66 4>;
+				status = "disabled";
+			};
+
+			ecspi@02018000 { /* eCSPI5 */
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
+				reg = <0x02018000 0x4000>;
+				interrupts = <67 4>;
+				status = "disabled";
+			};
+
+			uart0: uart@02020000 { /* UART1 */
+				compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+				reg = <0x02020000 0x4000>;
+				interrupts = <58 4>;
+				status = "disabled";
+			};
+
+			esai@02024000 {
+				reg = <0x02024000 0x4000>;
+				interrupts = <83 4>;
+			};
+
+			ssi@02028000 { /* SSI1 */
+				reg = <0x02028000 0x4000>;
+				interrupts = <78 4>;
+			};
+
+			ssi@0202c000 { /* SSI2 */
+				reg = <0x0202c000 0x4000>;
+				interrupts = <79 4>;
+			};
+
+			ssi@02030000 { /* SSI3 */
+				reg = <0x02030000 0x4000>;
+				interrupts = <80 4>;
+			};
+
+			asrc@02034000 {
+				reg = <0x02034000 0x4000>;
+				interrupts = <82 4>;
+			};
+
+			spba@0203c000 {
+				reg = <0x0203c000 0x4000>;
+			};
+		};
+
+		vpu@02040000 {
+			reg = <0x02040000 0x3c000>;
+			interrupts = <35 4 44 4>;
+		};
+
+		aipstz@0207c000 { /* AIPSTZ1 */
+			reg = <0x0207c000 0x4000>;
+		};
+
+		pwm@02080000 { /* PWM1 */
+			reg = <0x02080000 0x4000>;
+			interrupts = <115 4>;
+		};
+
+		pwm@02084000 { /* PWM2 */
+			reg = <0x02084000 0x4000>;
+			interrupts = <116 4>;
+		};
+
+		pwm@02088000 { /* PWM3 */
+			reg = <0x02088000 0x4000>;
+			interrupts = <117 4>;
+		};
+
+		pwm@0208c000 { /* PWM4 */
+			reg = <0x0208c000 0x4000>;
+			interrupts = <118 4>;
+		};
+
+		flexcan@02090000 { /* CAN1 */
+			reg = <0x02090000 0x4000>;
+			interrupts = <142 4>;
+		};
+
+		flexcan@02094000 { /* CAN2 */
+			reg = <0x02094000 0x4000>;
+			interrupts = <143 4>;
+		};
+
+		gpt@02098000 {
+			compatible = "fsl,imx6q-gpt";
+			reg = <0x02098000 0x4000>;
+			interrupts = <87 4>;
+		};
+
+		gpio0: gpio@0209c000 { /* GPIO1 */
+			compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
+			reg = <0x0209c000 0x4000>;
+			interrupts = <98 4 99 4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+		};
+
+		gpio1: gpio@020a0000 { /* GPIO2 */
+			compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
+			reg = <0x020a0000 0x4000>;
+			interrupts = <100 4 101 4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+		};
+
+		gpio2: gpio@020a4000 { /* GPIO3 */
+			compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
+			reg = <0x020a4000 0x4000>;
+			interrupts = <102 4 103 4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+		};
+
+		gpio3: gpio@020a8000 { /* GPIO4 */
+			compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
+			reg = <0x020a8000 0x4000>;
+			interrupts = <104 4 105 4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+		};
+
+		gpio4: gpio@020ac000 { /* GPIO5 */
+			compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
+			reg = <0x020ac000 0x4000>;
+			interrupts = <106 4 107 4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+		};
+
+		gpio5: gpio@020b0000 { /* GPIO6 */
+			compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
+			reg = <0x020b0000 0x4000>;
+			interrupts = <108 4 109 4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+		};
+
+		gpio6: gpio@020b4000 { /* GPIO7 */
+			compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
+			reg = <0x020b4000 0x4000>;
+			interrupts = <110 4 111 4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+		};
+
+		kpp@020b8000 {
+			reg = <0x020b8000 0x4000>;
+			interrupts = <114 4>;
+		};
+
+		wdog@020bc000 { /* WDOG1 */
+			compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
+			reg = <0x020bc000 0x4000>;
+			interrupts = <112 4>;
+			status = "disabled";
+		};
+
+		wdog@020c0000 { /* WDOG2 */
+			compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
+			reg = <0x020c0000 0x4000>;
+			interrupts = <113 4>;
+			status = "disabled";
+		};
+
+		ccm@020c4000 {
+			compatible = "fsl,imx6q-ccm";
+			reg = <0x020c4000 0x4000>;
+			interrupts = <119 4 120 4>;
+		};
+
+		anatop@020c8000 {
+			compatible = "fsl,imx6q-anatop";
+			reg = <0x020c8000 0x1000>;
+			interrupts = <81 4 86 4 159 4>;
+		};
+
+		usbphy@020c9000 { /* USBPHY1 */
+			reg = <0x020c9000 0x1000>;
+			interrupts = <76 4>;
+		};
+
+		usbphy@020ca000 { /* USBPHY2 */
+			reg = <0x020ca000 0x1000>;
+			interrupts = <77 4>;
+		};
+
+		snvs@020cc000 {
+			reg = <0x020cc000 0x4000>;
+			interrupts = <51 4 52 4>;
+		};
+
+		epit@020d0000 { /* EPIT1 */
+			reg = <0x020d0000 0x4000>;
+			interrupts = <88 4>;
+		};
+
+		epit@020d4000 { /* EPIT2 */
+			reg = <0x020d4000 0x4000>;
+			interrupts = <89 4>;
+		};
+
+		src@020d8000 {
+			compatible = "fsl,imx6q-src";
+			reg = <0x020d8000 0x4000>;
+			interrupts = <123 4 128 4>;
+		};
+
+		gpc@020dc000 {
+			compatible = "fsl,imx6q-gpc";
+			reg = <0x020dc000 0x4000>;
+			interrupts = <121 4 122 4>;
+		};
+
+		iomuxc@020e0000 {
+			reg = <0x020e0000 0x4000>;
+		};
+
+		dcic@020e4000 { /* DCIC1 */
+			reg = <0x020e4000 0x4000>;
+			interrupts = <156 4>;
+		};
+
+		dcic@020e8000 { /* DCIC2 */
+			reg = <0x020e8000 0x4000>;
+			interrupts = <157 4>;
+		};
+
+		sdma@020ec000 {
+			compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
+			reg = <0x020ec000 0x4000>;
+			interrupts = <34 4>;
+		};
+	};
+
+	aips-bus@02100000 { /* AIPS2 */
+		compatible = "fsl,aips-bus", "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x02100000 0x100000>;
+		ranges;
+
+		caam@02100000 {
+			reg = <0x02100000 0x40000>;
+			interrupts = <137 4 138 4>;
+		};
+
+		aipstz@0217c000 { /* AIPSTZ2 */
+			reg = <0x0217c000 0x4000>;
+		};
+
+		enet@02188000 {
+			compatible = "fsl,imx6q-fec";
+			reg = <0x02188000 0x4000>;
+			interrupts = <150 4 151 4>;
+			status = "disabled";
+		};
+
+		mlb@0218c000 {
+			reg = <0x0218c000 0x4000>;
+			interrupts = <85 4 149 4 158 4>;
+		};
+
+		usdhc@02190000 { /* uSDHC1 */
+			reg = <0x02190000 0x4000>;
+			interrupts = <54 4>;
+		};
+
+		usdhc@02194000 { /* uSDHC2 */
+			reg = <0x02194000 0x4000>;
+			interrupts = <55 4>;
+		};
+
+		usdhc@02198000 { /* uSDHC3 */
+			reg = <0x02198000 0x4000>;
+			interrupts = <56 4>;
+		};
+
+		usdhc@0219c000 { /* uSDHC4 */
+			reg = <0x0219c000 0x4000>;
+			interrupts = <57 4>;
+		};
+
+		i2c@021a0000 { /* I2C1 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
+			reg = <0x021a0000 0x4000>;
+			interrupts = <68 4>;
+			status = "disabled";
+		};
+
+		i2c@021a4000 { /* I2C2 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
+			reg = <0x021a4000 0x4000>;
+			interrupts = <69 4>;
+			status = "disabled";
+		};
+
+		i2c@021a8000 { /* I2C3 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
+			reg = <0x021a8000 0x4000>;
+			interrupts = <70 4>;
+			status = "disabled";
+		};
+
+		romcp@021ac000 {
+			reg = <0x021ac000 0x4000>;
+		};
+
+		mmdc@021b0000 { /* MMDC0 */
+			compatible = "fsl,imx6q-mmdc";
+			reg = <0x021b0000 0x4000>;
+		};
+
+		mmdc@021b4000 { /* MMDC1 */
+			reg = <0x021b4000 0x4000>;
+		};
+
+		weim@021b8000 {
+			reg = <0x021b8000 0x4000>;
+			interrupts = <46 4>;
+		};
+
+		ocotp@021bc000 {
+			reg = <0x021bc000 0x4000>;
+		};
+
+		ocotp@021c0000 {
+			reg = <0x021c0000 0x4000>;
+			interrupts = <53 4>;
+		};
+
+		tzasc@021d0000 { /* TZASC1 */
+			reg = <0x021d0000 0x4000>;
+			interrupts = <140 4>;
+		};
+
+		tzasc@021d4000 { /* TZASC2 */
+			reg = <0x021d4000 0x4000>;
+			interrupts = <141 4>;
+		};
+
+		audmux@021d8000 {
+			reg = <0x021d8000 0x4000>;
+		};
+
+		mipi@021dc000 { /* MIPI-CSI */
+			reg = <0x021dc000 0x4000>;
+		};
+
+		mipi@021e0000 { /* MIPI-DSI */
+			reg = <0x021e0000 0x4000>;
+		};
+
+		vdoa@021e4000 {
+			reg = <0x021e4000 0x4000>;
+			interrupts = <50 4>;
+		};
+
+		uart1: uart@021e8000 { /* UART2 */
+			compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+			reg = <0x021e8000 0x4000>;
+			interrupts = <59 4>;
+			status = "disabled";
+		};
+
+		uart2: uart@021ec000 { /* UART3 */
+			compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+			reg = <0x021ec000 0x4000>;
+			interrupts = <60 4>;
+			status = "disabled";
+		};
+
+		uart3: uart@021f0000 { /* UART4 */
+			compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+			reg = <0x021f0000 0x4000>;
+			interrupts = <61 4>;
+			status = "disabled";
+		};
+
+		uart4: uart@021f4000 { /* UART5 */
+			compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+			reg = <0x021f4000 0x4000>;
+			interrupts = <62 4>;
+			status = "disabled";
+		};
+	};
+};