| Message ID | 20210111113010.32056-2-manivannan.sadhasivam@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | Add support for USB3 PHY on SDX55 | expand |
On Mon, 11 Jan 2021 17:00:09 +0530, Manivannan Sadhasivam wrote: > Add devicetree YAML binding for Qualcomm QMP Super Speed (SS) PHY found > in SDX55. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 27 +++++++++++++++++++ > 1 file changed, 27 insertions(+) > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml index ec05db374645..0f00d82461fd 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml @@ -34,6 +34,7 @@ properties: - qcom,sm8250-qmp-gen3x1-pcie-phy - qcom,sm8250-qmp-gen3x2-pcie-phy - qcom,sm8250-qmp-modem-pcie-phy + - qcom,sdx55-qmp-usb3-uni-phy reg: items: @@ -131,6 +132,32 @@ allOf: items: - const: phy - const: common + - if: + properties: + compatible: + contains: + enum: + - qcom,sdx55-qmp-usb3-uni-phy + then: + properties: + clocks: + items: + - description: Phy aux clock. + - description: Phy config clock. + - description: 19.2 MHz ref clk. + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: ref + resets: + items: + - description: reset of phy block. + - description: phy common block reset. + reset-names: + items: + - const: phy + - const: common - if: properties: compatible:
Add devicetree YAML binding for Qualcomm QMP Super Speed (SS) PHY found in SDX55. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) -- 2.25.1