| Message ID | 20201223060204.576856-19-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | tcg: backend constraints cleanup | expand |
On Tue, Dec 22, 2020 at 10:23 PM Richard Henderson <richard.henderson@linaro.org> wrote: > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > tcg/riscv/tcg-target-conset.h | 25 +++++++++++ > tcg/riscv/tcg-target.h | 1 + > tcg/riscv/tcg-target.c.inc | 83 ++++++++++------------------------- > 3 files changed, 49 insertions(+), 60 deletions(-) > create mode 100644 tcg/riscv/tcg-target-conset.h > > diff --git a/tcg/riscv/tcg-target-conset.h b/tcg/riscv/tcg-target-conset.h > new file mode 100644 > index 0000000000..116dd75db2 > --- /dev/null > +++ b/tcg/riscv/tcg-target-conset.h > @@ -0,0 +1,25 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * RISC-V target-specific constaint sets. > + * Copyright (c) 2020 Linaro > + */ > + > +C_O0_I1(r) > +C_O0_I2(LZ, L) > +C_O0_I2(rZ, r) > +C_O0_I2(rZ, rZ) > +C_O0_I3(LZ, L, L) > +C_O0_I3(LZ, LZ, L) > +C_O0_I4(LZ, LZ, L, L) > +C_O0_I4(rZ, rZ, rZ, rZ) > +C_O1_I1(r, L) > +C_O1_I1(r, r) > +C_O1_I2(r, L, L) > +C_O1_I2(r, r, ri) > +C_O1_I2(r, r, rI) > +C_O1_I2(r, rZ, rN) > +C_O1_I2(r, rZ, rZ) > +C_O1_I4(r, rZ, rZ, rZ, rZ) > +C_O2_I1(r, r, L) > +C_O2_I2(r, r, L, L) > +C_O2_I4(r, r, rZ, rZ, rM, rM) > diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h > index 032439d806..a357962e01 100644 > --- a/tcg/riscv/tcg-target.h > +++ b/tcg/riscv/tcg-target.h > @@ -175,5 +175,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); > #define TCG_TARGET_NEED_POOL_LABELS > > #define TCG_TARGET_HAS_MEMORY_BSWAP 0 > +#define TCG_TARGET_CONSET_H > > #endif > diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc > index 33047c1951..d222692704 100644 > --- a/tcg/riscv/tcg-target.c.inc > +++ b/tcg/riscv/tcg-target.c.inc > @@ -1571,50 +1571,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, > } > } > > -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) > +static int tcg_target_op_def(TCGOpcode op) > { > - static const TCGTargetOpDef r > - = { .args_ct_str = { "r" } }; > - static const TCGTargetOpDef r_r > - = { .args_ct_str = { "r", "r" } }; > - static const TCGTargetOpDef rZ_r > - = { .args_ct_str = { "rZ", "r" } }; > - static const TCGTargetOpDef rZ_rZ > - = { .args_ct_str = { "rZ", "rZ" } }; > - static const TCGTargetOpDef rZ_rZ_rZ_rZ > - = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } }; > - static const TCGTargetOpDef r_r_ri > - = { .args_ct_str = { "r", "r", "ri" } }; > - static const TCGTargetOpDef r_r_rI > - = { .args_ct_str = { "r", "r", "rI" } }; > - static const TCGTargetOpDef r_rZ_rN > - = { .args_ct_str = { "r", "rZ", "rN" } }; > - static const TCGTargetOpDef r_rZ_rZ > - = { .args_ct_str = { "r", "rZ", "rZ" } }; > - static const TCGTargetOpDef r_rZ_rZ_rZ_rZ > - = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } }; > - static const TCGTargetOpDef r_L > - = { .args_ct_str = { "r", "L" } }; > - static const TCGTargetOpDef r_r_L > - = { .args_ct_str = { "r", "r", "L" } }; > - static const TCGTargetOpDef r_L_L > - = { .args_ct_str = { "r", "L", "L" } }; > - static const TCGTargetOpDef r_r_L_L > - = { .args_ct_str = { "r", "r", "L", "L" } }; > - static const TCGTargetOpDef LZ_L > - = { .args_ct_str = { "LZ", "L" } }; > - static const TCGTargetOpDef LZ_L_L > - = { .args_ct_str = { "LZ", "L", "L" } }; > - static const TCGTargetOpDef LZ_LZ_L > - = { .args_ct_str = { "LZ", "LZ", "L" } }; > - static const TCGTargetOpDef LZ_LZ_L_L > - = { .args_ct_str = { "LZ", "LZ", "L", "L" } }; > - static const TCGTargetOpDef r_r_rZ_rZ_rM_rM > - = { .args_ct_str = { "r", "r", "rZ", "rZ", "rM", "rM" } }; > - > switch (op) { > case INDEX_op_goto_ptr: > - return &r; > + return C_O0_I1(r); > > case INDEX_op_ld8u_i32: > case INDEX_op_ld8s_i32: > @@ -1646,7 +1607,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) > case INDEX_op_extrl_i64_i32: > case INDEX_op_extrh_i64_i32: > case INDEX_op_ext_i32_i64: > - return &r_r; > + return C_O1_I1(r, r); > > case INDEX_op_st8_i32: > case INDEX_op_st16_i32: > @@ -1655,7 +1616,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) > case INDEX_op_st16_i64: > case INDEX_op_st32_i64: > case INDEX_op_st_i64: > - return &rZ_r; > + return C_O0_I2(rZ, r); > > case INDEX_op_add_i32: > case INDEX_op_and_i32: > @@ -1665,11 +1626,11 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) > case INDEX_op_and_i64: > case INDEX_op_or_i64: > case INDEX_op_xor_i64: > - return &r_r_rI; > + return C_O1_I2(r, r, rI); > > case INDEX_op_sub_i32: > case INDEX_op_sub_i64: > - return &r_rZ_rN; > + return C_O1_I2(r, rZ, rN); > > case INDEX_op_mul_i32: > case INDEX_op_mulsh_i32: > @@ -1687,7 +1648,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) > case INDEX_op_rem_i64: > case INDEX_op_remu_i64: > case INDEX_op_setcond_i64: > - return &r_rZ_rZ; > + return C_O1_I2(r, rZ, rZ); > > case INDEX_op_shl_i32: > case INDEX_op_shr_i32: > @@ -1695,39 +1656,41 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) > case INDEX_op_shl_i64: > case INDEX_op_shr_i64: > case INDEX_op_sar_i64: > - return &r_r_ri; > + return C_O1_I2(r, r, ri); > > case INDEX_op_brcond_i32: > case INDEX_op_brcond_i64: > - return &rZ_rZ; > + return C_O0_I2(rZ, rZ); > > case INDEX_op_add2_i32: > case INDEX_op_add2_i64: > case INDEX_op_sub2_i32: > case INDEX_op_sub2_i64: > - return &r_r_rZ_rZ_rM_rM; > + return C_O2_I4(r, r, rZ, rZ, rM, rM); > > case INDEX_op_brcond2_i32: > - return &rZ_rZ_rZ_rZ; > + return C_O0_I4(rZ, rZ, rZ, rZ); > > case INDEX_op_setcond2_i32: > - return &r_rZ_rZ_rZ_rZ; > + return C_O1_I4(r, rZ, rZ, rZ, rZ); > > case INDEX_op_qemu_ld_i32: > - return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L; > + return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS > + ? C_O1_I1(r, L) : C_O1_I2(r, L, L)); > case INDEX_op_qemu_st_i32: > - return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_L : &LZ_L_L; > + return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS > + ? C_O0_I2(LZ, L) : C_O0_I3(LZ, L, L)); > case INDEX_op_qemu_ld_i64: > - return TCG_TARGET_REG_BITS == 64 ? &r_L > - : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L > - : &r_r_L_L; > + return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) > + : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, L) > + : C_O2_I2(r, r, L, L)); > case INDEX_op_qemu_st_i64: > - return TCG_TARGET_REG_BITS == 64 ? &LZ_L > - : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_LZ_L > - : &LZ_LZ_L_L; > + return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(LZ, L) > + : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(LZ, LZ, L) > + : C_O0_I4(LZ, LZ, L, L)); > > default: > - return NULL; > + g_assert_not_reached(); > } > } > > -- > 2.25.1 > >
On Wed, 23 Dec 2020 at 06:25, Richard Henderson <richard.henderson@linaro.org> wrote: > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > tcg/riscv/tcg-target-conset.h | 25 +++++++++++ > tcg/riscv/tcg-target.h | 1 + > tcg/riscv/tcg-target.c.inc | 83 ++++++++++------------------------- > 3 files changed, 49 insertions(+), 60 deletions(-) > create mode 100644 tcg/riscv/tcg-target-conset.h > > diff --git a/tcg/riscv/tcg-target-conset.h b/tcg/riscv/tcg-target-conset.h > new file mode 100644 > index 0000000000..116dd75db2 > --- /dev/null > +++ b/tcg/riscv/tcg-target-conset.h > @@ -0,0 +1,25 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * RISC-V target-specific constaint sets. "constraint" > + * Copyright (c) 2020 Linaro > + */ > + (Also "conset.h" looks really like a typo for "const.h" which is kinda confusing :-)) -- PMM
On 1/7/21 7:08 PM, Peter Maydell wrote: > On Wed, 23 Dec 2020 at 06:25, Richard Henderson > <richard.henderson@linaro.org> wrote: >> >> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> >> --- >> tcg/riscv/tcg-target-conset.h | 25 +++++++++++ >> tcg/riscv/tcg-target.h | 1 + >> tcg/riscv/tcg-target.c.inc | 83 ++++++++++------------------------- >> 3 files changed, 49 insertions(+), 60 deletions(-) >> create mode 100644 tcg/riscv/tcg-target-conset.h >> >> diff --git a/tcg/riscv/tcg-target-conset.h b/tcg/riscv/tcg-target-conset.h >> new file mode 100644 >> index 0000000000..116dd75db2 >> --- /dev/null >> +++ b/tcg/riscv/tcg-target-conset.h >> @@ -0,0 +1,25 @@ >> +/* SPDX-License-Identifier: MIT */ >> +/* >> + * RISC-V target-specific constaint sets. > > "constraint" > >> + * Copyright (c) 2020 Linaro >> + */ >> + > > (Also "conset.h" looks really like a typo for "const.h" which > is kinda confusing :-)) Isn't it an abbrev for "constraint sets"?
On 1/7/21 8:08 AM, Peter Maydell wrote: > (Also "conset.h" looks really like a typo for "const.h" which > is kinda confusing :-)) Naming suggestions? :-) r~
On Thu, 7 Jan 2021 at 19:15, Richard Henderson <richard.henderson@linaro.org> wrote: > > On 1/7/21 8:08 AM, Peter Maydell wrote: > > (Also "conset.h" looks really like a typo for "const.h" which > > is kinda confusing :-)) > > Naming suggestions? :-) tcg-target-con-set.h ? -- PMM
diff --git a/tcg/riscv/tcg-target-conset.h b/tcg/riscv/tcg-target-conset.h new file mode 100644 index 0000000000..116dd75db2 --- /dev/null +++ b/tcg/riscv/tcg-target-conset.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: MIT */ +/* + * RISC-V target-specific constaint sets. + * Copyright (c) 2020 Linaro + */ + +C_O0_I1(r) +C_O0_I2(LZ, L) +C_O0_I2(rZ, r) +C_O0_I2(rZ, rZ) +C_O0_I3(LZ, L, L) +C_O0_I3(LZ, LZ, L) +C_O0_I4(LZ, LZ, L, L) +C_O0_I4(rZ, rZ, rZ, rZ) +C_O1_I1(r, L) +C_O1_I1(r, r) +C_O1_I2(r, L, L) +C_O1_I2(r, r, ri) +C_O1_I2(r, r, rI) +C_O1_I2(r, rZ, rN) +C_O1_I2(r, rZ, rZ) +C_O1_I4(r, rZ, rZ, rZ, rZ) +C_O2_I1(r, r, L) +C_O2_I2(r, r, L, L) +C_O2_I4(r, r, rZ, rZ, rM, rM) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 032439d806..a357962e01 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -175,5 +175,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_POOL_LABELS #define TCG_TARGET_HAS_MEMORY_BSWAP 0 +#define TCG_TARGET_CONSET_H #endif diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 33047c1951..d222692704 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1571,50 +1571,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } } -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static int tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r - = { .args_ct_str = { "r" } }; - static const TCGTargetOpDef r_r - = { .args_ct_str = { "r", "r" } }; - static const TCGTargetOpDef rZ_r - = { .args_ct_str = { "rZ", "r" } }; - static const TCGTargetOpDef rZ_rZ - = { .args_ct_str = { "rZ", "rZ" } }; - static const TCGTargetOpDef rZ_rZ_rZ_rZ - = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } }; - static const TCGTargetOpDef r_r_ri - = { .args_ct_str = { "r", "r", "ri" } }; - static const TCGTargetOpDef r_r_rI - = { .args_ct_str = { "r", "r", "rI" } }; - static const TCGTargetOpDef r_rZ_rN - = { .args_ct_str = { "r", "rZ", "rN" } }; - static const TCGTargetOpDef r_rZ_rZ - = { .args_ct_str = { "r", "rZ", "rZ" } }; - static const TCGTargetOpDef r_rZ_rZ_rZ_rZ - = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } }; - static const TCGTargetOpDef r_L - = { .args_ct_str = { "r", "L" } }; - static const TCGTargetOpDef r_r_L - = { .args_ct_str = { "r", "r", "L" } }; - static const TCGTargetOpDef r_L_L - = { .args_ct_str = { "r", "L", "L" } }; - static const TCGTargetOpDef r_r_L_L - = { .args_ct_str = { "r", "r", "L", "L" } }; - static const TCGTargetOpDef LZ_L - = { .args_ct_str = { "LZ", "L" } }; - static const TCGTargetOpDef LZ_L_L - = { .args_ct_str = { "LZ", "L", "L" } }; - static const TCGTargetOpDef LZ_LZ_L - = { .args_ct_str = { "LZ", "LZ", "L" } }; - static const TCGTargetOpDef LZ_LZ_L_L - = { .args_ct_str = { "LZ", "LZ", "L", "L" } }; - static const TCGTargetOpDef r_r_rZ_rZ_rM_rM - = { .args_ct_str = { "r", "r", "rZ", "rZ", "rM", "rM" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: @@ -1646,7 +1607,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_extrl_i64_i32: case INDEX_op_extrh_i64_i32: case INDEX_op_ext_i32_i64: - return &r_r; + return C_O1_I1(r, r); case INDEX_op_st8_i32: case INDEX_op_st16_i32: @@ -1655,7 +1616,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_st16_i64: case INDEX_op_st32_i64: case INDEX_op_st_i64: - return &rZ_r; + return C_O0_I2(rZ, r); case INDEX_op_add_i32: case INDEX_op_and_i32: @@ -1665,11 +1626,11 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_and_i64: case INDEX_op_or_i64: case INDEX_op_xor_i64: - return &r_r_rI; + return C_O1_I2(r, r, rI); case INDEX_op_sub_i32: case INDEX_op_sub_i64: - return &r_rZ_rN; + return C_O1_I2(r, rZ, rN); case INDEX_op_mul_i32: case INDEX_op_mulsh_i32: @@ -1687,7 +1648,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_rem_i64: case INDEX_op_remu_i64: case INDEX_op_setcond_i64: - return &r_rZ_rZ; + return C_O1_I2(r, rZ, rZ); case INDEX_op_shl_i32: case INDEX_op_shr_i32: @@ -1695,39 +1656,41 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_shl_i64: case INDEX_op_shr_i64: case INDEX_op_sar_i64: - return &r_r_ri; + return C_O1_I2(r, r, ri); case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return &rZ_rZ; + return C_O0_I2(rZ, rZ); case INDEX_op_add2_i32: case INDEX_op_add2_i64: case INDEX_op_sub2_i32: case INDEX_op_sub2_i64: - return &r_r_rZ_rZ_rM_rM; + return C_O2_I4(r, r, rZ, rZ, rM, rM); case INDEX_op_brcond2_i32: - return &rZ_rZ_rZ_rZ; + return C_O0_I4(rZ, rZ, rZ, rZ); case INDEX_op_setcond2_i32: - return &r_rZ_rZ_rZ_rZ; + return C_O1_I4(r, rZ, rZ, rZ, rZ); case INDEX_op_qemu_ld_i32: - return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L; + return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS + ? C_O1_I1(r, L) : C_O1_I2(r, L, L)); case INDEX_op_qemu_st_i32: - return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_L : &LZ_L_L; + return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS + ? C_O0_I2(LZ, L) : C_O0_I3(LZ, L, L)); case INDEX_op_qemu_ld_i64: - return TCG_TARGET_REG_BITS == 64 ? &r_L - : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L - : &r_r_L_L; + return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) + : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, L) + : C_O2_I2(r, r, L, L)); case INDEX_op_qemu_st_i64: - return TCG_TARGET_REG_BITS == 64 ? &LZ_L - : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_LZ_L - : &LZ_LZ_L_L; + return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(LZ, L) + : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(LZ, LZ, L) + : C_O0_I4(LZ, LZ, L, L)); default: - return NULL; + g_assert_not_reached(); } }
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/riscv/tcg-target-conset.h | 25 +++++++++++ tcg/riscv/tcg-target.h | 1 + tcg/riscv/tcg-target.c.inc | 83 ++++++++++------------------------- 3 files changed, 49 insertions(+), 60 deletions(-) create mode 100644 tcg/riscv/tcg-target-conset.h -- 2.25.1