diff mbox series

target/arm: Fix sve pred_desc decoding

Message ID 20201230172522.33629-1-richard.henderson@linaro.org
State New
Headers show
Series target/arm: Fix sve pred_desc decoding | expand

Commit Message

Richard Henderson Dec. 30, 2020, 5:25 p.m. UTC 
There was an inconsistency between encoding, which uses
SIMD_DATA_SHIFT, and decoding which used SIMD_OPRSZ_BITS.
This happened to be ok, until e2e7168a214, which reduced
the size of SIMD_OPRSZ_BITS, which lead to truncating all
predicate vector lengths.

Cc: qemu-stable@nongnu.org
Buglink: https://bugs.launchpad.net/bugs/1908551
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---

Ouch.  The patch that exposed this, e2e7168a214, went in near
the start of the 5.2 devel period, and I never noticed.  I've
been doing most of my testing vs ArmIE of late, which due to
lack of a proper sve signal frame restricts RISU to sve128,
which worked fine with this truncation.  I need to spend some
time getting FVP working again...


r~

---
 target/arm/sve_helper.c | 46 ++++++++++++++++++++---------------------
 1 file changed, 23 insertions(+), 23 deletions(-)

-- 
2.25.1

Comments

Peter Maydell Jan. 7, 2021, 6:02 p.m. UTC | #1 
On Wed, 30 Dec 2020 at 17:25, Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> There was an inconsistency between encoding, which uses

> SIMD_DATA_SHIFT, and decoding which used SIMD_OPRSZ_BITS.

> This happened to be ok, until e2e7168a214, which reduced

> the size of SIMD_OPRSZ_BITS, which lead to truncating all

> predicate vector lengths.

>

> Cc: qemu-stable@nongnu.org

> Buglink: https://bugs.launchpad.net/bugs/1908551

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>

> Ouch.  The patch that exposed this, e2e7168a214, went in near

> the start of the 5.2 devel period, and I never noticed.  I've

> been doing most of my testing vs ArmIE of late, which due to

> lack of a proper sve signal frame restricts RISU to sve128,

> which worked fine with this truncation.  I need to spend some

> time getting FVP working again...

>

>

> r~

>

> ---

>  target/arm/sve_helper.c | 46 ++++++++++++++++++++---------------------

>  1 file changed, 23 insertions(+), 23 deletions(-)

>

> diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c

> index 5f037c3a8f..99e4b70d2f 100644

> --- a/target/arm/sve_helper.c

> +++ b/target/arm/sve_helper.c

> @@ -914,7 +914,7 @@ uint32_t HELPER(sve_pfirst)(void *vd, void *vg, uint32_t words)

>

>  uint32_t HELPER(sve_pnext)(void *vd, void *vg, uint32_t pred_desc)

>  {

> -    intptr_t words = extract32(pred_desc, 0, SIMD_OPRSZ_BITS);

> +    intptr_t words = extract32(pred_desc, 0, SIMD_DATA_SHIFT);

>      intptr_t esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2);

>      uint32_t flags = PREDTEST_INIT;

>      uint64_t *d = vd, *g = vg, esz_mask;

> @@ -1867,7 +1867,7 @@ static uint64_t compress_bits(uint64_t x, int n)

>

>  void HELPER(sve_zip_p)(void *vd, void *vn, void *vm, uint32_t pred_desc)

>  {

> -    intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;

> +    intptr_t oprsz = extract32(pred_desc, 0, SIMD_DATA_SHIFT) + 2;


Why do we not get oprsz by extracting SIMD_OPRSZ_BITS starting at
SIMD_OPRSZ_SHIFT ? (or even by calling simd_oprsz(), which
certainly looks like it ought to be a helper function for
extracting the oprsz...)

If the encoding constants in tcg-gvec-desc.h are right then
"SIMD_DATA_SHIFT bits starting at bit 0" is two fields glued
together (MAXSZ and OPRSZ).

thanks
-- PMM
Richard Henderson Jan. 7, 2021, 7:13 p.m. UTC | #2 
On 1/7/21 8:02 AM, Peter Maydell wrote:
>>  void HELPER(sve_zip_p)(void *vd, void *vn, void *vm, uint32_t pred_desc)

>>  {

>> -    intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;

>> +    intptr_t oprsz = extract32(pred_desc, 0, SIMD_DATA_SHIFT) + 2;

> 

> Why do we not get oprsz by extracting SIMD_OPRSZ_BITS starting at

> SIMD_OPRSZ_SHIFT ? (or even by calling simd_oprsz(), which

> certainly looks like it ought to be a helper function for

> extracting the oprsz...)


The predicate operations are small -- minimum 2 bytes -- and cannot encode with
the real simd_oprsz (minumum 8, then multiples of 16).

This is shear abuse of the SIMD_* defines.  You're right that I shouldn't have
done this in the first place, and should probably rename everything having to
do with predicates.


r~
diff mbox series

Patch

diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 5f037c3a8f..99e4b70d2f 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -914,7 +914,7 @@  uint32_t HELPER(sve_pfirst)(void *vd, void *vg, uint32_t words)
 
 uint32_t HELPER(sve_pnext)(void *vd, void *vg, uint32_t pred_desc)
 {
-    intptr_t words = extract32(pred_desc, 0, SIMD_OPRSZ_BITS);
+    intptr_t words = extract32(pred_desc, 0, SIMD_DATA_SHIFT);
     intptr_t esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2);
     uint32_t flags = PREDTEST_INIT;
     uint64_t *d = vd, *g = vg, esz_mask;
@@ -1867,7 +1867,7 @@  static uint64_t compress_bits(uint64_t x, int n)
 
 void HELPER(sve_zip_p)(void *vd, void *vn, void *vm, uint32_t pred_desc)
 {
-    intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
+    intptr_t oprsz = extract32(pred_desc, 0, SIMD_DATA_SHIFT) + 2;
     int esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2);
     intptr_t high = extract32(pred_desc, SIMD_DATA_SHIFT + 2, 1);
     uint64_t *d = vd;
@@ -1928,7 +1928,7 @@  void HELPER(sve_zip_p)(void *vd, void *vn, void *vm, uint32_t pred_desc)
 
 void HELPER(sve_uzp_p)(void *vd, void *vn, void *vm, uint32_t pred_desc)
 {
-    intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
+    intptr_t oprsz = extract32(pred_desc, 0, SIMD_DATA_SHIFT) + 2;
     int esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2);
     int odd = extract32(pred_desc, SIMD_DATA_SHIFT + 2, 1) << esz;
     uint64_t *d = vd, *n = vn, *m = vm;
@@ -1985,7 +1985,7 @@  void HELPER(sve_uzp_p)(void *vd, void *vn, void *vm, uint32_t pred_desc)
 
 void HELPER(sve_trn_p)(void *vd, void *vn, void *vm, uint32_t pred_desc)
 {
-    intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
+    intptr_t oprsz = extract32(pred_desc, 0, SIMD_DATA_SHIFT) + 2;
     uintptr_t esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2);
     bool odd = extract32(pred_desc, SIMD_DATA_SHIFT + 2, 1);
     uint64_t *d = vd, *n = vn, *m = vm;
@@ -2035,7 +2035,7 @@  static uint8_t reverse_bits_8(uint8_t x, int n)
 
 void HELPER(sve_rev_p)(void *vd, void *vn, uint32_t pred_desc)
 {
-    intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
+    intptr_t oprsz = extract32(pred_desc, 0, SIMD_DATA_SHIFT) + 2;
     int esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2);
     intptr_t i, oprsz_2 = oprsz / 2;
 
@@ -2065,7 +2065,7 @@  void HELPER(sve_rev_p)(void *vd, void *vn, uint32_t pred_desc)
 
 void HELPER(sve_punpk_p)(void *vd, void *vn, uint32_t pred_desc)
 {
-    intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
+    intptr_t oprsz = extract32(pred_desc, 0, SIMD_DATA_SHIFT) + 2;
     intptr_t high = extract32(pred_desc, SIMD_DATA_SHIFT + 2, 1);
     uint64_t *d = vd;
     intptr_t i;
@@ -2221,7 +2221,7 @@  void HELPER(sve_compact_d)(void *vd, void *vn, void *vg, uint32_t desc)
  */
 int32_t HELPER(sve_last_active_element)(void *vg, uint32_t pred_desc)
 {
-    intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
+    intptr_t oprsz = extract32(pred_desc, 0, SIMD_DATA_SHIFT) + 2;
     intptr_t esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2);
 
     return last_active_element(vg, DIV_ROUND_UP(oprsz, 8), esz);
@@ -2694,7 +2694,7 @@  static uint32_t do_zero(ARMPredicateReg *d, intptr_t oprsz)
 void HELPER(sve_brkpa)(void *vd, void *vn, void *vm, void *vg,
                        uint32_t pred_desc)
 {
-    intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
+    intptr_t oprsz = extract32(pred_desc, 0, SIMD_DATA_SHIFT) + 2;
     if (last_active_pred(vn, vg, oprsz)) {
         compute_brk_z(vd, vm, vg, oprsz, true);
     } else {
@@ -2705,7 +2705,7 @@  void HELPER(sve_brkpa)(void *vd, void *vn, void *vm, void *vg,
 uint32_t HELPER(sve_brkpas)(void *vd, void *vn, void *vm, void *vg,
                             uint32_t pred_desc)
 {
-    intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
+    intptr_t oprsz = extract32(pred_desc, 0, SIMD_DATA_SHIFT) + 2;
     if (last_active_pred(vn, vg, oprsz)) {
         return compute_brks_z(vd, vm, vg, oprsz, true);
     } else {
@@ -2716,7 +2716,7 @@  uint32_t HELPER(sve_brkpas)(void *vd, void *vn, void *vm, void *vg,
 void HELPER(sve_brkpb)(void *vd, void *vn, void *vm, void *vg,
                        uint32_t pred_desc)
 {
-    intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
+    intptr_t oprsz = extract32(pred_desc, 0, SIMD_DATA_SHIFT) + 2;
     if (last_active_pred(vn, vg, oprsz)) {
         compute_brk_z(vd, vm, vg, oprsz, false);
     } else {
@@ -2727,7 +2727,7 @@  void HELPER(sve_brkpb)(void *vd, void *vn, void *vm, void *vg,
 uint32_t HELPER(sve_brkpbs)(void *vd, void *vn, void *vm, void *vg,
                             uint32_t pred_desc)
 {
-    intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
+    intptr_t oprsz = extract32(pred_desc, 0, SIMD_DATA_SHIFT) + 2;
     if (last_active_pred(vn, vg, oprsz)) {
         return compute_brks_z(vd, vm, vg, oprsz, false);
     } else {
@@ -2737,55 +2737,55 @@  uint32_t HELPER(sve_brkpbs)(void *vd, void *vn, void *vm, void *vg,
 
 void HELPER(sve_brka_z)(void *vd, void *vn, void *vg, uint32_t pred_desc)
 {
-    intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
+    intptr_t oprsz = extract32(pred_desc, 0, SIMD_DATA_SHIFT) + 2;
     compute_brk_z(vd, vn, vg, oprsz, true);
 }
 
 uint32_t HELPER(sve_brkas_z)(void *vd, void *vn, void *vg, uint32_t pred_desc)
 {
-    intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
+    intptr_t oprsz = extract32(pred_desc, 0, SIMD_DATA_SHIFT) + 2;
     return compute_brks_z(vd, vn, vg, oprsz, true);
 }
 
 void HELPER(sve_brkb_z)(void *vd, void *vn, void *vg, uint32_t pred_desc)
 {
-    intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
+    intptr_t oprsz = extract32(pred_desc, 0, SIMD_DATA_SHIFT) + 2;
     compute_brk_z(vd, vn, vg, oprsz, false);
 }
 
 uint32_t HELPER(sve_brkbs_z)(void *vd, void *vn, void *vg, uint32_t pred_desc)
 {
-    intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
+    intptr_t oprsz = extract32(pred_desc, 0, SIMD_DATA_SHIFT) + 2;
     return compute_brks_z(vd, vn, vg, oprsz, false);
 }
 
 void HELPER(sve_brka_m)(void *vd, void *vn, void *vg, uint32_t pred_desc)
 {
-    intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
+    intptr_t oprsz = extract32(pred_desc, 0, SIMD_DATA_SHIFT) + 2;
     compute_brk_m(vd, vn, vg, oprsz, true);
 }
 
 uint32_t HELPER(sve_brkas_m)(void *vd, void *vn, void *vg, uint32_t pred_desc)
 {
-    intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
+    intptr_t oprsz = extract32(pred_desc, 0, SIMD_DATA_SHIFT) + 2;
     return compute_brks_m(vd, vn, vg, oprsz, true);
 }
 
 void HELPER(sve_brkb_m)(void *vd, void *vn, void *vg, uint32_t pred_desc)
 {
-    intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
+    intptr_t oprsz = extract32(pred_desc, 0, SIMD_DATA_SHIFT) + 2;
     compute_brk_m(vd, vn, vg, oprsz, false);
 }
 
 uint32_t HELPER(sve_brkbs_m)(void *vd, void *vn, void *vg, uint32_t pred_desc)
 {
-    intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
+    intptr_t oprsz = extract32(pred_desc, 0, SIMD_DATA_SHIFT) + 2;
     return compute_brks_m(vd, vn, vg, oprsz, false);
 }
 
 void HELPER(sve_brkn)(void *vd, void *vn, void *vg, uint32_t pred_desc)
 {
-    intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
+    intptr_t oprsz = extract32(pred_desc, 0, SIMD_DATA_SHIFT) + 2;
 
     if (!last_active_pred(vn, vg, oprsz)) {
         do_zero(vd, oprsz);
@@ -2811,7 +2811,7 @@  static uint32_t predtest_ones(ARMPredicateReg *d, intptr_t oprsz,
 
 uint32_t HELPER(sve_brkns)(void *vd, void *vn, void *vg, uint32_t pred_desc)
 {
-    intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
+    intptr_t oprsz = extract32(pred_desc, 0, SIMD_DATA_SHIFT) + 2;
 
     if (last_active_pred(vn, vg, oprsz)) {
         return predtest_ones(vd, oprsz, -1);
@@ -2822,7 +2822,7 @@  uint32_t HELPER(sve_brkns)(void *vd, void *vn, void *vg, uint32_t pred_desc)
 
 uint64_t HELPER(sve_cntp)(void *vn, void *vg, uint32_t pred_desc)
 {
-    intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
+    intptr_t oprsz = extract32(pred_desc, 0, SIMD_DATA_SHIFT) + 2;
     intptr_t esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2);
     uint64_t *n = vn, *g = vg, sum = 0, mask = pred_esz_masks[esz];
     intptr_t i;
@@ -2836,7 +2836,7 @@  uint64_t HELPER(sve_cntp)(void *vn, void *vg, uint32_t pred_desc)
 
 uint32_t HELPER(sve_while)(void *vd, uint32_t count, uint32_t pred_desc)
 {
-    uintptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
+    uintptr_t oprsz = extract32(pred_desc, 0, SIMD_DATA_SHIFT) + 2;
     intptr_t esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2);
     uint64_t esz_mask = pred_esz_masks[esz];
     ARMPredicateReg *d = vd;