| Message ID | 20210103100007.32867-3-samuel@sholland.org |
|---|---|
| State | Accepted |
| Commit | b071a124558fce2135f62b25d02cf3ba9bf3de6a |
| Headers | show |
| Series | Allwinner H6 RSB support | expand |
On Sun, Jan 3, 2021 at 11:00 AM Samuel Holland <samuel@sholland.org> wrote: > As there is an RSB controller in the H6 SoC, there should be some pin > configuration for it. While no such configuration is documented, the > "s_i2c" pins are suspiciously on the "alternate" function 3, with no > primary function 2 given. This suggests the primary function for these > pins is actually RSB, and that is indeed the case. > > Add the "s_rsb" pin functions so the RSB controller can be used. > > Signed-off-by: Samuel Holland <samuel@sholland.org> Is it OK if I just apply this patch to the pinctrl tree? Yours, Linus Walleij
On Wed, Jan 6, 2021 at 6:35 AM Linus Walleij <linus.walleij@linaro.org> wrote: > > On Sun, Jan 3, 2021 at 11:00 AM Samuel Holland <samuel@sholland.org> wrote: > > > As there is an RSB controller in the H6 SoC, there should be some pin > > configuration for it. While no such configuration is documented, the > > "s_i2c" pins are suspiciously on the "alternate" function 3, with no > > primary function 2 given. This suggests the primary function for these > > pins is actually RSB, and that is indeed the case. > > > > Add the "s_rsb" pin functions so the RSB controller can be used. > > > > Signed-off-by: Samuel Holland <samuel@sholland.org> > > Is it OK if I just apply this patch to the pinctrl tree? Please do. Thanks ChenYu
On Sun, Jan 3, 2021 at 11:00 AM Samuel Holland <samuel@sholland.org> wrote: > As there is an RSB controller in the H6 SoC, there should be some pin > configuration for it. While no such configuration is documented, the > "s_i2c" pins are suspiciously on the "alternate" function 3, with no > primary function 2 given. This suggests the primary function for these > pins is actually RSB, and that is indeed the case. > > Add the "s_rsb" pin functions so the RSB controller can be used. > > Signed-off-by: Samuel Holland <samuel@sholland.org> This patch applied to the pinctrl tree. Yours, Linus Walleij
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c index 4557e18d5989..c7d90c44e87a 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c @@ -24,11 +24,13 @@ static const struct sunxi_desc_pin sun50i_h6_r_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */ SUNXI_FUNCTION(0x3, "s_i2c"), /* SCK */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */ SUNXI_FUNCTION(0x3, "s_i2c"), /* SDA */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
As there is an RSB controller in the H6 SoC, there should be some pin configuration for it. While no such configuration is documented, the "s_i2c" pins are suspiciously on the "alternate" function 3, with no primary function 2 given. This suggests the primary function for these pins is actually RSB, and that is indeed the case. Add the "s_rsb" pin functions so the RSB controller can be used. Signed-off-by: Samuel Holland <samuel@sholland.org> --- drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c | 2 ++ 1 file changed, 2 insertions(+)