Message ID | 20201228154920.18846-1-digetx@gmail.com |
---|---|
Headers | show |
Series | Introduce memory interconnect for NVIDIA Tegra SoCs | expand |
On Mon, Dec 28, 2020 at 06:49:18PM +0300, Dmitry Osipenko wrote: > Now Internal and External memory controllers are memory interconnection > providers. This allows us to use interconnect API for tuning of memory > configuration. EMC driver now supports OPPs and DVFS. > > Tested-by: Nicolas Chauvet <kwizart@gmail.com> > Acked-by: Georgi Djakov <georgi.djakov@linaro.org> > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- > drivers/memory/tegra/Kconfig | 1 + > drivers/memory/tegra/tegra124-emc.c | 320 +++++++++++++++++++++++++++- > drivers/memory/tegra/tegra124.c | 82 ++++++- > 3 files changed, 391 insertions(+), 12 deletions(-) Thanks, applied. Best regards, Krzysztof
28.12.2020 18:49, Dmitry Osipenko пишет: > Display controller (DC) performs isochronous memory transfers, and thus, > has a requirement for a minimum memory bandwidth that shall be fulfilled, > otherwise framebuffer data can't be fetched fast enough and this results > in a DC's data-FIFO underflow that follows by a visual corruption. > > The Memory Controller drivers provide facility for memory bandwidth > management via interconnect API. Let's wire up the interconnect API > support to the DC driver in order to fix the distorted display output > on T30 Ouya, T124 TK1 and other Tegra devices. > > Tested-by: Peter Geis <pgwipeout@gmail.com> > Tested-by: Nicolas Chauvet <kwizart@gmail.com> > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- Thierry, I'm looking forward to yours review. Only DRM patches are left unmerged yet in this series.