diff mbox series

crypto: x86/crc32c-intel - Don't match some Zhaoxin CPUs

Message ID 1608028091-29439-1-git-send-email-TonyWWang-oc@zhaoxin.com
State New
Headers show
Series crypto: x86/crc32c-intel - Don't match some Zhaoxin CPUs | expand

Commit Message

Tony W Wang-oc Dec. 15, 2020, 10:28 a.m. UTC
The driver crc32c-intel match CPUs supporting X86_FEATURE_XMM4_2.
On platforms with Zhaoxin CPUs supporting this X86 feature, when
crc32c-intel and crc32c-generic are both registered, system will
use crc32c-intel because its .cra_priority is greater than
crc32c-generic.

When doing lmbench3 Create and Delete file test on partitions with
ext4 enabling metadata checksum, found using crc32c-generic driver
could get about 20% performance gain than using the driver crc32c-intel
on some Zhaoxin CPUs.

This case expect to use crc32c-generic driver for these Zhaoxin CPUs
to get performance gain, so remove these Zhaoxin CPUs support from
crc32c-intel.

Signed-off-by: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
---
 arch/x86/crypto/crc32c-intel_glue.c | 21 +++++++++++++++++++--
 1 file changed, 19 insertions(+), 2 deletions(-)

Comments

Herbert Xu Jan. 2, 2021, 9:12 p.m. UTC | #1
On Tue, Dec 15, 2020 at 06:28:11PM +0800, Tony W Wang-oc wrote:
> The driver crc32c-intel match CPUs supporting X86_FEATURE_XMM4_2.

> On platforms with Zhaoxin CPUs supporting this X86 feature, when

> crc32c-intel and crc32c-generic are both registered, system will

> use crc32c-intel because its .cra_priority is greater than

> crc32c-generic.

> 

> When doing lmbench3 Create and Delete file test on partitions with

> ext4 enabling metadata checksum, found using crc32c-generic driver

> could get about 20% performance gain than using the driver crc32c-intel

> on some Zhaoxin CPUs.

> 

> This case expect to use crc32c-generic driver for these Zhaoxin CPUs

> to get performance gain, so remove these Zhaoxin CPUs support from

> crc32c-intel.

> 

> Signed-off-by: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>

> ---

>  arch/x86/crypto/crc32c-intel_glue.c | 21 +++++++++++++++++++--

>  1 file changed, 19 insertions(+), 2 deletions(-)


This does not seem to address the latest comment from hpa.

Thanks,
-- 
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
Tony W Wang-oc Jan. 7, 2021, 6:27 a.m. UTC | #2
On 03/01/2021 05:12, Herbert Xu wrote:
> On Tue, Dec 15, 2020 at 06:28:11PM +0800, Tony W Wang-oc wrote:

>> The driver crc32c-intel match CPUs supporting X86_FEATURE_XMM4_2.

>> On platforms with Zhaoxin CPUs supporting this X86 feature, when

>> crc32c-intel and crc32c-generic are both registered, system will

>> use crc32c-intel because its .cra_priority is greater than

>> crc32c-generic.

>>

>> When doing lmbench3 Create and Delete file test on partitions with

>> ext4 enabling metadata checksum, found using crc32c-generic driver

>> could get about 20% performance gain than using the driver crc32c-intel

>> on some Zhaoxin CPUs.

>>

>> This case expect to use crc32c-generic driver for these Zhaoxin CPUs

>> to get performance gain, so remove these Zhaoxin CPUs support from

>> crc32c-intel.

>>

>> Signed-off-by: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>

>> ---

>>  arch/x86/crypto/crc32c-intel_glue.c | 21 +++++++++++++++++++--

>>  1 file changed, 19 insertions(+), 2 deletions(-)

> 

> This does not seem to address the latest comment from hpa.

> 


Yes, please ignore this patch. Have send new patch set per Hpa's suggestion.

Sincerely
Tonyw

> Thanks,

>
diff mbox series

Patch

diff --git a/arch/x86/crypto/crc32c-intel_glue.c b/arch/x86/crypto/crc32c-intel_glue.c
index feccb52..5171091 100644
--- a/arch/x86/crypto/crc32c-intel_glue.c
+++ b/arch/x86/crypto/crc32c-intel_glue.c
@@ -215,14 +215,31 @@  static struct shash_alg alg = {
 };
 
 static const struct x86_cpu_id crc32c_cpu_id[] = {
-	X86_MATCH_FEATURE(X86_FEATURE_XMM4_2, NULL),
+	/*
+	 * Negative entries; exclude these chips from using this driver.
+	 * They match the positive rule below, but their CRC32 instruction
+	 * implementation is so slow, it doesn't merit use.
+	 */
+	X86_MATCH_VENDOR_FAM_FEATURE(ZHAOXIN, 0x6, X86_FEATURE_XMM4_2, false),
+	X86_MATCH_VENDOR_FAM_MODEL_FEATURE(ZHAOXIN, 0x7, 0x1b, X86_FEATURE_XMM4_2, false),
+	X86_MATCH_VENDOR_FAM_MODEL_FEATURE(ZHAOXIN, 0x7, 0x3b, X86_FEATURE_XMM4_2, false),
+	X86_MATCH_VENDOR_FAM_FEATURE(CENTAUR, 0x6, X86_FEATURE_XMM4_2, false),
+	X86_MATCH_VENDOR_FAM_MODEL_FEATURE(CENTAUR, 0x7, 0x1b, X86_FEATURE_XMM4_2, false),
+	X86_MATCH_VENDOR_FAM_MODEL_FEATURE(CENTAUR, 0x7, 0x3b, X86_FEATURE_XMM4_2, false),
+	/*
+	 * Positive entry; SSE-4.2 instructions include special purpose CRC32
+	 * instructions.
+	 */
+	X86_MATCH_FEATURE(X86_FEATURE_XMM4_2, true),
 	{}
 };
 MODULE_DEVICE_TABLE(x86cpu, crc32c_cpu_id);
 
 static int __init crc32c_intel_mod_init(void)
 {
-	if (!x86_match_cpu(crc32c_cpu_id))
+	const struct x86_cpu_id *m = x86_match_cpu(crc32c_cpu_id);
+
+	if (!m || !m->driver_data)
 		return -ENODEV;
 #ifdef CONFIG_X86_64
 	if (boot_cpu_has(X86_FEATURE_PCLMULQDQ)) {