diff mbox series

[v6,04/11] clk: at91: clk-master: add 5th divisor for mck master

Message ID 1605800597-16720-5-git-send-email-claudiu.beznea@microchip.com
State Superseded
Headers show
Series clk: at91: clk-master: re-factor master clock | expand

Commit Message

Claudiu Beznea Nov. 19, 2020, 3:43 p.m. UTC
From: Eugen Hristev <eugen.hristev@microchip.com>

clk-master can have 5 divisors with a field width of 3 bits
on some products.

Change the mask and number of divisors accordingly.

Reported-by: Mihai Sain <mihai.sain@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 drivers/clk/at91/clk-master.c | 2 +-
 drivers/clk/at91/pmc.h        | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

Comments

Stephen Boyd Dec. 19, 2020, 7:53 p.m. UTC | #1
Quoting Claudiu Beznea (2020-11-19 07:43:10)
> From: Eugen Hristev <eugen.hristev@microchip.com>

> 

> clk-master can have 5 divisors with a field width of 3 bits

> on some products.

> 

> Change the mask and number of divisors accordingly.

> 

> Reported-by: Mihai Sain <mihai.sain@microchip.com>

> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>

> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>

> ---


Applied to clk-next
diff mbox series

Patch

diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
index bd0d8a69a2cf..aafd003b30cf 100644
--- a/drivers/clk/at91/clk-master.c
+++ b/drivers/clk/at91/clk-master.c
@@ -15,7 +15,7 @@ 
 #define MASTER_PRES_MASK	0x7
 #define MASTER_PRES_MAX		MASTER_PRES_MASK
 #define MASTER_DIV_SHIFT	8
-#define MASTER_DIV_MASK		0x3
+#define MASTER_DIV_MASK		0x7
 
 #define PMC_MCR			0x30
 #define PMC_MCR_ID_MSK		GENMASK(3, 0)
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
index 7b86affc6d7c..0a9364bde339 100644
--- a/drivers/clk/at91/pmc.h
+++ b/drivers/clk/at91/pmc.h
@@ -48,7 +48,7 @@  extern const struct clk_master_layout at91sam9x5_master_layout;
 
 struct clk_master_characteristics {
 	struct clk_range output;
-	u32 divisors[4];
+	u32 divisors[5];
 	u8 have_div3_pres;
 };