| Message ID | Ax8WZP5mKeS4D-elLrXw3AUz9iT7Dgfh-VVWbSOiypPXlS9KRr6GFXhrlf2v6QrhWeFtheX0gYhM-zGawalUidf1noc1gE-TvinLrKryibc=@protonmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | ufs: Unrecoverable UFSHCD_UIC_DL_TCx_REPLAY_ERROR after some write operations | expand |
I've been able to extract some output. This is triggered by writing 1MB or more (although I haven't tested smaller sizes):
[ 113.808190] ufshcd-qcom 624000.ufshc: UFS Host state=3
[ 114.345777] ufshcd-qcom 624000.ufshc: outstanding reqs=0x1c00 tasks=0x0
[ 114.615383] ufshcd-qcom 624000.ufshc: saved_err=0x4, saved_uic_err=0x45
[ 114.884837] ufshcd-qcom 624000.ufshc: Device power mode=1, UIC link state=1
[ 115.154517] ufshcd-qcom 624000.ufshc: PM in progress=0, sys. suspended=0
[ 115.424186] ufshcd-qcom 624000.ufshc: Auto BKOPS=0, Host self-block=1
[ 115.693062] ufshcd-qcom 624000.ufshc: Clk gate=1
[ 115.960450] ufshcd-qcom 624000.ufshc: last_hibern8_exit_tstamp at 0 us, hibern8_exit_cnt=0
[ 116.230669] ufshcd-qcom 624000.ufshc: last intr at 116214372 us, last intr status=0x4
[ 116.501027] ufshcd-qcom 624000.ufshc: error handling flags=0x1, req. abort count=0
[ 116.771186] ufshcd-qcom 624000.ufshc: hba->ufs_version=0x200, Host capabilities=0x107001f, caps=0x10f
[ 117.041178] ufshcd-qcom 624000.ufshc: quirks=0x20, dev. quirks=0xc4
[ 117.308990] ufshcd-qcom 624000.ufshc: UFS dev info: SAMSUNG KLUCG4J1CB-B0B1 rev 0800
[ 117.579011] ufshcd-qcom 624000.ufshc: clk: core_clk_src, rate: 100000000
[ 117.849273] ufshcd-qcom 624000.ufshc: clk: core_clk_unipro_src, rate: 150000000
[ 118.120005] ufshcd-qcom 624000.ufshc: ufshcd_print_pwr_info:[RX, TX]: gear=[1, 1], lane[1, 1], pwr[FAST MODE, FAST MODE], rate = 2
[ 118.396060] host_regs: 00000000: 0107001f 00000000 00010100 00000000
[ 118.671326] host_regs: 00000010: 01000000 00010217 00000000 00000000
[ 118.944397] host_regs: 00000020: 00000000 00030e75 00000000 00000000
[ 119.215094] host_regs: 00000030: 0000010f 00000001 00000000 00000000
[ 119.483854] host_regs: 00000040: 00000000 00000000 00000000 00000000
[ 119.751127] host_regs: 00000050: 00f4f000 00000001 00001c00 00000000
[ 120.016432] host_regs: 00000060: 00000001 ffffffff 00000000 00000000
[ 120.016865] host_regs: 00000070: 00f50000 00000001 00000000 00000000
[ 120.543366] host_regs: 00000080: 00000001 00000000 00000000 00000000
[ 120.806938] host_regs: 00000090: 00000002 d0020000 00000000 00000096
[ 121.070606] ufshcd-qcom 624000.ufshc: pa_err[0] = 0x80000010 at 113794938 us
[ 121.333942] ufshcd-qcom 624000.ufshc: dl_err[5] = 0x80000002 at 120801823 us
[ 121.595917] ufshcd-qcom 624000.ufshc: dl_err[2] = 0x80000002 at 121129498 us
[ 121.855581] ufshcd-qcom 624000.ufshc: dl_err[7] = 0x80000002 at 121457175 us
[ 122.112917] ufshcd-qcom 624000.ufshc: dl_err[4] = 0x80000002 at 121784848 us
[ 122.367927] ufshcd-qcom 624000.ufshc: dl_err[1] = 0x80000002 at 122112499 us
[ 122.621619] ufshcd-qcom 624000.ufshc: dl_err[6] = 0x80000002 at 122440198 us
[ 122.873739] ufshcd-qcom 624000.ufshc: dl_err[3] = 0x80000002 at 122767886 us
[ 123.124168] ufshcd-qcom 624000.ufshc: dl_err[0] = 0x80000002 at 123095544 us
[ 123.372712] ufshcd-qcom 624000.ufshc: No record of nl_err
[ 123.619878] ufshcd-qcom 624000.ufshc: No record of tl_err
[ 123.865440] ufshcd-qcom 624000.ufshc: No record of dme_err
[ 124.109979] ufshcd-qcom 624000.ufshc: No record of auto_hibern8_err
[ 124.355018] ufshcd-qcom 624000.ufshc: No record of fatal_err
[ 124.599515] ufshcd-qcom 624000.ufshc: No record of link_startup_fail
[ 124.842980] ufshcd-qcom 624000.ufshc: No record of resume_fail
[ 125.085270] ufshcd-qcom 624000.ufshc: No record of suspend_fail
[ 125.327011] ufshcd-qcom 624000.ufshc: dev_reset[0] = 0x0 at 13117269 us
[ 125.567446] ufshcd-qcom 624000.ufshc: No record of host_reset
[ 125.808674] ufshcd-qcom 624000.ufshc: No record of task_abort
[ 126.048492] HCI Vendor Specific Registers 00000000: 000000c8 00000000 00000000 00000000
[ 126.292312] HCI Vendor Specific Registers 00000010: 00000000 00000000 00000000 5c5c052c
[ 126.535310] HCI Vendor Specific Registers 00000020: 3f0113ff 20020000 06021408 00000000
[ 126.779421] HCI Vendor Specific Registers 00000030: 00000000 00000000 02500000 00000000
[ 127.022870] UFS_UFS_DBG_RD_REG_OCSC 00000000: 00000000 00000000 00000000 00000000
[ 127.267364] UFS_UFS_DBG_RD_REG_OCSC 00000010: 00000000 00000000 00000000 00000000
[ 127.509680] UFS_UFS_DBG_RD_REG_OCSC 00000020: 00000000 00000000 00000000 00000000
[ 127.751360] UFS_UFS_DBG_RD_REG_OCSC 00000030: 00000000 00000000 00000000 00000000
[ 127.989556] UFS_UFS_DBG_RD_REG_OCSC 00000040: 00000000 00000000 00000000 00000000
[ 128.225467] UFS_UFS_DBG_RD_REG_OCSC 00000050: 00000000 00000000 00000000 00000000
[ 128.459069] UFS_UFS_DBG_RD_REG_OCSC 00000060: 00000000 00000000 00000000 00000000
[ 128.690664] UFS_UFS_DBG_RD_REG_OCSC 00000070: 00000000 00000000 00000000 00000000
[ 128.919665] UFS_UFS_DBG_RD_REG_OCSC 00000080: 00000000 00000000 00000000 00000000
[ 129.147282] UFS_UFS_DBG_RD_REG_OCSC 00000090: 00000000 00000000 00000000 00000000
[ 129.371907] UFS_UFS_DBG_RD_REG_OCSC 000000a0: 00000000 00000000 00200900 00000000
[ 129.594675] UFS_UFS_DBG_RD_EDTL_RAM 00000000: 00000000 00000000 00000000 00000000
[ 129.815206] UFS_UFS_DBG_RD_EDTL_RAM 00000010: 00000000 00000000 00000000 00000000
[ 130.033197] UFS_UFS_DBG_RD_EDTL_RAM 00000020: 00000000 00000000 00042000 00080000
[ 130.248984] UFS_UFS_DBG_RD_EDTL_RAM 00000030: 00000000 00000000 00000000 00000000
[ 130.462922] UFS_UFS_DBG_RD_EDTL_RAM 00000040: 00000000 00000000 00000000 00000000
[ 130.674566] UFS_UFS_DBG_RD_EDTL_RAM 00000050: 00000000 00000000 00000000 00000000
[ 130.883699] UFS_UFS_DBG_RD_EDTL_RAM 00000060: 00000000 00000000 00000000 00000000
[ 131.091041] UFS_UFS_DBG_RD_EDTL_RAM 00000070: 00000000 00000000 00000000 00000000
[ 131.298990] UFS_UFS_DBG_RD_DESC_RAM 00000000: 80000fff 00040687 40000fff 00021020
[ 131.505084] UFS_UFS_DBG_RD_DESC_RAM 00000010: c0000fff 00040687 19963525 00359120
[ 131.710684] UFS_UFS_DBG_RD_DESC_RAM 00000020: 00000fff 0004062e 66435341 00157455
[ 131.915438] UFS_UFS_DBG_RD_DESC_RAM 00000030: 80000fff 0004067d d4105c24 00231a1c
[ 132.119479] UFS_UFS_DBG_RD_DESC_RAM 00000040: 80000fff 00040623 5551bad5 000516d1
[ 132.321585] UFS_UFS_DBG_RD_DESC_RAM 00000050: 00000fff 00040687 37b55d21 002b5295
[ 132.521798] UFS_UFS_DBG_RD_DESC_RAM 00000060: c0000fff 00040687 e0d1560e 00190cf8
[ 132.721981] UFS_UFS_DBG_RD_DESC_RAM 00000070: 40000fff 00040688 556f5870 00290397
[ 132.920757] UFS_UFS_DBG_RD_DESC_RAM 00000080: 00000fff 0004067f 54d1415d 001ed331
[ 133.117748] UFS_UFS_DBG_RD_DESC_RAM 00000090: 80000fff 00040688 df628357 000dd471
[ 133.313320] UFS_UFS_DBG_RD_DESC_RAM 000000a0: 80000fff 0004090a c0000fff 0004090a
[ 133.507520] UFS_UFS_DBG_RD_DESC_RAM 000000b0: 00000fff 0004091b 40000fff 0004091b
[ 133.700839] UFS_UFS_DBG_RD_DESC_RAM 000000c0: c0000fff 0004067c c1c7d070 001f3c56
[ 133.892789] UFS_UFS_DBG_RD_DESC_RAM 000000d0: 80000fff 00040681 9c916145 00216c95
[ 134.083483] UFS_UFS_DBG_RD_DESC_RAM 000000e0: c0000fff 00040601 ce5071b1 000cd375
[ 134.273256] UFS_UFS_DBG_RD_DESC_RAM 000000f0: 00000fff 0004073a 44529135 00144475
[ 134.463647] UFS_UFS_DBG_RD_DESC_RAM 00000100: 80000fff 00040647 54494557 002662d8
[ 134.652976] UFS_UFS_DBG_RD_DESC_RAM 00000110: 80000fff 00040664 a8731961 00111d15
[ 134.840679] UFS_UFS_DBG_RD_DESC_RAM 00000120: 40000fff 00040652 b16d0738 0017694d
[ 135.028259] UFS_UFS_DBG_RD_DESC_RAM 00000130: 80000fff 00040664 1d136d60 00139655
[ 135.216168] UFS_UFS_DBG_RD_DESC_RAM 00000140: 40000fff 00040658 50f567dd 003dfc51
[ 135.401538] UFS_UFS_DBG_RD_DESC_RAM 00000150: 80000fff 00040499 6554c551 0024d954
[ 135.584468] UFS_UFS_DBG_RD_DESC_RAM 00000160: 00000fff 00040612 dd17c578 0035551c
[ 135.764983] UFS_UFS_DBG_RD_DESC_RAM 00000170: 80000fff 000404c3 84769d50 0015fa60
[ 135.943072] UFS_UFS_DBG_RD_DESC_RAM 00000180: 80000fff 0004067c 00000fff 000404bb
[ 136.120257] UFS_UFS_DBG_RD_DESC_RAM 00000190: 80000fff 0004072a c0000fff 000404e4
[ 136.297243] UFS_UFS_DBG_RD_DESC_RAM 000001a0: c0000fff 0004076c 00000fff 00040664
[ 136.474576] UFS_UFS_DBG_RD_DESC_RAM 000001b0: c0000fff 0005f57f c0000fff 000404bf
[ 136.648589] UFS_UFS_DBG_RD_DESC_RAM 000001c0: 80000fff 00040498 00000fff 0004060e
[ 136.823272] UFS_UFS_DBG_RD_DESC_RAM 000001d0: 80000fff 0004072a 00000fff 00040780
[ 136.999038] UFS_UFS_DBG_RD_DESC_RAM 000001e0: 80000fff 00040628 00000fff 0004073a
[ 137.175337] UFS_UFS_DBG_RD_DESC_RAM 000001f0: c0000fff 00040629 c0000fff 00040492
[ 137.351450] UFS_UFS_DBG_RD_PRDT_RAM 00000000: 04100000 0000fe10 10100000 0000fe10
[ 137.525376] UFS_UFS_DBG_RD_PRDT_RAM 00000010: 1c100000 0000fe10 28100000 0000fe10
[ 137.699068] UFS_UFS_DBG_RD_PRDT_RAM 00000020: 34100000 0000fe10 40100000 0000fe10
[ 137.869494] UFS_UFS_DBG_RD_PRDT_RAM 00000030: 4c100000 0000fe10 58100000 0000fe10
[ 138.036819] UFS_UFS_DBG_RD_PRDT_RAM 00000040: 64100000 0000fe10 70100000 0000fe10
[ 138.203442] UFS_UFS_DBG_RD_PRDT_RAM 00000050: 7fe00040 0000fe10 8820007e 0000fe10
[ 138.367863] UFS_UFS_DBG_RD_PRDT_RAM 00000060: 94100000 0000fe10 a0100000 0000fe10
[ 138.531560] UFS_UFS_DBG_RD_PRDT_RAM 00000070: ac100000 0000fe10 b8100000 0000fe10
[ 138.695427] UFS_UFS_DBG_RD_PRDT_RAM 00000080: c4100000 0000fe10 d0100000 0000fe10
[ 138.857888] UFS_UFS_DBG_RD_PRDT_RAM 00000090: dc100000 0000fe10 e8100000 0000fe10
[ 139.019904] UFS_UFS_DBG_RD_PRDT_RAM 000000a0: f4100000 0000fe10 00100000 0000fe11
[ 139.180553] UFS_UFS_DBG_RD_PRDT_RAM 000000b0: 0c100000 0000fe11 18100000 0000fe11
[ 139.338494] UFS_UFS_DBG_RD_PRDT_RAM 000000c0: 24100000 0000fe11 30100000 0000fe11
[ 139.492650] UFS_UFS_DBG_RD_PRDT_RAM 000000d0: 3c100000 0000fe11 48100000 0000fe11
[ 139.643934] UFS_UFS_DBG_RD_PRDT_RAM 000000e0: 54100000 0000fe11 60100000 0000fe11
[ 139.792567] UFS_UFS_DBG_RD_PRDT_RAM 000000f0: 6c100000 0000fe11 78100000 0000fe11
[ 139.937711] UFS_DBG_RD_REG_UAWM 00000000: 00000000 0000005e 00000000 0001fec0
[ 140.080933] UFS_DBG_RD_REG_UARM 00000000: 00000000 00000001 00000011 00000001
[ 140.223860] UFS_DBG_RD_REG_TXUC 00000000: 00000000 0000080b 00000000 00000000
[ 140.365478] UFS_DBG_RD_REG_TXUC 00000010: 01880000 fe108420 00000000 00000000
[ 140.506504] UFS_DBG_RD_REG_TXUC 00000020: 00000000 0000001f 00000000 00000000
[ 140.647317] UFS_DBG_RD_REG_TXUC 00000030: 004b0020 004b0000 00000000 00000004
[ 140.786597] UFS_DBG_RD_REG_TXUC 00000040: 00000080 00000000 03f84210 00000080
[ 140.924746] UFS_DBG_RD_REG_TXUC 00000050: fe108600 00000000 00000080 fe108800
[ 141.062655] UFS_DBG_RD_REG_TXUC 00000060: 00000000 00000000 00000000 00000000
[ 141.199714] UFS_DBG_RD_REG_TXUC 00000070: 000a0006 00000000 802b0000 0003b000
[ 141.335214] UFS_DBG_RD_REG_TXUC 00000080: 00000600 00000000 00070a00 00000000
[ 141.469084] UFS_DBG_RD_REG_TXUC 00000090: 01900054 00000000 00000000 00000000
[ 141.601430] UFS_DBG_RD_REG_TXUC 000000a0: 00000000 00000000 00000000 00000000
[ 141.731501] UFS_DBG_RD_REG_TXUC 000000b0: 00000001 00000040 00000000 0000000a
[ 141.859421] UFS_DBG_RD_REG_RXUC 00000000: 00000000 48004043 42000000 1000a318
[ 141.986555] UFS_DBG_RD_REG_RXUC 00000010: 00000000 0003c000 00001000 00000000
[ 142.112087] UFS_DBG_RD_REG_RXUC 00000020: 00000000 00000000 00000120 80040420
[ 142.237097] UFS_DBG_RD_REG_RXUC 00000030: 00f4f128 00000200 00001000 00000000
[ 142.359317] UFS_DBG_RD_REG_RXUC 00000040: 00000000 00000024 00f4f128 0e480000
[ 142.477794] UFS_DBG_RD_REG_RXUC 00000050: 00060000 00000000 00000000 00000001
[ 142.596477] UFS_DBG_RD_REG_RXUC 00000060: 00000040 00000000 00000004
[ 142.715272] UFS_DBG_RD_REG_DFC 00000000: 00000000 002c163e fe108800 00000800
[ 142.835213] UFS_DBG_RD_REG_DFC 00000010: 00004824 fe1125f0 00000010 00000000
[ 142.955774] UFS_DBG_RD_REG_DFC 00000020: 00000000 46d00000 00000102 fffff3ff
[ 143.077055] UFS_DBG_RD_REG_DFC 00000030: 00f00000 00000000 00000000 00000000
[ 143.198751] UFS_DBG_RD_REG_DFC 00000040: fffff3ff 00000000 00000000
[ 143.320087] UFS_DBG_RD_REG_TRLUT 00000000: 00000000 00015f7d 00000b00 00000005
[ 143.443073] UFS_DBG_RD_REG_TRLUT 00000010: 00000105 00000201 00000301 00000401
[ 143.566790] UFS_DBG_RD_REG_TRLUT 00000020: 00000501 00000601 00000705 00000800
[ 143.688212] UFS_DBG_RD_REG_TRLUT 00000030: 00000900 00010a00 00010b00 00000c05
[ 143.809771] UFS_DBG_RD_REG_TRLUT 00000040: 00000d05 00000e05 00000f05 00001004
[ 143.931601] UFS_DBG_RD_REG_TRLUT 00000050: 00001104 00001204 00001304 00001404
[ 144.053695] UFS_DBG_RD_REG_TRLUT 00000060: 00001504 00001604 00001704 00001800
[ 144.175751] UFS_DBG_RD_REG_TRLUT 00000070: 00001900 00001a00 00001b00 00001c00
[ 144.298661] UFS_DBG_RD_REG_TRLUT 00000080: 00001d00 00001e00
[ 144.379883] ufshcd-qcom 624000.ufshc: ufshcd_abort: Device abort task at tag 12
[ 144.420604] UFS_DBG_RD_REG_TMRLUT 00000000: 00000000 00000001 00000000 00000000
[ 144.420909] UFS_DBG_RD_REG_TMRLUT 00000010: 00000000 00000000 00000000 00000000
[ 144.547617] sd 0:0:0:0: [sda] tag#12 CDB: opcode=0x2a 2a 00 00 00 87 dc 00 00 02 00
[ 144.673115] UFS_DBG_RD_REG_TMRLUT 00000020: 00000000
[ 144.673529] ufshcd-qcom 624000.ufshc: UPIU[10] - issue time 113455849 us
[ 144.673872] ufshcd-qcom 624000.ufshc: UPIU[10] - complete time 0 us
[ 144.799766] host_regs: 00000000: 0107001f 00000000 00010100 00000000
[ 144.927599] ufshcd-qcom 624000.ufshc: UPIU[10] - Transfer Request Descriptor phys@0x100f4f140
[ 144.927953] UPIU TRD: 00000000: 13000000 00000000 0000000f 00000000
[ 145.057473] host_regs: 00000010: 01000000 00010217 00000000 00000000
[ 145.188931] UPIU TRD: 00000010: fe107800 00000000 00800080 0100007e
[ 145.189275] ufshcd-qcom 624000.ufshc: UPIU[10] - Request UPIU phys@0xfe107800
[ 145.321002] host_regs: 00000020: 00000000 00030e75 00000000 00000000
[ 145.454548] UPIU REQ: 00000000: 0a002001 00000000 00000000 00e00700
[ 145.454853] UPIU REQ: 00000010: 0000002a 0000de86 0000007e 00000000
[ 145.455192] ufshcd-qcom 624000.ufshc: UPIU[10] - Response UPIU phys@0xfe107a00
[ 145.592478] host_regs: 00000030: 0000010f 00000001 00000000 00000000
[ 145.730528] UPIU RSP: 00000000: 00000000 00000000 00000000 00000000
[ 145.730909] UPIU RSP: 00000010: 00000000 00000000 00000000 00000000
[ 145.869558] host_regs: 00000040: 00000000 00000000 00000000 00000000
[ 146.007648] UPIU RSP: 00000020: 00000000 00000000 00000000 00000000
[ 146.007953] UPIU RSP: 00000030: 00000000
[ 146.149114] host_regs: 00000050: 00f4f000 00000001 00001c00 00000000
[ 146.289166] ufshcd-qcom 624000.ufshc: UPIU[10] - PRDT - 126 entries phys@0xfe107c00
[ 146.289495] ufshcd-qcom 624000.ufshc: UPIU[11] - issue time 113459063 us
[ 146.430775] host_regs: 00000060: 00000001 ffffffff 00000000 00000000
[ 146.571358] ufshcd-qcom 624000.ufshc: UPIU[11] - complete time 0 us
[ 146.571687] ufshcd-qcom 624000.ufshc: UPIU[11] - Transfer Request Descriptor phys@0x100f4f160
[ 146.714702] host_regs: 00000070: 00f50000 00000001 00000000 00000000
[ 146.857432] UPIU TRD: 00000000: 13000000 00000000 0000000f 00000000
[ 146.857745] UPIU TRD: 00000010: fe108400 00000000 00800080 01000080
[ 147.001449] host_regs: 00000080: 00000001 00000000 00000000 00000000
[ 147.144936] ufshcd-qcom 624000.ufshc: UPIU[11] - Request UPIU phys@0xfe108400
[ 147.145276] UPIU REQ: 00000000: 0b002001 00000000 00000000 00000800
[ 147.290445] host_regs: 00000090: 00000002 d0020000 00000000 00000096
[ 147.435613] UPIU REQ: 00000010: 0000002a 00005c87 00000080 00000000
[ 147.435968] ufshcd-qcom 624000.ufshc: UPIU[11] - Response UPIU phys@0xfe108600
[ 147.581455] ufshcd-qcom 624000.ufshc: pa_err[0] = 0x80000010 at 113794938 us
[ 147.729752] UPIU RSP: 00000000: 00000000 00000000 00000000 00000000
[ 147.730623] UPIU RSP: 00000010: 00000000 00000000 00000000 00000000
[ 147.882526] ufshcd-qcom 624000.ufshc: dl_err[3] = 0x80000002 at 147409028 us
[ 148.034857] UPIU RSP: 00000020: 00000000 00000000 00000000 00000000
[ 148.035126] UPIU RSP: 00000030: 00000000
[ 148.190937] ufshcd-qcom 624000.ufshc: dl_err[0] = 0x80000002 at 147736702 us
[ 148.346792] ufshcd-qcom 624000.ufshc: UPIU[11] - PRDT - 128 entries phys@0xfe108800
[ 148.348748] ufshcd-qcom 624000.ufshc: dl_err[2] = 0x80000002 at 147867771 us
[ 148.510000] ufshcd-qcom 624000.ufshc: UPIU[12] - issue time 113459748 us
[ 148.511827] ufshcd-qcom 624000.ufshc: dl_err[4] = 0x80000002 at 147998841 us
[ 148.674508] ufshcd-qcom 624000.ufshc: UPIU[12] - complete time 0 us
[ 148.675964] ufshcd-qcom 624000.ufshc: dl_err[6] = 0x80000002 at 148129910 us
[ 148.843480] ufshcd-qcom 624000.ufshc: UPIU[12] - Transfer Request Descriptor phys@0x100f4f180
[ 148.845114] ufshcd-qcom 624000.ufshc: dl_err[0] = 0x80000002 at 148499197 us
[ 148.845123] ufshcd-qcom 624000.ufshc: dl_err[1] = 0x80000002 at 148663336 us
[ 148.845128] ufshcd-qcom 624000.ufshc: dl_err[2] = 0x80000002 at 148832566 us
[ 148.845134] ufshcd-qcom 624000.ufshc: No record of nl_err
[ 148.845138] ufshcd-qcom 624000.ufshc: No record of tl_err
[ 148.845142] ufshcd-qcom 624000.ufshc: No record of dme_err
[ 148.845146] ufshcd-qcom 624000.ufshc: No record of auto_hibern8_err
[ 148.845151] ufshcd-qcom 624000.ufshc: No record of fatal_err
[ 148.845155] ufshcd-qcom 624000.ufshc: No record of link_startup_fail
[ 148.845160] ufshcd-qcom 624000.ufshc: No record of resume_fail
[ 148.845286] ufshcd-qcom 624000.ufshc: No record of suspend_fail
[ 149.015420] UPIU TRD: 00000000: 13000000 00000000 0000000f 00000000
[ 149.017194] ufshcd-qcom 624000.ufshc: dev_reset[0] = 0x0 at 13117269 us
[ 149.017200] ufshcd-qcom 624000.ufshc: No record of host_reset
[ 149.017205] ufshcd-qcom 624000.ufshc: task_abort[0] = 0x0 at 144789360 us
[ 149.017339] HCI Vendor Specific Registers 00000000: 000000c8 00000000 00000000 00000000
[ 149.191307] UPIU TRD: 00000010: fe109000 00000000 00800080 01000002
[ 149.192250] HCI Vendor Specific Registers 00000010: 00000000 00000000 00000000 5c5c052c
[ 149.366851] ufshcd-qcom 624000.ufshc: UPIU[12] - Request UPIU phys@0xfe109000
[ 149.368676] HCI Vendor Specific Registers 00000020: 3f0113ff 20020000 06021408 00000000
[ 149.368683] HCI Vendor Specific Registers 00000030: 00000000 00000000 02500000 00000000
[ 149.368806] UFS_UFS_DBG_RD_REG_OCSC 00000000: 00000000 00000000 00000000 00000000
[ 149.544500] UPIU REQ: 00000000: 0c002001 00000000 00000000 00200000
[ 149.546401] UFS_UFS_DBG_RD_REG_OCSC 00000010: 00000000 00000000 00000000 00000000
[ 149.546408] UFS_UFS_DBG_RD_REG_OCSC 00000020: 00000000 00000000 00000000 00000000
[ 149.546412] UFS_UFS_DBG_RD_REG_OCSC 00000030: 00000000 00000000 00000000 00000000
[ 149.546417] UFS_UFS_DBG_RD_REG_OCSC 00000040: 00000000 00000000 00000000 00000000
[ 149.546421] UFS_UFS_DBG_RD_REG_OCSC 00000050: 00000000 00000000 00000000 00000000
[ 149.546425] UFS_UFS_DBG_RD_REG_OCSC 00000060: 00000000 00000000 00000000 00000000
[ 149.546430] UFS_UFS_DBG_RD_REG_OCSC 00000070: 00000000 00000000 00000000 00000000
[ 149.546434] UFS_UFS_DBG_RD_REG_OCSC 00000080: 00000000 00000000 00000000 00000000
[ 149.546438] UFS_UFS_DBG_RD_REG_OCSC 00000090: 00000000 00000000 00000000 00000000
[ 149.546443] UFS_UFS_DBG_RD_REG_OCSC 000000a0: 00000000 00000000 00200900 00000000
[ 149.546469] UFS_UFS_DBG_RD_EDTL_RAM 00000000: 00000000 00000000 00000000 00000000
[ 149.546473] UFS_UFS_DBG_RD_EDTL_RAM 00000010: 00000000 00000000 00000000 00000000
[ 149.546478] UFS_UFS_DBG_RD_EDTL_RAM 00000020: 00000000 00000000 00042000 00080000
[ 149.546482] UFS_UFS_DBG_RD_EDTL_RAM 00000030: 00000000 00000000 00000000 00000000
[ 149.546486] UFS_UFS_DBG_RD_EDTL_RAM 00000040: 00000000 00000000 00000000 00000000
[ 149.546490] UFS_UFS_DBG_RD_EDTL_RAM 00000050: 00000000 00000000 00000000 00000000
[ 149.546495] UFS_UFS_DBG_RD_EDTL_RAM 00000060: 00000000 00000000 00000000 00000000
[ 149.546499] UFS_UFS_DBG_RD_EDTL_RAM 00000070: 00000000 00000000 00000000 00000000
[ 149.546581] UFS_UFS_DBG_RD_DESC_RAM 00000000: 80000fff 00040687 40000fff 00021020
[ 149.546586] UFS_UFS_DBG_RD_DESC_RAM 00000010: c0000fff 00040687 19963525 00359120
[ 149.546590] UFS_UFS_DBG_RD_DESC_RAM 00000020: 00000fff 0004062e 66435341 00157455
[ 149.546595] UFS_UFS_DBG_RD_DESC_RAM 00000030: 80000fff 0004067d d4105c24 00231a1c
[ 149.546599] UFS_UFS_DBG_RD_DESC_RAM 00000040: 80000fff 00040623 5551bad5 000516d1
[ 149.546603] UFS_UFS_DBG_RD_DESC_RAM 00000050: 00000fff 00040687 37b55d21 002b5295
[ 149.546608] UFS_UFS_DBG_RD_DESC_RAM 00000060: c0000fff 00040687 e0d1560e 00190cf8
[ 149.546612] UFS_UFS_DBG_RD_DESC_RAM 00000070: 40000fff 00040688 556f5870 00290397
[ 149.546616] UFS_UFS_DBG_RD_DESC_RAM 00000080: 00000fff 0004067f 54d1415d 001ed331
[ 149.546621] UFS_UFS_DBG_RD_DESC_RAM 00000090: 80000fff 00040688 df628357 000dd471
[ 149.546629] UFS_UFS_DBG_RD_DESC_RAM 000000a0: 80000fff 0004090a c0000fff 0004090a
[ 149.546633] UFS_UFS_DBG_RD_DESC_RAM 000000b0: 00000fff 0004091b 40000fff 0004091b
[ 149.546638] UFS_UFS_DBG_RD_DESC_RAM 000000c0: c0000fff 0004067c c1c7d070 001f3c56
[ 149.546642] UFS_UFS_DBG_RD_DESC_RAM 000000d0: 80000fff 00040681 9c916145 00216c95
[ 149.546646] UFS_UFS_DBG_RD_DESC_RAM 000000e0: c0000fff 00040601 ce5071b1 000cd375
[ 149.546651] UFS_UFS_DBG_RD_DESC_RAM 000000f0: 00000fff 0004073a 44529135 00144475
[ 149.546655] UFS_UFS_DBG_RD_DESC_RAM 00000100: 80000fff 00040647 54494557 002662d8
[ 149.546660] UFS_UFS_DBG_RD_DESC_RAM 00000110: 80000fff 00040664 a8731961 00111d15
[ 149.546664] UFS_UFS_DBG_RD_DESC_RAM 00000120: 40000fff 00040652 b16d0738 0017694d
[ 149.546668] UFS_UFS_DBG_RD_DESC_RAM 00000130: 80000fff 00040664 1d136d60 00139655
[ 149.546673] UFS_UFS_DBG_RD_DESC_RAM 00000140: 40000fff 00040658 50f567dd 003dfc51
[ 149.546677] UFS_UFS_DBG_RD_DESC_RAM 00000150: 80000fff 00040499 6554c551 0024d954
[ 149.546681] UFS_UFS_DBG_RD_DESC_RAM 00000160: 00000fff 00040612 dd17c578 0035551c
[ 149.546686] UFS_UFS_DBG_RD_DESC_RAM 00000170: 80000fff 000404c3 84769d50 0015fa60
[ 149.546690] UFS_UFS_DBG_RD_DESC_RAM 00000180: 80000fff 0004067c 00000fff 000404bb
[ 149.546694] UFS_UFS_DBG_RD_DESC_RAM 00000190: 80000fff 0004072a c0000fff 000404e4
[ 149.546699] UFS_UFS_DBG_RD_DESC_RAM 000001a0: c0000fff 0004076c 00000fff 00040664
[ 149.546703] UFS_UFS_DBG_RD_DESC_RAM 000001b0: c0000fff 0005f57f c0000fff 000404bf
[ 149.546707] UFS_UFS_DBG_RD_DESC_RAM 000001c0: 80000fff 00040498 00000fff 0004060e
[ 149.546712] UFS_UFS_DBG_RD_DESC_RAM 000001d0: 80000fff 0004072a 00000fff 00040780
[ 149.546716] UFS_UFS_DBG_RD_DESC_RAM 000001e0: 80000fff 00040628 00000fff 0004073a
[ 149.546722] UFS_UFS_DBG_RD_DESC_RAM 000001f0: c0000fff 00040629 c0000fff 00040492
[ 149.546866] UFS_UFS_DBG_RD_PRDT_RAM 00000000: 04100000 0000fe10 10100000 0000fe10
[ 149.546871] UFS_UFS_DBG_RD_PRDT_RAM 00000010: 1c100000 0000fe10 28100000 0000fe10
[ 149.546876] UFS_UFS_DBG_RD_PRDT_RAM 00000020: 34100000 0000fe10 40100000 0000fe10
[ 149.546882] UFS_UFS_DBG_RD_PRDT_RAM 00000030: 4c100000 0000fe10 58100000 0000fe10
[ 149.723062] UPIU REQ: 00000010: 0000002a 0000dc87 00000002 00000000
[ 149.725028] UFS_UFS_DBG_RD_PRDT_RAM 00000040: 64100000 0000fe10 70100000 0000fe10
[ 149.725039] UFS_UFS_DBG_RD_PRDT_RAM 00000050: 7fe00040 0000fe10 8820007e 0000fe10
[ 149.725046] UFS_UFS_DBG_RD_PRDT_RAM 00000060: 94100000 0000fe10 a0100000 0000fe10
[ 149.725053] UFS_UFS_DBG_RD_PRDT_RAM 00000070: ac100000 0000fe10 b8100000 0000fe10
[ 149.725061] UFS_UFS_DBG_RD_PRDT_RAM 00000080: c4100000 0000fe10 d0100000 0000fe10
[ 149.725069] UFS_UFS_DBG_RD_PRDT_RAM 00000090: dc100000 0000fe10 e8100000 0000fe10
[ 149.725076] UFS_UFS_DBG_RD_PRDT_RAM 000000a0: f4100000 0000fe10 00100000 0000fe11
[ 149.725084] UFS_UFS_DBG_RD_PRDT_RAM 000000b0: 0c100000 0000fe11 18100000 0000fe11
[ 149.725093] UFS_UFS_DBG_RD_PRDT_RAM 000000c0: 24100000 0000fe11 30100000 0000fe11
[ 149.725101] UFS_UFS_DBG_RD_PRDT_RAM 000000d0: 3c100000 0000fe11 48100000 0000fe11
[ 149.725108] UFS_UFS_DBG_RD_PRDT_RAM 000000e0: 54100000 0000fe11 60100000 0000fe11
[ 149.725115] UFS_UFS_DBG_RD_PRDT_RAM 000000f0: 6c100000 0000fe11 78100000 0000fe11
[ 149.725246] UFS_DBG_RD_REG_UAWM 00000000: 00000000 0000005e 00000000 0001fec0
[ 149.906604] ufshcd-qcom 624000.ufshc: UPIU[12] - Response UPIU phys@0xfe109200
[ 149.908298] UFS_DBG_RD_REG_UARM 00000000: 00000000 00000001 00000011 00000001
[ 150.090936] UPIU RSP: 00000000: 00000000 00000000 00000000 00000000
[ 150.093093] UFS_DBG_RD_REG_TXUC 00000000: 00000000 0000080b 00000000 00000000
[ 150.276959] UPIU RSP: 00000010: 00000000 00000000 00000000 00000000
[ 150.279005] UFS_DBG_RD_REG_TXUC 00000010: 01880000 fe108420 00000000 00000000
[ 150.279012] UFS_DBG_RD_REG_TXUC 00000020: 00000000 0000001f 00000000 00000000
[ 150.279016] UFS_DBG_RD_REG_TXUC 00000030: 004b0020 004b0000 00000000 00000004
[ 150.279021] UFS_DBG_RD_REG_TXUC 00000040: 00000080 00000000 03f84210 00000080
[ 150.279025] UFS_DBG_RD_REG_TXUC 00000050: fe108600 00000000 00000080 fe108800
[ 150.279029] UFS_DBG_RD_REG_TXUC 00000060: 00000000 00000000 00000000 00000000
[ 150.279034] UFS_DBG_RD_REG_TXUC 00000070: 000a0006 00000000 802b0000 0003b000
[ 150.279048] UFS_DBG_RD_REG_TXUC 00000080: 00000600 00000000 00070a00 00000000
[ 150.279052] UFS_DBG_RD_REG_TXUC 00000090: 01900054 00000000 00000000 00000000
[ 150.279056] UFS_DBG_RD_REG_TXUC 000000a0: 00000000 00000000 00000000 00000000
[ 150.279061] UFS_DBG_RD_REG_TXUC 000000b0: 00000001 00000040 00000000 0000000a
[ 150.279082] UFS_DBG_RD_REG_RXUC 00000000: 00000000 48004043 42000000 1000a318
[ 150.279086] UFS_DBG_RD_REG_RXUC 00000010: 00000000 0003c000 00001000 00000000
[ 150.279090] UFS_DBG_RD_REG_RXUC 00000020: 00000000 00000000 00000120 80040420
[ 150.279094] UFS_DBG_RD_REG_RXUC 00000030: 00f4f128 00000200 00001000 00000000
[ 150.279098] UFS_DBG_RD_REG_RXUC 00000040: 00000000 00000024 00f4f128 0e480000
[ 150.279103] UFS_DBG_RD_REG_RXUC 00000050: 00060000 00000000 00000000 00000001
[ 150.279107] UFS_DBG_RD_REG_RXUC 00000060: 00000040 00000000 00000004
[ 150.279123] UFS_DBG_RD_REG_DFC 00000000: 00000000 002c163e fe108800 00000800
[ 150.279127] UFS_DBG_RD_REG_DFC 00000010: 00004824 fe1125f0 00000010 00000000
[ 150.279131] UFS_DBG_RD_REG_DFC 00000020: 00000000 46d00000 00000102 fffff3ff
[ 150.279135] UFS_DBG_RD_REG_DFC 00000030: 00f00000 00000000 00000000 00000000
[ 150.279150] UFS_DBG_RD_REG_DFC 00000040: fffff3ff 00000000 00000000
[ 150.279175] UFS_DBG_RD_REG_TRLUT 00000000: 00000000 00015f7d 00000b00 00000005
[ 150.279180] UFS_DBG_RD_REG_TRLUT 00000010: 00000105 00000201 00000301 00000401
[ 150.279184] UFS_DBG_RD_REG_TRLUT 00000020: 00000501 00000601 00000705 00000800
[ 150.279189] UFS_DBG_RD_REG_TRLUT 00000030: 00000900 00010a00 00010b00 00000c05
[ 150.279193] UFS_DBG_RD_REG_TRLUT 00000040: 00000d05 00000e05 00000f05 00001004
[ 150.279198] UFS_DBG_RD_REG_TRLUT 00000050: 00001104 00001204 00001304 00001404
[ 150.279202] UFS_DBG_RD_REG_TRLUT 00000060: 00001504 00001604 00001704 00001800
[ 150.279206] UFS_DBG_RD_REG_TRLUT 00000070: 00001900 00001a00 00001b00 00001c00
[ 150.279210] UFS_DBG_RD_REG_TRLUT 00000080: 00001d00 00001e00
[ 150.279223] UFS_DBG_RD_REG_TMRLUT 00000000: 00000000 00000001 00000000 00000000
[ 150.279232] UFS_DBG_RD_REG_TMRLUT 00000010: 00000000 00000000 00000000 00000000
[ 150.279236] UFS_DBG_RD_REG_TMRLUT 00000020: 00000000
[ 150.279247] ufshcd-qcom 624000.ufshc: UFS Host state=3
[ 150.279253] ufshcd-qcom 624000.ufshc: outstanding reqs=0x1c00 tasks=0x0
[ 150.279257] ufshcd-qcom 624000.ufshc: saved_err=0x4, saved_uic_err=0x45
[ 150.279261] ufshcd-qcom 624000.ufshc: Device power mode=1, UIC link state=1
[ 150.279265] ufshcd-qcom 624000.ufshc: PM in progress=0, sys. suspended=0
[ 150.279269] ufshcd-qcom 624000.ufshc: Auto BKOPS=0, Host self-block=1
[ 150.279273] ufshcd-qcom 624000.ufshc: Clk gate=1
[ 150.279279] ufshcd-qcom 624000.ufshc: last_hibern8_exit_tstamp at 0 us, hibern8_exit_cnt=0
[ 150.279283] ufshcd-qcom 624000.ufshc: last intr at 150266167 us, last intr status=0x4
[ 150.279288] ufshcd-qcom 624000.ufshc: error handling flags=0x1, req. abort count=0
[ 150.279293] ufshcd-qcom 624000.ufshc: hba->ufs_version=0x200, Host capabilities=0x107001f, caps=0x10f
[ 150.279297] ufshcd-qcom 624000.ufshc: quirks=0x20, dev. quirks=0xc4
[ 150.279304] ufshcd-qcom 624000.ufshc: UFS dev info: SAMSUNG KLUCG4J1CB-B0B1 rev 0800
[ 150.279311] ufshcd-qcom 624000.ufshc: clk: core_clk_src, rate: 100000000
[ 150.279321] ufshcd-qcom 624000.ufshc: clk: core_clk_unipro_src, rate: 150000000
[ 150.279333] ufshcd-qcom 624000.ufshc: ufshcd_print_pwr_info:[RX, TX]: gear=[1, 1], lane[1, 1], pwr[FAST MODE, FAST MODE], rate = 2
[ 150.279341] ufshcd-qcom 624000.ufshc: UPIU[12] - issue time 113459748 us
[ 150.279483] ufshcd-qcom 624000.ufshc: UPIU[12] - complete time 0 us
[ 150.279488] ufshcd-qcom 624000.ufshc: UPIU[12] - Transfer Request Descriptor phys@0x100f4f180
[ 150.279495] UPIU TRD: 00000000: 13000000 00000000 0000000f 00000000
[ 150.279501] UPIU TRD: 00000010: fe109000 00000000 00800080 01000002
[ 150.279506] ufshcd-qcom 624000.ufshc: UPIU[12] - Request UPIU phys@0xfe109000
[ 150.279512] UPIU REQ: 00000000: 0c002001 00000000 00000000 00200000
[ 150.279518] UPIU REQ: 00000010: 0000002a 0000dc87 00000002 00000000
[ 150.279524] ufshcd-qcom 624000.ufshc: UPIU[12] - Response UPIU phys@0xfe109200
[ 150.466783] UPIU RSP: 00000020: 00000000 00000000 00000000 00000000
[ 150.468895] UPIU RSP: 00000000: 00000000 00000000 00000000 00000000
[ 150.655769] UPIU RSP: 00000030: 00000000
[ 150.657913] UPIU RSP: 00000010: 00000000 00000000 00000000 00000000
[ 150.657920] UPIU RSP: 00000020: 00000000 00000000 00000000 00000000
[ 150.657924] UPIU RSP: 00000030: 00000000
[ 150.657931] ufshcd-qcom 624000.ufshc: UPIU[12] - PRDT - 2 entries phys@0xfe109400
[ 150.657936] UPIU PRDT: 00000000: 024ec000 00000001 00000000 00000fff
[ 150.657941] UPIU PRDT: 00000010: 024ed000 00000001 00000000 00000fff
[ 150.657961] ------------[ cut here ]------------
[ 150.657976] WARNING: CPU: 0 PID: 117 at block/blk-core.c:633 blk_get_request+0x70/0x80
[ 150.657979] Modules linked in:
[ 150.657991] CPU: 0 PID: 117 Comm: kworker/u8:2 Not tainted 5.10.0-rc5-00038-g8bf1a3dfb7a1-dirty #131
[ 150.657994] Hardware name: Xiaomi Mi Note 2 (DT)
[ 150.658013] Workqueue: scsi_tmf_0 scmd_eh_abort_handler
[ 150.658021] pstate: 00000005 (nzcv daif -PAN -UAO -TCO BTYPE=--)
[ 150.658027] pc : blk_get_request+0x70/0x80
[ 150.658035] lr : __ufshcd_issue_tm_cmd+0x6c/0x30c
[ 150.658037] sp : ffff80001249bb50
[ 150.658041] x29: ffff80001249bb50 x28: ffff0000808a63c0
[ 150.658050] x27: ffff80001249bbf8 x26: 0000000000001000
[ 150.658058] x25: ffff0000808a63c0 x24: ffff000080374890
[ 150.658065] x23: ffff800011217058 x22: ffff000080374890
[ 150.658074] x21: ffff80001249bd17 x20: ffff000080e1a698
[ 150.658081] x19: ffff000080374890 x18: ffff800011d826f0
[ 150.658089] x17: 00000000ffffffff x16: ffff8000145e2180
[ 150.658097] x15: 0000000000000040 x14: 0000000000000008
[ 150.658105] x13: ffff800012033a50 x12: fffffffffffce107
[ 150.658113] x11: ffff800011d82708 x10: fffffffffffe0000
[ 150.658120] x9 : ffff80001249bb70 x8 : 00000f0000000001
[ 150.658129] x7 : 0000000000000004 x6 : 000000000c000000
[ 150.658136] x5 : 0000000000000000 x4 : 0000000000008000
[ 150.658144] x3 : ffff000080374000 x2 : 0000000000000002
[ 150.658151] x1 : 0000000000000023 x0 : 00000000fffffff6
[ 150.658160] Call trace:
[ 150.658166] blk_get_request+0x70/0x80
[ 150.658171] __ufshcd_issue_tm_cmd+0x6c/0x30c
[ 150.658175] ufshcd_issue_tm_cmd+0x74/0xf0
[ 150.658180] ufshcd_try_to_abort_task+0x84/0x210
[ 150.658184] ufshcd_abort+0x2d4/0x2f0
[ 150.658188] scmd_eh_abort_handler+0x74/0x110
[ 150.658197] process_one_work+0x1cc/0x350
[ 150.658202] worker_thread+0x13c/0x470
[ 150.658208] kthread+0x154/0x160
[ 150.658215] ret_from_fork+0x10/0x30
[ 150.658219] ---[ end trace 0a4bb985405d86cd ]---
[ 150.658357] ------------[ cut here ]------------
[ 150.658369] WARNING: CPU: 0 PID: 117 at block/blk-mq-tag.c:100 blk_mq_get_tag+0x2d8/0x304
[ 150.844508] ufshcd-qcom 624000.ufshc: UPIU[12] - PRDT - 2 entries phys@0xfe109400
[ 150.846283] Modules linked in:
[ 150.846293] CPU: 0 PID: 117 Comm: kworker/u8:2 Tainted: G W 5.10.0-rc5-00038-g8bf1a3dfb7a1-dirty #131
[ 150.846296] Hardware name: Xiaomi Mi Note 2 (DT)
[ 150.846308] Workqueue: scsi_tmf_0 scmd_eh_abort_handler
[ 150.846315] pstate: 60000005 (nZCv daif -PAN -UAO -TCO BTYPE=--)
[ 150.846323] pc : blk_mq_get_tag+0x2d8/0x304
[ 150.846328] lr : __blk_mq_alloc_request+0x60/0x140
[ 150.846331] sp : ffff80001249ba20
[ 150.846334] x29: ffff80001249ba20 x28: ffff0000808a63c0
[ 150.846342] x27: ffff80001249bbf8 x26: ffff000080dcfd00
[ 150.846350] x25: ffff0000808a63c0 x24: ffff000080374890
[ 150.846358] x23: ffff000080e1a698 x22: ffff0000808a63c0
[ 150.846365] x21: ffff800011d69a40 x20: ffff8000118d4000
[ 150.846373] x19: ffff80001249bb20 x18: ffff800011d826f0
[ 150.846381] x17: 00000000ffffffff x16: ffff8000145e2180
[ 150.846389] x15: 0000000000000040 x14: 0000000000000008
[ 150.846397] x13: ffff800012033a50 x12: fffffffffffce107
[ 150.846404] x11: ffff800011d82708 x10: fffffffffffe0000
[ 150.846412] x9 : ffff80001249bb70 x8 : 00000f0000000001
[ 150.846420] x7 : 0000000000000004 x6 : 000000000c000000
[ 150.846427] x5 : 0000000000000000 x4 : 0000000000000002
[ 150.846435] x3 : ffff000081021000 x2 : ffff80001249baa8
[ 150.846443] x1 : ffff0000808a63c0 x0 : 0000000000000000
[ 150.846450] Call trace:
[ 150.846457] blk_mq_get_tag+0x2d8/0x304
[ 150.846462] __blk_mq_alloc_request+0x60/0x140
[ 150.846466] blk_mq_alloc_request+0x78/0xac
[ 150.846472] blk_get_request+0x2c/0x80
[ 150.846478] __ufshcd_issue_tm_cmd+0x6c/0x30c
[ 150.846483] ufshcd_issue_tm_cmd+0x74/0xf0
[ 150.846487] ufshcd_try_to_abort_task+0x84/0x210
[ 150.846491] ufshcd_abort+0x2d4/0x2f0
[ 150.846496] scmd_eh_abort_handler+0x74/0x110
[ 150.846503] process_one_work+0x1cc/0x350
[ 150.846508] worker_thread+0x13c/0x470
[ 150.846513] kthread+0x154/0x160
[ 150.846518] ret_from_fork+0x10/0x30
[ 150.846522] ---[ end trace 0a4bb985405d86ce ]---
[ 191.779671] ufshcd-qcom 624000.ufshc: ufshcd_print_pwr_info:[RX, TX]: gear=[1, 1], lane[1, 1], pwr[SLOWAUTO_MODE, SLOWAUTO_MODE], rate = 0
[ 191.993190] ufshcd-qcom 624000.ufshc: ufshcd_print_pwr_info:[RX, TX]: gear=[3, 3], lane[1, 1], pwr[FAST MODE, FAST MODE], rate = 2
I had to disable this part of ufshcd.c:6064 since it floods dmesg with repeated output:
/* dump controller state before resetting */
if ((hba->saved_err & (INT_FATAL_ERRORS)) ||
(hba->saved_uic_err &&
(hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
__func__, hba->saved_err,
hba->saved_uic_err);
ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE,
"host_regs: ");
ufshcd_print_pwr_info(hba);
}
‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐
On Thursday, October 29, 2020 3:46 PM, Yassine Oudjana <y.oudjana@protonmail.com> wrote:
> I'm trying to get the mainline kernel working on a Xiaomi Mi Note 2 with MSM8996Pro and
> Samsung KLUCG4J1CB-B0B1, but I'm getting UFSHCD_UIC_DL_TCx_REPLAY_ERROR after some write operations.
>
> I'm not certain what kind of write is causing it, but it never happens when root is set to be
> mounted read-only, so I don't think it's reading that causes it. However, I was able to write dmesg
> without any errors by using an initramfs hook, except that is before I get the error.
>
> As soon as it happens, it never recovers from it. It tries to reset, but it just gets the error
> again after resetting.
>
> UFS reset isn't defined currently in the msm8996 device tree, so I defined it:
>
> --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> @@ -1100,6 +1100,8 @@ ufshc: ufshc@624000 {
>
> lanes-per-direction = <1>;
>
> #reset-cells = <1>;
>
>
> - resets = <&gcc GCC_UFS_BCR>;
>
>
> - reset-names = "rst";
> status = "disabled";
>
>
>
> ufs_variant {
>
> When I did that, PHY poweron started to fail (qcom_qmp_phy_power_on in the PHY driver was
> timing out). I looked into the downstream kernel for this device, and found out that it calibrates
> the PHY while the reset is asserted. So I did this and was able to "fix"(?) it:
>
> --- a/drivers/scsi/ufs/ufs-qcom.c
> +++ b/drivers/scsi/ufs/ufs-qcom.c
> @@ -292,11 +294,9 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
> bool is_rate_B = (UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B)
> ? true : false;
>
> - /* Reset UFS Host Controller and PHY */
>
>
> - ret = ufs_qcom_host_reset(hba);
>
>
> - if (ret)
>
>
> - dev_warn(hba->dev, "%s: host reset returned %d\\n",
>
>
> - __func__, ret);
>
>
>
> - ufs_qcom_assert_reset(hba);
>
>
> - /* provide 1ms delay to let the reset pulse propagate. */
>
>
> - usleep_range(1000, 1100);
>
>
>
> if (is_rate_B)
> phy_set_mode(phy, PHY_MODE_UFS_HS_B);
> @@ -309,11 +309,19 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
> goto out;
> }
>
> - ufs_qcom_deassert_reset(hba);
>
>
> - /*
>
>
> - * after reset deassertion, phy will need all ref clocks,
>
>
> - * voltage, current to settle down before starting serdes.
>
>
> - */
>
>
> - usleep_range(1000, 1100);
>
>
> - /* power on phy - start serdes and phy's power and clocks */
> ret = phy_power_on(phy);
>
>
>
> Note that using reset_control_de/assert(host->core_reset) instead of ufs_qcom_de/assert_reset(hba)
> didn't work. I thought it was only about the order of operations (PHY calibration before deasserting
> the reset), but it seems like there's more to it.
>
> Now phy poweron succeeds again, but it still isn't able to recover from
> UFSHCD_UIC_DL_TCx_REPLAY_ERROR when it happens.
>
> I also found some differences in the PHY calibration tables in the downstream kernel, so I changed
> them here:
>
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
> @@ -461,22 +461,22 @@ static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
> static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
> QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
> QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
>
> - QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
>
>
>
> - QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
> QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
>
>
>
> - QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
>
>
>
> - QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
> QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
>
>
>
> - QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
>
>
>
> - QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
> QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
> QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
>
>
>
> - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
>
>
>
> - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
> QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
> QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
> QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
>
>
>
> - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
>
>
>
> - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
> QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
> QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
>
>
>
> @@ -510,21 +510,40 @@ static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
>
> static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
> QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
>
> - QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
>
>
>
> - QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
>
>
>
> };
>
> static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
> QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
>
> - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
>
>
> - QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
>
>
> - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
>
>
> - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
>
>
>
> - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0f),
>
>
> - QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
>
>
> - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
>
>
> - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
> QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
> QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
> QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
>
>
>
> - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
>
>
> - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
>
>
>
> - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3f),
>
>
> - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0d),
>
>
>
> };
>
> That didn't change anything either.
>
> I noticed that in downstream there are 3 slightly different calibration tables for host versions
> 2.0.0, 2.1.0, and 2.2.0 which this device has.
> Also, I noticed that QSERDES_COM_VCO_TUNE_MAP differs between rate A and B, where it's set to 0x14
> for rate A, and to 0x54 for rate B. This was done on mainline too until the 14nm-specific QMP PHY
> driver and others were combined into one driver (phy-qcom-qmp.c), and after then only the rate B
> value 0x54 is used always.
> Those aren't necessarily related to this issue, but I thought I'd mention them since I noticed them
> on my way.
>
> What else could be causing this?
>
> Using the mainline tree at 4525c8781ec0701ce824e8bd379ae1b129e26568
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1100,6 +1100,8 @@ ufshc: ufshc@624000 { lanes-per-direction = <1>; #reset-cells = <1>; + resets = <&gcc GCC_UFS_BCR>; + reset-names = "rst"; status = "disabled"; ufs_variant { When I did that, PHY poweron started to fail (qcom_qmp_phy_power_on in the PHY driver was timing out). I looked into the downstream kernel for this device, and found out that it calibrates the PHY while the reset is asserted. So I did this and was able to "fix"(?) it: --- a/drivers/scsi/ufs/ufs-qcom.c +++ b/drivers/scsi/ufs/ufs-qcom.c @@ -292,11 +294,9 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) bool is_rate_B = (UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B) ? true : false; - /* Reset UFS Host Controller and PHY */ - ret = ufs_qcom_host_reset(hba); - if (ret) - dev_warn(hba->dev, "%s: host reset returned %d\n", - __func__, ret); + ufs_qcom_assert_reset(hba); + /* provide 1ms delay to let the reset pulse propagate. */ + usleep_range(1000, 1100); if (is_rate_B) phy_set_mode(phy, PHY_MODE_UFS_HS_B); @@ -309,11 +309,19 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) goto out; } + ufs_qcom_deassert_reset(hba); + /* + * after reset deassertion, phy will need all ref clocks, + * voltage, current to settle down before starting serdes. + */ + usleep_range(1000, 1100); + /* power on phy - start serdes and phy's power and clocks */ ret = phy_power_on(phy); Note that using reset_control_de/assert(host->core_reset) instead of ufs_qcom_de/assert_reset(hba) didn't work. I thought it was only about the order of operations (PHY calibration before deasserting the reset), but it seems like there's more to it. Now phy poweron succeeds again, but it still isn't able to recover from UFSHCD_UIC_DL_TCx_REPLAY_ERROR when it happens. I also found some differences in the PHY calibration tables in the downstream kernel, so I changed them here: --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -461,22 +461,22 @@ static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = { QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01), QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), - QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), - QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02), QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05), + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44), QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), @@ -510,21 +510,40 @@ static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = { static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), - QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02), + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), }; static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00), - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18), - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40), + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b), QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff), QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f), QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0d), }; That didn't change anything either. I noticed that in downstream there are 3 slightly different calibration tables for host versions 2.0.0, 2.1.0, and 2.2.0 which this device has. Also, I noticed that QSERDES_COM_VCO_TUNE_MAP differs between rate A and B, where it's set to 0x14 for rate A, and to 0x54 for rate B. This was done on mainline too until the 14nm-specific QMP PHY driver and others were combined into one driver (phy-qcom-qmp.c), and after then only the rate B value 0x54 is used always. Those aren't necessarily related to this issue, but I thought I'd mention them since I noticed them on my way. What else could be causing this? Using the mainline tree at 4525c8781ec0701ce824e8bd379ae1b129e26568