[01/11] target/arm: Enforce word alignment for LDRD/STRD

Message ID	20201125040642.2339476-2-richard.henderson@linaro.org
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Series	target/arm: enforce alignment \| expand [for-6.0,00/11] target/arm: enforce alignment [01/11] target/arm: Enforce word alignment for LDRD/STRD [02/11] target/arm: Enforce alignment for LDA/LDAH/STL/STLH [03/11] target/arm: Enforce alignment for LDM/STM [04/11] target/arm: Enforce alignment for RFE [05/11] target/arm: Enforce alignment for SRS [06/11] target/arm: Enforce alignment for VLDM/VSTM [07/11] target/arm: Enforce alignment for VLDR/VSTR [08/11] target/arm: Enforce alignment for VLD1 (all lanes) [09/11] target/arm: Enforce alignment for VLDn/VSTn (multiple) [10/11] target/arm: Fix decode of align in VLDST_single [11/11] target/arm: Enforce alignment for VLDn/VSTn (single)

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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH 01/11] target/arm: Enforce word alignment for LDRD/STRD
Date: Tue, 24 Nov 2020 20:06:32 -0800
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Series

target/arm: enforce alignment | expand

Comments

Philippe Mathieu-Daudé Nov. 25, 2020, 8:11 a.m. UTC | #1

On 11/25/20 5:06 AM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>  target/arm/translate.c | 8 ++++----

>  1 file changed, 4 insertions(+), 4 deletions(-)


Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

diff --git a/target/arm/translate.c b/target/arm/translate.c
index 6d04ca3a8a..17883d00f4 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -6458,7 +6458,7 @@  static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a)
     addr = op_addr_rr_pre(s, a);
 
     tmp = tcg_temp_new_i32();
-    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data);
+    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN_4 | s->be_data);
     store_reg(s, a->rt, tmp);
 
     tcg_gen_addi_i32(addr, addr, 4);
@@ -6487,7 +6487,7 @@  static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a)
     addr = op_addr_rr_pre(s, a);
 
     tmp = load_reg(s, a->rt);
-    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data);
+    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN_4 | s->be_data);
     tcg_temp_free_i32(tmp);
 
     tcg_gen_addi_i32(addr, addr, 4);
@@ -6595,7 +6595,7 @@  static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a, int rt2)
     addr = op_addr_ri_pre(s, a);
 
     tmp = tcg_temp_new_i32();
-    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data);
+    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN_4 | s->be_data);
     store_reg(s, a->rt, tmp);
 
     tcg_gen_addi_i32(addr, addr, 4);
@@ -6634,7 +6634,7 @@  static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a, int rt2)
     addr = op_addr_ri_pre(s, a);
 
     tmp = load_reg(s, a->rt);
-    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data);
+    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN_4 | s->be_data);
     tcg_temp_free_i32(tmp);
 
     tcg_gen_addi_i32(addr, addr, 4);

[01/11] target/arm: Enforce word alignment for LDRD/STRD

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