| Message ID | 20201030102636.16476-1-matthias.schiffer@ew.tq-group.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2,1/2] ARM: dts: imx7-tqma7: add SPI-NOR flash | expand |
Hi Matthias, On 20-10-30 11:26, Matthias Schiffer wrote: > The SPI-NOR flash on the SoM was missing from the device tree. > > Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> > --- > arch/arm/boot/dts/imx7-tqma7.dtsi | 30 ++++++++++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > > v2: change node name to flash@0 > > > diff --git a/arch/arm/boot/dts/imx7-tqma7.dtsi b/arch/arm/boot/dts/imx7-tqma7.dtsi > index 8773344b54aa..22f4194322ed 100644 > --- a/arch/arm/boot/dts/imx7-tqma7.dtsi > +++ b/arch/arm/boot/dts/imx7-tqma7.dtsi > @@ -160,6 +160,20 @@ > >; > }; > > + pinctrl_qspi: qspigrp { > + fsl,pins = < > + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x5A > + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x5A > + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x5A > + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x5A > + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x11 > + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x54 > + MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x54 As far as I know we are using GPIO based chip selects and not the one from the controller-IP or is this different for qspi? > + /* #QSPI_RESET */ > + MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x40000052 Do you really need to mux the reset-gpio? > + >; > + }; > + > pinctrl_usdhc3: usdhc3grp { > fsl,pins = < > MX7D_PAD_SD3_CMD__SD3_CMD 0x59 > @@ -217,6 +231,22 @@ > }; > }; > > +&qspi { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_qspi>; > + status = "okay"; > + > + flash0: flash@0 { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "jedec,spi-nor"; > + spi-max-frequency = <29000000>; > + spi-rx-bus-width = <4>; > + spi-tx-bus-width = <4>; > + reg = <0>; Please check Documentation/devicetree/bindings/mtd/partition.txt to see how partitions are added nowadays. With this in mind you should reorder the node to: compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <29000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; Regards, Marco > + }; > +}; > + > &sdma { > status = "okay"; > }; > -- > 2.17.1 > > >
Hi Matthias, On 20-10-30 11:26, Matthias Schiffer wrote: > Add the partition layout also used by the bootloader. > > Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> > --- > arch/arm/boot/dts/imx7-mba7.dtsi | 32 ++++++++++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > > v2: no changes > > > diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi > index c6d1c63f7905..3683f97f946f 100644 > --- a/arch/arm/boot/dts/imx7-mba7.dtsi > +++ b/arch/arm/boot/dts/imx7-mba7.dtsi > @@ -237,6 +237,38 @@ > }; > }; > > +&flash0 { Please see my other email about how to add paritions nowadays. Regards, Marco > + uboot@0 { > + label = "U-Boot"; > + reg = <0x0 0xd0000>; > + }; > + > + env1@d0000 { > + label = "ENV1"; > + reg = <0xd0000 0x10000>; > + }; > + > + env2@e0000 { > + label = "ENV2"; > + reg = <0xe0000 0x10000>; > + }; > + > + dtb@f0000 { > + label = "DTB"; > + reg = <0xf0000 0x10000>; > + }; > + > + linux@100000 { > + label = "Linux"; > + reg = <0x100000 0x700000>; > + }; > + > + rootfs@800000 { > + label = "RootFS"; > + reg = <0x800000 0x3800000>; > + }; > +}; > + > &flexcan1 { > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_flexcan1>; > -- > 2.17.1 > > > -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
On Mon, 2020-11-02 at 09:24 +0100, Marco Felsch wrote: > Hi Matthias, > > On 20-10-30 11:26, Matthias Schiffer wrote: > > The SPI-NOR flash on the SoM was missing from the device tree. > > > > Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> > > --- > > arch/arm/boot/dts/imx7-tqma7.dtsi | 30 ++++++++++++++++++++++++++++++ > > 1 file changed, 30 insertions(+) > > > > v2: change node name to flash@0 Sorry for the very late reply, I intend to address the review comments soon. > > > > > > diff --git a/arch/arm/boot/dts/imx7-tqma7.dtsi b/arch/arm/boot/dts/imx7-tqma7.dtsi > > index 8773344b54aa..22f4194322ed 100644 > > --- a/arch/arm/boot/dts/imx7-tqma7.dtsi > > +++ b/arch/arm/boot/dts/imx7-tqma7.dtsi > > @@ -160,6 +160,20 @@ > > >; > > }; > > > > + pinctrl_qspi: qspigrp { > > + fsl,pins = < > > + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x5A > > + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x5A > > + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x5A > > + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x5A > > + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x11 > > + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x54 > > + MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x54 > > As far as I know we are using GPIO based chip selects and not the one > from the controller-IP or is this different for qspi? Native chip selects are used for QSPI. I don't think GPIO CS make sense for this kind of QSPI controller that provides memory-mapped access to SPI flash. > > > + /* #QSPI_RESET */ > > + MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x40000052 > > Do you really need to mux the reset-gpio? The muxing configures a pullup on the reset pin to ensure that a connected flash chip is not held in reset. However, the signal is marked as optional in the schematics, and on all SoMs I have here the flash reset is wired to the board reset instead of this SoC GPIO. Still, configuring the pullup seems like a good idea to me, in case hardware variants with the optional signal actually exist - there shouldn't be any downsides, as the pin is either unconnected or wired to the flash reset. I guess I could additionally add an input hog to ensure that the pin cannot be changed? The SION bit in the pad configuration seems to be a mistake, I'll remove it. > > > + >; > > + }; > > + > > pinctrl_usdhc3: usdhc3grp { > > fsl,pins = < > > MX7D_PAD_SD3_CMD__SD3_CMD 0x59 > > @@ -217,6 +231,22 @@ > > }; > > }; > > > > +&qspi { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_qspi>; > > + status = "okay"; > > + > > + flash0: flash@0 { > > + #address-cells = <1>; > > + #size-cells = <1>; > > + compatible = "jedec,spi-nor"; > > + spi-max-frequency = <29000000>; > > + spi-rx-bus-width = <4>; > > + spi-tx-bus-width = <4>; > > + reg = <0>; > > Please check Documentation/devicetree/bindings/mtd/partition.txt to see > how partitions are added nowadays. With this in mind you should reorder > the node to: > > compatible = "jedec,spi-nor"; > reg = <0>; > spi-max-frequency = <29000000>; > spi-rx-bus-width = <4>; > spi-tx-bus-width = <4>; > > > Regards, > Marco > > > + }; > > +}; > > + > > &sdma { > > status = "okay"; > > }; > > -- > > 2.17.1 > > > > > >
diff --git a/arch/arm/boot/dts/imx7-tqma7.dtsi b/arch/arm/boot/dts/imx7-tqma7.dtsi index 8773344b54aa..22f4194322ed 100644 --- a/arch/arm/boot/dts/imx7-tqma7.dtsi +++ b/arch/arm/boot/dts/imx7-tqma7.dtsi @@ -160,6 +160,20 @@ >; }; + pinctrl_qspi: qspigrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x5A + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x5A + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x5A + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x5A + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x11 + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x54 + MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x54 + /* #QSPI_RESET */ + MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x40000052 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX7D_PAD_SD3_CMD__SD3_CMD 0x59 @@ -217,6 +231,22 @@ }; }; +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + flash0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + reg = <0>; + }; +}; + &sdma { status = "okay"; };
The SPI-NOR flash on the SoM was missing from the device tree. Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> --- arch/arm/boot/dts/imx7-tqma7.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) v2: change node name to flash@0