| Message ID | 20201029141358.3102636-1-alistair.francis@wdc.com |
|---|---|
| Headers | show |
| Series | riscv-to-apply queue | expand |
On Thu, 29 Oct 2020 at 14:25, Alistair Francis <alistair.francis@wdc.com> wrote: > > The following changes since commit c0444009147aa935d52d5acfc6b70094bb42b0dd: > > Merge remote-tracking branch 'remotes/armbru/tags/pull-qmp-2020-10-27' into staging (2020-10-29 10:03:32 +0000) > > are available in the Git repository at: > > git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20201029 > > for you to fetch changes up to e041badcd4ac644a67f02f8765095a5ff7a24d47: > > hw/riscv: microchip_pfsoc: Hook the I2C1 controller (2020-10-29 07:11:14 -0700) > > ---------------------------------------------------------------- > This series adds support for migration to RISC-V QEMU and expands the > Microchip PFSoC to allow unmodified HSS and Linux boots. > > ---------------------------------------------------------------- Hi; this fails 'make check' on 32-bit hosts: qemu-system-riscv64: at most 2047 MB RAM can be simulated Broken pipe ../../tests/qtest/libqtest.c:167: kill_qemu() tried to terminate QEMU process but encountered exit status 1 (expected 0) ERROR qtest-riscv64/qom-test - too few tests run (expected 6, got 3) and qemu-system-riscv64: at most 2047 MB RAM can be simulated Broken pipe ../../tests/qtest/libqtest.c:167: kill_qemu() tried to terminate QEMU process but encountered exit status 1 (expected 0) ERROR qtest-riscv64/test-hmp - too few tests run (expected 7, got 3) thanks -- PMM
On Sun, Nov 1, 2020 at 10:02 PM Peter Maydell <peter.maydell@linaro.org> wrote: > > On Thu, 29 Oct 2020 at 14:25, Alistair Francis <alistair.francis@wdc.com> wrote: > > > > The following changes since commit c0444009147aa935d52d5acfc6b70094bb42b0dd: > > > > Merge remote-tracking branch 'remotes/armbru/tags/pull-qmp-2020-10-27' into staging (2020-10-29 10:03:32 +0000) > > > > are available in the Git repository at: > > > > git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20201029 > > > > for you to fetch changes up to e041badcd4ac644a67f02f8765095a5ff7a24d47: > > > > hw/riscv: microchip_pfsoc: Hook the I2C1 controller (2020-10-29 07:11:14 -0700) > > > > ---------------------------------------------------------------- > > This series adds support for migration to RISC-V QEMU and expands the > > Microchip PFSoC to allow unmodified HSS and Linux boots. > > > > ---------------------------------------------------------------- > > Hi; this fails 'make check' on 32-bit hosts: Oops, I don't have 32-bit hosts to test :( > > qemu-system-riscv64: at most 2047 MB RAM can be simulated > Broken pipe > ../../tests/qtest/libqtest.c:167: kill_qemu() tried to terminate QEMU > process but encountered exit status 1 (expected 0) > ERROR qtest-riscv64/qom-test - too few tests run (expected 6, got 3) > > and > > qemu-system-riscv64: at most 2047 MB RAM can be simulated > Broken pipe > ../../tests/qtest/libqtest.c:167: kill_qemu() tried to terminate QEMU > process but encountered exit status 1 (expected 0) > ERROR qtest-riscv64/test-hmp - too few tests run (expected 7, got 3) > But I think this is caused by the following commit: https://github.com/alistair23/qemu/commit/8c47c1e9df850a928b4b230240a950feabe6152f I will send a new version of this patch soon. Regards, Bin
The following changes since commit c0444009147aa935d52d5acfc6b70094bb42b0dd: Merge remote-tracking branch 'remotes/armbru/tags/pull-qmp-2020-10-27' into staging (2020-10-29 10:03:32 +0000) are available in the Git repository at: git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20201029 for you to fetch changes up to e041badcd4ac644a67f02f8765095a5ff7a24d47: hw/riscv: microchip_pfsoc: Hook the I2C1 controller (2020-10-29 07:11:14 -0700) ---------------------------------------------------------------- This series adds support for migration to RISC-V QEMU and expands the Microchip PFSoC to allow unmodified HSS and Linux boots. ---------------------------------------------------------------- Anup Patel (2): hw/riscv: sifive_u: Allow passing custom DTB hw/riscv: virt: Allow passing custom DTB Bin Meng (10): hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support hw/riscv: microchip_pfsoc: Connect DDR memory controller modules hw/misc: Add Microchip PolarFire SoC IOSCB module support hw/riscv: microchip_pfsoc: Connect the IOSCB module hw/misc: Add Microchip PolarFire SoC SYSREG module support hw/riscv: microchip_pfsoc: Connect the SYSREG module hw/riscv: microchip_pfsoc: Map the reserved memory at address 0 hw/riscv: microchip_pfsoc: Correct DDR memory map hw/riscv: microchip_pfsoc: Hook the I2C1 controller Yifei Jiang (6): target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit target/riscv: Add basic vmstate description of CPU target/riscv: Add PMP state description target/riscv: Add H extension state description target/riscv: Add V extension state description target/riscv: Add sifive_plic vmstate include/hw/intc/sifive_plic.h | 1 + include/hw/misc/mchp_pfsoc_dmc.h | 56 +++++++++ include/hw/misc/mchp_pfsoc_ioscb.h | 50 ++++++++ include/hw/misc/mchp_pfsoc_sysreg.h | 39 ++++++ include/hw/riscv/microchip_pfsoc.h | 18 ++- target/riscv/cpu.h | 24 ++-- target/riscv/cpu_bits.h | 19 +-- target/riscv/internals.h | 4 + target/riscv/pmp.h | 2 + hw/intc/sifive_plic.c | 26 +++- hw/misc/mchp_pfsoc_dmc.c | 216 ++++++++++++++++++++++++++++++++ hw/misc/mchp_pfsoc_ioscb.c | 242 ++++++++++++++++++++++++++++++++++++ hw/misc/mchp_pfsoc_sysreg.c | 99 +++++++++++++++ hw/riscv/microchip_pfsoc.c | 123 +++++++++++++++--- hw/riscv/sifive_u.c | 28 +++-- hw/riscv/virt.c | 27 ++-- target/riscv/cpu.c | 16 +-- target/riscv/cpu_helper.c | 35 ++---- target/riscv/csr.c | 18 +-- target/riscv/machine.c | 196 +++++++++++++++++++++++++++++ target/riscv/op_helper.c | 11 +- target/riscv/pmp.c | 29 +++-- MAINTAINERS | 6 + hw/misc/Kconfig | 9 ++ hw/misc/meson.build | 3 + hw/riscv/Kconfig | 3 + target/riscv/meson.build | 3 +- 27 files changed, 1177 insertions(+), 126 deletions(-) create mode 100644 include/hw/misc/mchp_pfsoc_dmc.h create mode 100644 include/hw/misc/mchp_pfsoc_ioscb.h create mode 100644 include/hw/misc/mchp_pfsoc_sysreg.h create mode 100644 hw/misc/mchp_pfsoc_dmc.c create mode 100644 hw/misc/mchp_pfsoc_ioscb.c create mode 100644 hw/misc/mchp_pfsoc_sysreg.c create mode 100644 target/riscv/machine.c