| Message ID | 20201016171000.21240-1-ivan.griffin@emdalo.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry | expand |
On Fri, Oct 16, 2020 at 10:10 AM Ivan Griffin <ivan.griffin@emdalo.com> wrote: > > Adding the PolarFire SoC IOSCBCTRL memory region to prevent QEMU > reporting a STORE/AMO Access Fault. > > This region is used by the PolarFire SoC port of U-Boot to > interact with the FPGA system controller. > > Signed-off-by: Ivan Griffin <ivan.griffin@emdalo.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > hw/riscv/microchip_pfsoc.c | 10 ++++++++++ > include/hw/riscv/microchip_pfsoc.h | 1 + > 2 files changed, 11 insertions(+) > > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c > index 4627179cd3..9aaa276ee2 100644 > --- a/hw/riscv/microchip_pfsoc.c > +++ b/hw/riscv/microchip_pfsoc.c > @@ -97,6 +97,7 @@ static const struct MemmapEntry { > [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 }, > [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 }, > [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, > + [MICROCHIP_PFSOC_IOSCB_CTRL] = { 0x37020000, 0x1000 }, > [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 }, > [MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 }, > }; > @@ -341,6 +342,15 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) > create_unimplemented_device("microchip.pfsoc.ioscb.cfg", > memmap[MICROCHIP_PFSOC_IOSCB_CFG].base, > memmap[MICROCHIP_PFSOC_IOSCB_CFG].size); > + > + /* IOSCBCTRL > + * > + * These registers are not documented in the official documentation > + * but used by the polarfire-soc-bare-meta-library code > + */ > + create_unimplemented_device("microchip.pfsoc.ioscb.ctrl", > + memmap[MICROCHIP_PFSOC_IOSCB_CTRL].base, > + memmap[MICROCHIP_PFSOC_IOSCB_CTRL].size); > } > > static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data) > diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h > index 8bfc7e1a85..3f1874b162 100644 > --- a/include/hw/riscv/microchip_pfsoc.h > +++ b/include/hw/riscv/microchip_pfsoc.h > @@ -95,6 +95,7 @@ enum { > MICROCHIP_PFSOC_ENVM_CFG, > MICROCHIP_PFSOC_ENVM_DATA, > MICROCHIP_PFSOC_IOSCB_CFG, > + MICROCHIP_PFSOC_IOSCB_CTRL, > MICROCHIP_PFSOC_DRAM, > }; > > -- > 2.17.1 >
Hi Ivan, On Sat, Oct 17, 2020 at 1:10 AM Ivan Griffin <ivan.griffin@emdalo.com> wrote: > > Adding the PolarFire SoC IOSCBCTRL memory region to prevent QEMU > reporting a STORE/AMO Access Fault. > > This region is used by the PolarFire SoC port of U-Boot to > interact with the FPGA system controller. > > Signed-off-by: Ivan Griffin <ivan.griffin@emdalo.com> > --- > hw/riscv/microchip_pfsoc.c | 10 ++++++++++ > include/hw/riscv/microchip_pfsoc.h | 1 + > 2 files changed, 11 insertions(+) > > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c > index 4627179cd3..9aaa276ee2 100644 > --- a/hw/riscv/microchip_pfsoc.c > +++ b/hw/riscv/microchip_pfsoc.c > @@ -97,6 +97,7 @@ static const struct MemmapEntry { > [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 }, > [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 }, > [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, > + [MICROCHIP_PFSOC_IOSCB_CTRL] = { 0x37020000, 0x1000 }, > [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 }, > [MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 }, > }; > @@ -341,6 +342,15 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) > create_unimplemented_device("microchip.pfsoc.ioscb.cfg", > memmap[MICROCHIP_PFSOC_IOSCB_CFG].base, > memmap[MICROCHIP_PFSOC_IOSCB_CFG].size); > + > + /* IOSCBCTRL > + * > + * These registers are not documented in the official documentation > + * but used by the polarfire-soc-bare-meta-library code > + */ > + create_unimplemented_device("microchip.pfsoc.ioscb.ctrl", > + memmap[MICROCHIP_PFSOC_IOSCB_CTRL].base, > + memmap[MICROCHIP_PFSOC_IOSCB_CTRL].size); > } > > static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data) > diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h > index 8bfc7e1a85..3f1874b162 100644 > --- a/include/hw/riscv/microchip_pfsoc.h > +++ b/include/hw/riscv/microchip_pfsoc.h > @@ -95,6 +95,7 @@ enum { > MICROCHIP_PFSOC_ENVM_CFG, > MICROCHIP_PFSOC_ENVM_DATA, > MICROCHIP_PFSOC_IOSCB_CFG, > + MICROCHIP_PFSOC_IOSCB_CTRL, > MICROCHIP_PFSOC_DRAM, > }; Thank you for the patch! I am currently adding the DDR controller modeling support to PolarFire SoC which will cover this memory map. With my patch series, your patch is no longer needed. Regards, Bin
On Sun, Oct 18, 2020 at 6:58 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > Hi Ivan, > > On Sat, Oct 17, 2020 at 1:10 AM Ivan Griffin <ivan.griffin@emdalo.com> wrote: > > > > Adding the PolarFire SoC IOSCBCTRL memory region to prevent QEMU > > reporting a STORE/AMO Access Fault. > > > > This region is used by the PolarFire SoC port of U-Boot to > > interact with the FPGA system controller. > > > > Signed-off-by: Ivan Griffin <ivan.griffin@emdalo.com> > > --- > > hw/riscv/microchip_pfsoc.c | 10 ++++++++++ > > include/hw/riscv/microchip_pfsoc.h | 1 + > > 2 files changed, 11 insertions(+) > > > > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c > > index 4627179cd3..9aaa276ee2 100644 > > --- a/hw/riscv/microchip_pfsoc.c > > +++ b/hw/riscv/microchip_pfsoc.c > > @@ -97,6 +97,7 @@ static const struct MemmapEntry { > > [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 }, > > [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 }, > > [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, > > + [MICROCHIP_PFSOC_IOSCB_CTRL] = { 0x37020000, 0x1000 }, > > [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 }, > > [MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 }, > > }; > > @@ -341,6 +342,15 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) > > create_unimplemented_device("microchip.pfsoc.ioscb.cfg", > > memmap[MICROCHIP_PFSOC_IOSCB_CFG].base, > > memmap[MICROCHIP_PFSOC_IOSCB_CFG].size); > > + > > + /* IOSCBCTRL > > + * > > + * These registers are not documented in the official documentation > > + * but used by the polarfire-soc-bare-meta-library code > > + */ > > + create_unimplemented_device("microchip.pfsoc.ioscb.ctrl", > > + memmap[MICROCHIP_PFSOC_IOSCB_CTRL].base, > > + memmap[MICROCHIP_PFSOC_IOSCB_CTRL].size); > > } > > > > static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data) > > diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h > > index 8bfc7e1a85..3f1874b162 100644 > > --- a/include/hw/riscv/microchip_pfsoc.h > > +++ b/include/hw/riscv/microchip_pfsoc.h > > @@ -95,6 +95,7 @@ enum { > > MICROCHIP_PFSOC_ENVM_CFG, > > MICROCHIP_PFSOC_ENVM_DATA, > > MICROCHIP_PFSOC_IOSCB_CFG, > > + MICROCHIP_PFSOC_IOSCB_CTRL, > > MICROCHIP_PFSOC_DRAM, > > }; > > Thank you for the patch! > > I am currently adding the DDR controller modeling support to PolarFire > SoC which will cover this memory map. With my patch series, your patch > is no longer needed. I forgot to apply this, and Bin just sent his series. So if it's ok with you Ivan I'm just going to apply Bin's series instead. Sorry about that. Alistair > > Regards, > Bin
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 4627179cd3..9aaa276ee2 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -97,6 +97,7 @@ static const struct MemmapEntry { [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 }, [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 }, [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, + [MICROCHIP_PFSOC_IOSCB_CTRL] = { 0x37020000, 0x1000 }, [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 }, [MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 }, }; @@ -341,6 +342,15 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) create_unimplemented_device("microchip.pfsoc.ioscb.cfg", memmap[MICROCHIP_PFSOC_IOSCB_CFG].base, memmap[MICROCHIP_PFSOC_IOSCB_CFG].size); + + /* IOSCBCTRL + * + * These registers are not documented in the official documentation + * but used by the polarfire-soc-bare-meta-library code + */ + create_unimplemented_device("microchip.pfsoc.ioscb.ctrl", + memmap[MICROCHIP_PFSOC_IOSCB_CTRL].base, + memmap[MICROCHIP_PFSOC_IOSCB_CTRL].size); } static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data) diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h index 8bfc7e1a85..3f1874b162 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -95,6 +95,7 @@ enum { MICROCHIP_PFSOC_ENVM_CFG, MICROCHIP_PFSOC_ENVM_DATA, MICROCHIP_PFSOC_IOSCB_CFG, + MICROCHIP_PFSOC_IOSCB_CTRL, MICROCHIP_PFSOC_DRAM, };
Adding the PolarFire SoC IOSCBCTRL memory region to prevent QEMU reporting a STORE/AMO Access Fault. This region is used by the PolarFire SoC port of U-Boot to interact with the FPGA system controller. Signed-off-by: Ivan Griffin <ivan.griffin@emdalo.com> --- hw/riscv/microchip_pfsoc.c | 10 ++++++++++ include/hw/riscv/microchip_pfsoc.h | 1 + 2 files changed, 11 insertions(+)