mbox series

[v2,0/2] target/arm: Fix tlb flush page vs tbi

Message ID 20201016210754.818257-1-richard.henderson@linaro.org
Headers show
Series target/arm: Fix tlb flush page vs tbi | expand

Message

Richard Henderson Oct. 16, 2020, 9:07 p.m. UTC 
Since the FAR_ELx fix at 38d931687fa1, it is reported that
page granularity flushing is broken.

This makes sense, since TCG will record the entire virtual
address in its TLB, not simply the 56 significant bits.
With no other TCG support, the ARM backend should require
256 different page flushes to clear the virtual address of
any possible tag.

So I added a new tcg interface that allows passing the size
of the virtual address.  I thought a simple bit-count was a 
cleaner interface than passing in a mask, since it means that
we couldn't be passed nonsensical masks like 0xdeadbeef.  It
also makes it easy to re-direct special cases.

Changes for v2:
  * Add encode_pbm_to_runon/+decode_runon_to_pbm helpers (pmm).


r~


Richard Henderson (2):
  accel/tcg: Add tlb_flush_page_bits_by_mmuidx*
  target/arm: Use tlb_flush_page_bits_by_mmuidx*

 include/exec/exec-all.h |  36 ++++++
 accel/tcg/cputlb.c      | 275 ++++++++++++++++++++++++++++++++++++++--
 target/arm/helper.c     |  46 ++++++-
 3 files changed, 341 insertions(+), 16 deletions(-)

Comments

Philippe Mathieu-Daudé Oct. 17, 2020, 9:01 a.m. UTC | #1 
On 10/16/20 11:07 PM, Richard Henderson wrote:
> Since the FAR_ELx fix at 38d931687fa1, it is reported that

> page granularity flushing is broken.

> 

> This makes sense, since TCG will record the entire virtual

> address in its TLB, not simply the 56 significant bits.

> With no other TCG support, the ARM backend should require

> 256 different page flushes to clear the virtual address of

> any possible tag.

> 

> So I added a new tcg interface that allows passing the size

> of the virtual address.  I thought a simple bit-count was a

> cleaner interface than passing in a mask, since it means that

> we couldn't be passed nonsensical masks like 0xdeadbeef.  It

> also makes it easy to re-direct special cases.


Series:
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Peter Maydell Oct. 19, 2020, 3:47 p.m. UTC | #2 
On Fri, 16 Oct 2020 at 22:07, Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> Since the FAR_ELx fix at 38d931687fa1, it is reported that

> page granularity flushing is broken.

>

> This makes sense, since TCG will record the entire virtual

> address in its TLB, not simply the 56 significant bits.

> With no other TCG support, the ARM backend should require

> 256 different page flushes to clear the virtual address of

> any possible tag.

>

> So I added a new tcg interface that allows passing the size

> of the virtual address.  I thought a simple bit-count was a

> cleaner interface than passing in a mask, since it means that

> we couldn't be passed nonsensical masks like 0xdeadbeef.  It

> also makes it easy to re-direct special cases.

>

> Changes for v2:

>   * Add encode_pbm_to_runon/+decode_runon_to_pbm helpers (pmm).




Applied to target-arm.next, thanks.

-- PMM