| Message ID | 20201015152139.28903-4-space.monkey.delivers@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2,1/5,RISCV_PM] Add J-extension into RISC-V | expand |
On 10/15/20 8:21 AM, Alexey Baturo wrote: > Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com> > --- > target/riscv/insn_trans/trans_rva.c.inc | 3 +++ > target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ > target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ > target/riscv/insn_trans/trans_rvi.c.inc | 2 ++ > target/riscv/translate.c | 14 ++++++++++++++ > 5 files changed, 23 insertions(+) Looks ok. It does occur to me to wonder how this is intended to work with unaligned addresses, or large memory operations such as with RVV. Without changes in the generic tcg code, an unaligned memory op that crosses the mask will not wrap the second half. E.g. upmbase = 0 upmmask = 0xffff address = 0xfffe size = 8 will read [0x10005 : 0xfffe] and not [0x0005 : 0x0000] | [0xffff : 0xfffe] as a true wrapping would lead you do believe. r~
That's a great question, but unfortunately, I don't have an answer for it now. Let me ask it on J WG meeting that would happen next Monday along with extension naming and CSR numbers(hopefuly). Thanks! чт, 15 окт. 2020 г. в 20:00, Richard Henderson <richard.henderson@linaro.org >: > On 10/15/20 8:21 AM, Alexey Baturo wrote: > > Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com> > > --- > > target/riscv/insn_trans/trans_rva.c.inc | 3 +++ > > target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ > > target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ > > target/riscv/insn_trans/trans_rvi.c.inc | 2 ++ > > target/riscv/translate.c | 14 ++++++++++++++ > > 5 files changed, 23 insertions(+) > > Looks ok. > > It does occur to me to wonder how this is intended to work with unaligned > addresses, or large memory operations such as with RVV. > > Without changes in the generic tcg code, an unaligned memory op that > crosses > the mask will not wrap the second half. E.g. > > upmbase = 0 > upmmask = 0xffff > address = 0xfffe > size = 8 > > will read [0x10005 : 0xfffe] and not > [0x0005 : 0x0000] | [0xffff : 0xfffe] as a true wrapping would lead you do > believe. > > > r~ > <div dir="ltr">That's a great question, but unfortunately, I don't have an answer for it now.<div>Let me ask it on J WG meeting that would happen next Monday along with extension naming and CSR numbers(hopefuly).</div><div><br></div><div>Thanks!</div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">чт, 15 окт. 2020 г. в 20:00, Richard Henderson <<a href="mailto:richard.henderson@linaro.org">richard.henderson@linaro.org</a>>:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">On 10/15/20 8:21 AM, Alexey Baturo wrote:<br> > Signed-off-by: Alexey Baturo <<a href="mailto:space.monkey.delivers@gmail.com" target="_blank">space.monkey.delivers@gmail.com</a>><br> > ---<br> > target/riscv/insn_trans/trans_rva.c.inc | 3 +++<br> > target/riscv/insn_trans/trans_rvd.c.inc | 2 ++<br> > target/riscv/insn_trans/trans_rvf.c.inc | 2 ++<br> > target/riscv/insn_trans/trans_rvi.c.inc | 2 ++<br> > target/riscv/translate.c | 14 ++++++++++++++<br> > 5 files changed, 23 insertions(+)<br> <br> Looks ok.<br> <br> It does occur to me to wonder how this is intended to work with unaligned<br> addresses, or large memory operations such as with RVV.<br> <br> Without changes in the generic tcg code, an unaligned memory op that crosses<br> the mask will not wrap the second half. E.g.<br> <br> upmbase = 0<br> upmmask = 0xffff<br> address = 0xfffe<br> size = 8<br> <br> will read [0x10005 : 0xfffe] and not<br> [0x0005 : 0x0000] | [0xffff : 0xfffe] as a true wrapping would lead you do believe.<br> <br> <br> r~<br> </blockquote></div>
diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc index be8a9f06dd..5559e347ba 100644 --- a/target/riscv/insn_trans/trans_rva.c.inc +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -26,6 +26,7 @@ static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop) if (a->rl) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } + gen_pm_adjust_address(ctx, src1, src1); tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop); if (a->aq) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); @@ -46,6 +47,7 @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop) TCGLabel *l2 = gen_new_label(); gen_get_gpr(src1, a->rs1); + gen_pm_adjust_address(ctx, src1, src1); tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1); gen_get_gpr(src2, a->rs2); @@ -91,6 +93,7 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a, gen_get_gpr(src1, a->rs1); gen_get_gpr(src2, a->rs2); + gen_pm_adjust_address(ctx, src1, src1); (*func)(src2, src1, src2, ctx->mem_idx, mop); gen_set_gpr(a->rd, src2); diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc index 4f832637fa..935342f66d 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -25,6 +25,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) TCGv t0 = tcg_temp_new(); gen_get_gpr(t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); + gen_pm_adjust_address(ctx, t0, t0); tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ); @@ -40,6 +41,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) TCGv t0 = tcg_temp_new(); gen_get_gpr(t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); + gen_pm_adjust_address(ctx, t0, t0); tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ); diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc index 3dfec8211d..04b3c3eb3d 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -30,6 +30,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) TCGv t0 = tcg_temp_new(); gen_get_gpr(t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); + gen_pm_adjust_address(ctx, t0, t0); tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL); gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); @@ -47,6 +48,7 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a) gen_get_gpr(t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); + gen_pm_adjust_address(ctx, t0, t0); tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL); diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index d04ca0394c..bee7f6be46 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -141,6 +141,7 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop) TCGv t1 = tcg_temp_new(); gen_get_gpr(t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); + gen_pm_adjust_address(ctx, t0, t0); tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop); gen_set_gpr(a->rd, t1); @@ -180,6 +181,7 @@ static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop) TCGv dat = tcg_temp_new(); gen_get_gpr(t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); + gen_pm_adjust_address(ctx, t0, t0); gen_get_gpr(dat, a->rs2); tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 79dca2291b..a7cbf909f3 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -101,6 +101,16 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); } +/* + * Temp stub: generates address adjustment for PointerMasking + */ +static void gen_pm_adjust_address(DisasContext *s, + TCGv_i64 dst, + TCGv_i64 src) +{ + tcg_gen_mov_i64(dst, src); +} + /* * A narrow n-bit operation, where n < FLEN, checks that input operands * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. @@ -380,6 +390,7 @@ static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1, TCGv t1 = tcg_temp_new(); gen_get_gpr(t0, rs1); tcg_gen_addi_tl(t0, t0, imm); + gen_pm_adjust_address(ctx, t0, t0); int memop = tcg_memop_lookup[(opc >> 12) & 0x7]; if (memop < 0) { @@ -400,6 +411,7 @@ static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2, TCGv dat = tcg_temp_new(); gen_get_gpr(t0, rs1); tcg_gen_addi_tl(t0, t0, imm); + gen_pm_adjust_address(ctx, t0, t0); gen_get_gpr(dat, rs2); int memop = tcg_memop_lookup[(opc >> 12) & 0x7]; @@ -459,6 +471,7 @@ static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, t0 = tcg_temp_new(); gen_get_gpr(t0, rs1); tcg_gen_addi_tl(t0, t0, imm); + gen_pm_adjust_address(ctx, t0, t0); switch (opc) { case OPC_RISC_FLW: @@ -498,6 +511,7 @@ static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1, t0 = tcg_temp_new(); gen_get_gpr(t0, rs1); tcg_gen_addi_tl(t0, t0, imm); + gen_pm_adjust_address(ctx, t0, t0); switch (opc) { case OPC_RISC_FSW:
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com> --- target/riscv/insn_trans/trans_rva.c.inc | 3 +++ target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ target/riscv/insn_trans/trans_rvi.c.inc | 2 ++ target/riscv/translate.c | 14 ++++++++++++++ 5 files changed, 23 insertions(+)