| Message ID | 20200930095321.2006-15-zhaolichang@huawei.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | fix some comment spelling errors | expand |
On 9/30/20 11:53 AM, zhaolichang wrote: > I found that there are many spelling errors in the comments of qemu/target. > I used spellcheck to check the spelling errors and found some errors in the folder. > > Signed-off-by: zhaolichang <zhaolichang@huawei.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > --- > target/openrisc/cpu.h | 2 +- > target/sparc/asi.h | 2 +- > target/unicore32/translate.c | 2 +- > 3 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h > index bd42faf..8ca8605 100644 > --- a/target/openrisc/cpu.h > +++ b/target/openrisc/cpu.h > @@ -291,7 +291,7 @@ typedef struct CPUOpenRISCState { > int is_counting; > > uint32_t picmr; /* Interrupt mask register */ > - uint32_t picsr; /* Interrupt contrl register*/ > + uint32_t picsr; /* Interrupt control register*/ > #endif > void *irq[32]; /* Interrupt irq input */ > } CPUOpenRISCState; > diff --git a/target/sparc/asi.h b/target/sparc/asi.h > index bb58735..4e9f1d5 100644 > --- a/target/sparc/asi.h > +++ b/target/sparc/asi.h > @@ -231,7 +231,7 @@ > #define ASI_INTR_ID 0x63 /* (CMT) Interrupt ID register */ > #define ASI_CORE_ID 0x63 /* (CMT) LP ID register */ > #define ASI_CESR_ID 0x63 /* (CMT) CESR ID register */ > -#define ASI_IC_INSTR 0x66 /* Insn cache instrucion ram diag */ > +#define ASI_IC_INSTR 0x66 /* Insn cache instruction ram diag */ > #define ASI_IC_TAG 0x67 /* Insn cache tag/valid ram diag */ > #define ASI_IC_STAG 0x68 /* (III) Insn cache snoop tag ram */ > #define ASI_IC_PRE_DECODE 0x6e /* Insn cache pre-decode ram diag */ > diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c > index d4b06df..2e91b05 100644 > --- a/target/unicore32/translate.c > +++ b/target/unicore32/translate.c > @@ -119,7 +119,7 @@ static void load_reg_var(DisasContext *s, TCGv var, int reg) > { > if (reg == 31) { > uint32_t addr; > - /* normaly, since we updated PC */ > + /* normally, since we updated PC */ > addr = (long)s->pc; > tcg_gen_movi_i32(var, addr); > } else { >
On Wednesday, 2020-09-30 at 17:53:21 +08, zhaolichang wrote: > I found that there are many spelling errors in the comments of qemu/target. > I used spellcheck to check the spelling errors and found some errors in the folder. > > Signed-off-by: zhaolichang <zhaolichang@huawei.com> Reviewed-by: David Edmondson <david.edmondson@oracle.com> > --- > target/openrisc/cpu.h | 2 +- > target/sparc/asi.h | 2 +- > target/unicore32/translate.c | 2 +- > 3 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h > index bd42faf..8ca8605 100644 > --- a/target/openrisc/cpu.h > +++ b/target/openrisc/cpu.h > @@ -291,7 +291,7 @@ typedef struct CPUOpenRISCState { > int is_counting; > > uint32_t picmr; /* Interrupt mask register */ > - uint32_t picsr; /* Interrupt contrl register*/ > + uint32_t picsr; /* Interrupt control register*/ > #endif > void *irq[32]; /* Interrupt irq input */ > } CPUOpenRISCState; > diff --git a/target/sparc/asi.h b/target/sparc/asi.h > index bb58735..4e9f1d5 100644 > --- a/target/sparc/asi.h > +++ b/target/sparc/asi.h > @@ -231,7 +231,7 @@ > #define ASI_INTR_ID 0x63 /* (CMT) Interrupt ID register */ > #define ASI_CORE_ID 0x63 /* (CMT) LP ID register */ > #define ASI_CESR_ID 0x63 /* (CMT) CESR ID register */ > -#define ASI_IC_INSTR 0x66 /* Insn cache instrucion ram diag */ > +#define ASI_IC_INSTR 0x66 /* Insn cache instruction ram diag */ > #define ASI_IC_TAG 0x67 /* Insn cache tag/valid ram diag */ > #define ASI_IC_STAG 0x68 /* (III) Insn cache snoop tag ram */ > #define ASI_IC_PRE_DECODE 0x6e /* Insn cache pre-decode ram diag */ > diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c > index d4b06df..2e91b05 100644 > --- a/target/unicore32/translate.c > +++ b/target/unicore32/translate.c > @@ -119,7 +119,7 @@ static void load_reg_var(DisasContext *s, TCGv var, int reg) > { > if (reg == 31) { > uint32_t addr; > - /* normaly, since we updated PC */ > + /* normally, since we updated PC */ > addr = (long)s->pc; > tcg_gen_movi_i32(var, addr); > } else { > -- > 2.26.2.windows.1 dme. -- Tell her I'll be waiting, in the usual place.
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index bd42faf..8ca8605 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -291,7 +291,7 @@ typedef struct CPUOpenRISCState { int is_counting; uint32_t picmr; /* Interrupt mask register */ - uint32_t picsr; /* Interrupt contrl register*/ + uint32_t picsr; /* Interrupt control register*/ #endif void *irq[32]; /* Interrupt irq input */ } CPUOpenRISCState; diff --git a/target/sparc/asi.h b/target/sparc/asi.h index bb58735..4e9f1d5 100644 --- a/target/sparc/asi.h +++ b/target/sparc/asi.h @@ -231,7 +231,7 @@ #define ASI_INTR_ID 0x63 /* (CMT) Interrupt ID register */ #define ASI_CORE_ID 0x63 /* (CMT) LP ID register */ #define ASI_CESR_ID 0x63 /* (CMT) CESR ID register */ -#define ASI_IC_INSTR 0x66 /* Insn cache instrucion ram diag */ +#define ASI_IC_INSTR 0x66 /* Insn cache instruction ram diag */ #define ASI_IC_TAG 0x67 /* Insn cache tag/valid ram diag */ #define ASI_IC_STAG 0x68 /* (III) Insn cache snoop tag ram */ #define ASI_IC_PRE_DECODE 0x6e /* Insn cache pre-decode ram diag */ diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c index d4b06df..2e91b05 100644 --- a/target/unicore32/translate.c +++ b/target/unicore32/translate.c @@ -119,7 +119,7 @@ static void load_reg_var(DisasContext *s, TCGv var, int reg) { if (reg == 31) { uint32_t addr; - /* normaly, since we updated PC */ + /* normally, since we updated PC */ addr = (long)s->pc; tcg_gen_movi_i32(var, addr); } else {
I found that there are many spelling errors in the comments of qemu/target. I used spellcheck to check the spelling errors and found some errors in the folder. Signed-off-by: zhaolichang <zhaolichang@huawei.com> --- target/openrisc/cpu.h | 2 +- target/sparc/asi.h | 2 +- target/unicore32/translate.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-)