diff mbox series

[v10,7/7] Versal: Connect DWC3 controller with virt-versal

Message ID 1600957256-6494-8-git-send-email-sai.pavan.boddu@xilinx.com
State Superseded
Headers show
Series Make hcd-xhci independent of pci hooks | expand

Commit Message

Sai Pavan Boddu Sept. 24, 2020, 2:20 p.m. UTC
From: Vikram Garhwal <fnu.vikram@xilinx.com>

Connect dwc3 controller and usb2-reg module to xlnx-versal SOC, its placed
in iou of lpd domain and configure it as dual port host controller. Add the
respective guest dts nodes for "xlnx-versal-virt" machine.

Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
---
 hw/arm/xlnx-versal-virt.c    | 58 ++++++++++++++++++++++++++++++++++++++++++++
 hw/arm/xlnx-versal.c         | 34 ++++++++++++++++++++++++++
 include/hw/arm/xlnx-versal.h | 14 +++++++++++
 3 files changed, 106 insertions(+)

Comments

Edgar E. Iglesias Sept. 25, 2020, 6:39 p.m. UTC | #1
On Thu, Sep 24, 2020 at 07:50:56PM +0530, Sai Pavan Boddu wrote:
> From: Vikram Garhwal <fnu.vikram@xilinx.com>

> 

> Connect dwc3 controller and usb2-reg module to xlnx-versal SOC, its placed

> in iou of lpd domain and configure it as dual port host controller. Add the

> respective guest dts nodes for "xlnx-versal-virt" machine.


Hi Sai,

One minor comment inline.

And a question, could you please post an example command-line for this?


> 

> Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>

> Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>

> ---

>  hw/arm/xlnx-versal-virt.c    | 58 ++++++++++++++++++++++++++++++++++++++++++++

>  hw/arm/xlnx-versal.c         | 34 ++++++++++++++++++++++++++

>  include/hw/arm/xlnx-versal.h | 14 +++++++++++

>  3 files changed, 106 insertions(+)

> 

> diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c

> index 03e2320..f0ac5ba 100644

> --- a/hw/arm/xlnx-versal-virt.c

> +++ b/hw/arm/xlnx-versal-virt.c

> @@ -39,6 +39,8 @@ struct VersalVirt {

>          uint32_t ethernet_phy[2];

>          uint32_t clk_125Mhz;

>          uint32_t clk_25Mhz;

> +        uint32_t usb;

> +        uint32_t dwc;

>      } phandle;

>      struct arm_boot_info binfo;

>  

> @@ -66,6 +68,8 @@ static void fdt_create(VersalVirt *s)

>      s->phandle.clk_25Mhz = qemu_fdt_alloc_phandle(s->fdt);

>      s->phandle.clk_125Mhz = qemu_fdt_alloc_phandle(s->fdt);

>  

> +    s->phandle.usb = qemu_fdt_alloc_phandle(s->fdt);

> +    s->phandle.dwc = qemu_fdt_alloc_phandle(s->fdt);

>      /* Create /chosen node for load_dtb.  */

>      qemu_fdt_add_subnode(s->fdt, "/chosen");

>  

> @@ -148,6 +152,59 @@ static void fdt_add_timer_nodes(VersalVirt *s)

>                       compat, sizeof(compat));

>  }

>  

> +static void fdt_add_usb_xhci_nodes(VersalVirt *s)

> +{

> +    const char clocknames[] = "bus_clk\0ref_clk";

> +    char *name = g_strdup_printf("/usb@%" PRIx32, MM_USB2_CTRL_REGS);

> +    const char compat[] = "xlnx,versal-dwc3";

> +

> +    qemu_fdt_add_subnode(s->fdt, name);

> +    qemu_fdt_setprop(s->fdt, name, "compatible",

> +                         compat, sizeof(compat));

> +    qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",

> +                                 2, MM_USB2_CTRL_REGS,

> +                                 2, MM_USB2_CTRL_REGS_SIZE);

> +    qemu_fdt_setprop(s->fdt, name, "clock-names",

> +                         clocknames, sizeof(clocknames));

> +    qemu_fdt_setprop_cells(s->fdt, name, "clocks",

> +                               s->phandle.clk_25Mhz, s->phandle.clk_125Mhz);

> +    qemu_fdt_setprop(s->fdt, name, "ranges", NULL, 0);

> +    qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 2);

> +    qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 2);

> +    qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.usb);

> +    g_free(name);

> +

> +    {

> +        const char irq_name[] = "dwc_usb3";

> +        const char compat[] = "snps,dwc3";

> +

> +        name = g_strdup_printf("/usb@%" PRIx32 "/dwc3@%" PRIx32,

> +                               MM_USB2_CTRL_REGS, MM_USB_XHCI_0);

> +        qemu_fdt_add_subnode(s->fdt, name);

> +        qemu_fdt_setprop(s->fdt, name, "compatible",

> +                         compat, sizeof(compat));

> +        qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",

> +                                     2, MM_USB_XHCI_0, 2, MM_USB_XHCI_0_SIZE);

> +        qemu_fdt_setprop(s->fdt, name, "interrupt-names",

> +                         irq_name, sizeof(irq_name));

> +        qemu_fdt_setprop_cells(s->fdt, name, "interrupts",

> +                                   GIC_FDT_IRQ_TYPE_SPI, VERSAL_USB0_IRQ_0,

> +                                   GIC_FDT_IRQ_FLAGS_LEVEL_HI);

> +        qemu_fdt_setprop_cell(s->fdt, name,

> +                              "snps,quirk-frame-length-adjustment", 0x20);

> +        qemu_fdt_setprop_cells(s->fdt, name, "#stream-id-cells", 1);

> +        qemu_fdt_setprop_string(s->fdt, name, "dr_mode", "host");

> +        qemu_fdt_setprop_string(s->fdt, name, "phy-names", "usb3-phy");

> +        qemu_fdt_setprop(s->fdt, name, "snps,dis_u2_susphy_quirk", NULL, 0);

> +        qemu_fdt_setprop(s->fdt, name, "snps,dis_u3_susphy_quirk", NULL, 0);

> +        qemu_fdt_setprop(s->fdt, name, "snps,refclk_fladj", NULL, 0);

> +        qemu_fdt_setprop(s->fdt, name, "snps,mask_phy_reset", NULL, 0);

> +        qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.dwc);

> +        qemu_fdt_setprop_string(s->fdt, name, "maximum-speed", "high-speed");

> +        g_free(name);

> +    }

> +}

> +

>  static void fdt_add_uart_nodes(VersalVirt *s)

>  {

>      uint64_t addrs[] = { MM_UART1, MM_UART0 };

> @@ -515,6 +572,7 @@ static void versal_virt_init(MachineState *machine)

>      fdt_add_gic_nodes(s);

>      fdt_add_timer_nodes(s);

>      fdt_add_zdma_nodes(s);

> +    fdt_add_usb_xhci_nodes(s);

>      fdt_add_sd_nodes(s);

>      fdt_add_rtc_node(s);

>      fdt_add_cpu_nodes(s, psci_conduit);

> diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c

> index 12ba6c4..64b0d0a 100644

> --- a/hw/arm/xlnx-versal.c

> +++ b/hw/arm/xlnx-versal.c

> @@ -145,6 +145,39 @@ static void versal_create_uarts(Versal *s, qemu_irq *pic)

>      }

>  }

>  

> +static void versal_create_usbs(Versal *s, qemu_irq *pic)

> +{

> +    DeviceState *dev, *xhci_dev;

> +    MemoryRegion *mr;

> +

> +    object_initialize_child(OBJECT(s), "dwc3-0", &s->lpd.iou.usb.dwc3,

> +                            TYPE_USB_DWC3);

> +    dev = DEVICE(&s->lpd.iou.usb.dwc3);

> +    xhci_dev = DEVICE(&s->lpd.iou.usb.dwc3.sysbus_xhci);

> +

> +    object_property_set_link(OBJECT(xhci_dev), "dma", OBJECT(&s->mr_ps),

> +                             &error_abort);

> +    qdev_prop_set_uint32(xhci_dev, "intrs", 1);

> +    qdev_prop_set_uint32(xhci_dev, "slots", 2);

> +

> +    sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);

> +

> +    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);

> +    memory_region_add_subregion(&s->mr_ps, MM_USB_XHCI_0_DWC3_GLOBAL, mr);

> +    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(xhci_dev), 0);

> +    memory_region_add_subregion(&s->mr_ps, MM_USB_XHCI_0, mr);

> +

> +    sysbus_connect_irq(SYS_BUS_DEVICE(xhci_dev), 0, pic[VERSAL_USB0_IRQ_0]);

> +

> +    object_initialize_child(OBJECT(s), "usb2reg-0", &s->lpd.iou.usb.Usb2Regs,

> +                           TYPE_XILINX_VERSAL_USB2_CTRL_REGS);

> +    dev = DEVICE(&s->lpd.iou.usb.Usb2Regs);

> +    sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);

> +

> +    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);

> +    memory_region_add_subregion(&s->mr_ps, MM_USB2_CTRL_REGS, mr);

> +}

> +

>  static void versal_create_gems(Versal *s, qemu_irq *pic)

>  {

>      int i;

> @@ -333,6 +366,7 @@ static void versal_realize(DeviceState *dev, Error **errp)

>      versal_create_apu_cpus(s);

>      versal_create_apu_gic(s, pic);

>      versal_create_uarts(s, pic);

> +    versal_create_usbs(s, pic);

>      versal_create_gems(s, pic);

>      versal_create_admas(s, pic);

>      versal_create_sds(s, pic);

> diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h

> index 8ce8e63..743e4f7 100644

> --- a/include/hw/arm/xlnx-versal.h

> +++ b/include/hw/arm/xlnx-versal.h

> @@ -21,6 +21,8 @@

>  #include "hw/net/cadence_gem.h"

>  #include "hw/rtc/xlnx-zynqmp-rtc.h"

>  #include "qom/object.h"

> +#include "hw/usb/hcd-dwc3.h"

> +#include "hw/misc/xlnx-versal-usb2-ctrl-regs.h"

>  

>  #define TYPE_XLNX_VERSAL "xlnx-versal"

>  OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)

> @@ -59,6 +61,10 @@ struct Versal {

>              PL011State uart[XLNX_VERSAL_NR_UARTS];

>              CadenceGEMState gem[XLNX_VERSAL_NR_GEMS];

>              XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS];

> +            struct {

> +                USBDWC3 dwc3;

> +                VersalUsb2CtrlRegs Usb2Regs;


I'd prefer this to be any of the following:

                   VersalUsb2CtrlRegs ctrl;
                   VersalUsb2CtrlRegs regs;
                   VersalUsb2CtrlRegs ctrl_regs;
Gerd Hoffmann Sept. 28, 2020, 1:15 p.m. UTC | #2
On Fri, Sep 25, 2020 at 08:39:46PM +0200, Edgar E. Iglesias wrote:
> On Thu, Sep 24, 2020 at 07:50:56PM +0530, Sai Pavan Boddu wrote:

> > From: Vikram Garhwal <fnu.vikram@xilinx.com>

> > 

> > Connect dwc3 controller and usb2-reg module to xlnx-versal SOC, its placed

> > in iou of lpd domain and configure it as dual port host controller. Add the

> > respective guest dts nodes for "xlnx-versal-virt" machine.

> 

> Hi Sai,

> 

> One minor comment inline.


Cherry-picked patches 1-4 for the usb queue, leaving 5-7 for later (or
maybe the arm queue).

take care,
  Gerd
Sai Pavan Boddu Sept. 29, 2020, 5:42 a.m. UTC | #3
Hi Edgar,

> -----Original Message-----

> From: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

> Sent: Saturday, September 26, 2020 12:10 AM

> To: Sai Pavan Boddu <saipava@xilinx.com>

> Cc: Peter Maydell <peter.maydell@linaro.org>; Markus Armbruster

> <armbru@redhat.com>; 'Marc-André Lureau'

> <marcandre.lureau@redhat.com>; Paolo Bonzini <pbonzini@redhat.com>;

> Gerd Hoffmann <kraxel@redhat.com>; Edgar Iglesias <edgari@xilinx.com>;

> Francisco Eduardo Iglesias <figlesia@xilinx.com>; qemu-devel@nongnu.org;

> Alistair Francis <alistair.francis@wdc.com>; Eduardo Habkost

> <ehabkost@redhat.com>; Ying Fang <fangying1@huawei.com>; 'Philippe

> Mathieu-Daudé' <philmd@redhat.com>; Vikram Garhwal

> <fnuv@xilinx.com>; Paul Zimmerman <pauldzim@gmail.com>; Sai Pavan

> Boddu <saipava@xilinx.com>

> Subject: Re: [PATCH v10 7/7] Versal: Connect DWC3 controller with virt-versal

> 

> On Thu, Sep 24, 2020 at 07:50:56PM +0530, Sai Pavan Boddu wrote:

> > From: Vikram Garhwal <fnu.vikram@xilinx.com>

> >

> > Connect dwc3 controller and usb2-reg module to xlnx-versal SOC, its

> > placed in iou of lpd domain and configure it as dual port host

> > controller. Add the respective guest dts nodes for "xlnx-versal-virt"

> machine.

> 

> Hi Sai,

> 

> One minor comment inline.

> 

> And a question, could you please post an example command-line for this?

[Sai Pavan Boddu] Below is the command to plug a usb storage device on qemu command line

-device usb-storage,bus=usb-bus.0,port=1,drive=usb-stick -drive file=./usb-stick.img,id=usb-stick


> 

> 

> >

> > Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>

> > Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>

> > ---

> >  hw/arm/xlnx-versal-virt.c    | 58

> ++++++++++++++++++++++++++++++++++++++++++++

> >  hw/arm/xlnx-versal.c         | 34 ++++++++++++++++++++++++++

> >  include/hw/arm/xlnx-versal.h | 14 +++++++++++

> >  3 files changed, 106 insertions(+)

> >

> > diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c

> > index 03e2320..f0ac5ba 100644

> > --- a/hw/arm/xlnx-versal-virt.c

> > +++ b/hw/arm/xlnx-versal-virt.c

> > @@ -39,6 +39,8 @@ struct VersalVirt {

> >          uint32_t ethernet_phy[2];

> >          uint32_t clk_125Mhz;

> >          uint32_t clk_25Mhz;

> > +        uint32_t usb;

> > +        uint32_t dwc;

> >      } phandle;

> >      struct arm_boot_info binfo;

> >

> > @@ -66,6 +68,8 @@ static void fdt_create(VersalVirt *s)

> >      s->phandle.clk_25Mhz = qemu_fdt_alloc_phandle(s->fdt);

> >      s->phandle.clk_125Mhz = qemu_fdt_alloc_phandle(s->fdt);

> >

> > +    s->phandle.usb = qemu_fdt_alloc_phandle(s->fdt);

> > +    s->phandle.dwc = qemu_fdt_alloc_phandle(s->fdt);

> >      /* Create /chosen node for load_dtb.  */

> >      qemu_fdt_add_subnode(s->fdt, "/chosen");

> >

> > @@ -148,6 +152,59 @@ static void fdt_add_timer_nodes(VersalVirt *s)

> >                       compat, sizeof(compat));  }

> >

> > +static void fdt_add_usb_xhci_nodes(VersalVirt *s) {

> > +    const char clocknames[] = "bus_clk\0ref_clk";

> > +    char *name = g_strdup_printf("/usb@%" PRIx32,

> MM_USB2_CTRL_REGS);

> > +    const char compat[] = "xlnx,versal-dwc3";

> > +

> > +    qemu_fdt_add_subnode(s->fdt, name);

> > +    qemu_fdt_setprop(s->fdt, name, "compatible",

> > +                         compat, sizeof(compat));

> > +    qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",

> > +                                 2, MM_USB2_CTRL_REGS,

> > +                                 2, MM_USB2_CTRL_REGS_SIZE);

> > +    qemu_fdt_setprop(s->fdt, name, "clock-names",

> > +                         clocknames, sizeof(clocknames));

> > +    qemu_fdt_setprop_cells(s->fdt, name, "clocks",

> > +                               s->phandle.clk_25Mhz, s->phandle.clk_125Mhz);

> > +    qemu_fdt_setprop(s->fdt, name, "ranges", NULL, 0);

> > +    qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 2);

> > +    qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 2);

> > +    qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.usb);

> > +    g_free(name);

> > +

> > +    {

> > +        const char irq_name[] = "dwc_usb3";

> > +        const char compat[] = "snps,dwc3";

> > +

> > +        name = g_strdup_printf("/usb@%" PRIx32 "/dwc3@%" PRIx32,

> > +                               MM_USB2_CTRL_REGS, MM_USB_XHCI_0);

> > +        qemu_fdt_add_subnode(s->fdt, name);

> > +        qemu_fdt_setprop(s->fdt, name, "compatible",

> > +                         compat, sizeof(compat));

> > +        qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",

> > +                                     2, MM_USB_XHCI_0, 2, MM_USB_XHCI_0_SIZE);

> > +        qemu_fdt_setprop(s->fdt, name, "interrupt-names",

> > +                         irq_name, sizeof(irq_name));

> > +        qemu_fdt_setprop_cells(s->fdt, name, "interrupts",

> > +                                   GIC_FDT_IRQ_TYPE_SPI, VERSAL_USB0_IRQ_0,

> > +                                   GIC_FDT_IRQ_FLAGS_LEVEL_HI);

> > +        qemu_fdt_setprop_cell(s->fdt, name,

> > +                              "snps,quirk-frame-length-adjustment", 0x20);

> > +        qemu_fdt_setprop_cells(s->fdt, name, "#stream-id-cells", 1);

> > +        qemu_fdt_setprop_string(s->fdt, name, "dr_mode", "host");

> > +        qemu_fdt_setprop_string(s->fdt, name, "phy-names", "usb3-phy");

> > +        qemu_fdt_setprop(s->fdt, name, "snps,dis_u2_susphy_quirk", NULL,

> 0);

> > +        qemu_fdt_setprop(s->fdt, name, "snps,dis_u3_susphy_quirk", NULL,

> 0);

> > +        qemu_fdt_setprop(s->fdt, name, "snps,refclk_fladj", NULL, 0);

> > +        qemu_fdt_setprop(s->fdt, name, "snps,mask_phy_reset", NULL, 0);

> > +        qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.dwc);

> > +        qemu_fdt_setprop_string(s->fdt, name, "maximum-speed", "high-

> speed");

> > +        g_free(name);

> > +    }

> > +}

> > +

> >  static void fdt_add_uart_nodes(VersalVirt *s)  {

> >      uint64_t addrs[] = { MM_UART1, MM_UART0 }; @@ -515,6 +572,7 @@

> > static void versal_virt_init(MachineState *machine)

> >      fdt_add_gic_nodes(s);

> >      fdt_add_timer_nodes(s);

> >      fdt_add_zdma_nodes(s);

> > +    fdt_add_usb_xhci_nodes(s);

> >      fdt_add_sd_nodes(s);

> >      fdt_add_rtc_node(s);

> >      fdt_add_cpu_nodes(s, psci_conduit); diff --git

> > a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 12ba6c4..64b0d0a

> > 100644

> > --- a/hw/arm/xlnx-versal.c

> > +++ b/hw/arm/xlnx-versal.c

> > @@ -145,6 +145,39 @@ static void versal_create_uarts(Versal *s,

> qemu_irq *pic)

> >      }

> >  }

> >

> > +static void versal_create_usbs(Versal *s, qemu_irq *pic) {

> > +    DeviceState *dev, *xhci_dev;

> > +    MemoryRegion *mr;

> > +

> > +    object_initialize_child(OBJECT(s), "dwc3-0", &s->lpd.iou.usb.dwc3,

> > +                            TYPE_USB_DWC3);

> > +    dev = DEVICE(&s->lpd.iou.usb.dwc3);

> > +    xhci_dev = DEVICE(&s->lpd.iou.usb.dwc3.sysbus_xhci);

> > +

> > +    object_property_set_link(OBJECT(xhci_dev), "dma", OBJECT(&s-

> >mr_ps),

> > +                             &error_abort);

> > +    qdev_prop_set_uint32(xhci_dev, "intrs", 1);

> > +    qdev_prop_set_uint32(xhci_dev, "slots", 2);

> > +

> > +    sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);

> > +

> > +    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);

> > +    memory_region_add_subregion(&s->mr_ps,

> MM_USB_XHCI_0_DWC3_GLOBAL, mr);

> > +    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(xhci_dev), 0);

> > +    memory_region_add_subregion(&s->mr_ps, MM_USB_XHCI_0, mr);

> > +

> > +    sysbus_connect_irq(SYS_BUS_DEVICE(xhci_dev), 0,

> > + pic[VERSAL_USB0_IRQ_0]);

> > +

> > +    object_initialize_child(OBJECT(s), "usb2reg-0", &s-

> >lpd.iou.usb.Usb2Regs,

> > +                           TYPE_XILINX_VERSAL_USB2_CTRL_REGS);

> > +    dev = DEVICE(&s->lpd.iou.usb.Usb2Regs);

> > +    sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);

> > +

> > +    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);

> > +    memory_region_add_subregion(&s->mr_ps, MM_USB2_CTRL_REGS,

> mr); }

> > +

> >  static void versal_create_gems(Versal *s, qemu_irq *pic)  {

> >      int i;

> > @@ -333,6 +366,7 @@ static void versal_realize(DeviceState *dev, Error

> **errp)

> >      versal_create_apu_cpus(s);

> >      versal_create_apu_gic(s, pic);

> >      versal_create_uarts(s, pic);

> > +    versal_create_usbs(s, pic);

> >      versal_create_gems(s, pic);

> >      versal_create_admas(s, pic);

> >      versal_create_sds(s, pic);

> > diff --git a/include/hw/arm/xlnx-versal.h

> > b/include/hw/arm/xlnx-versal.h index 8ce8e63..743e4f7 100644

> > --- a/include/hw/arm/xlnx-versal.h

> > +++ b/include/hw/arm/xlnx-versal.h

> > @@ -21,6 +21,8 @@

> >  #include "hw/net/cadence_gem.h"

> >  #include "hw/rtc/xlnx-zynqmp-rtc.h"

> >  #include "qom/object.h"

> > +#include "hw/usb/hcd-dwc3.h"

> > +#include "hw/misc/xlnx-versal-usb2-ctrl-regs.h"

> >

> >  #define TYPE_XLNX_VERSAL "xlnx-versal"

> >  OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) @@ -59,6 +61,10

> @@

> > struct Versal {

> >              PL011State uart[XLNX_VERSAL_NR_UARTS];

> >              CadenceGEMState gem[XLNX_VERSAL_NR_GEMS];

> >              XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS];

> > +            struct {

> > +                USBDWC3 dwc3;

> > +                VersalUsb2CtrlRegs Usb2Regs;

> 

> I'd prefer this to be any of the following:

> 

>                    VersalUsb2CtrlRegs ctrl;	

[Sai Pavan Boddu] Thanks, I would use above.

Regards,
Sai Pavan
>                    VersalUsb2CtrlRegs regs;

>                    VersalUsb2CtrlRegs ctrl_regs;
Sai Pavan Boddu Sept. 29, 2020, 6:58 a.m. UTC | #4
Hi Gerd,

> -----Original Message-----

> From: Gerd Hoffmann <kraxel@redhat.com>

> Sent: Monday, September 28, 2020 6:45 PM

> To: Edgar Iglesias <edgari@xilinx.com>

> Cc: Sai Pavan Boddu <saipava@xilinx.com>; Peter Maydell

> <peter.maydell@linaro.org>; Markus Armbruster <armbru@redhat.com>;

> 'Marc-André Lureau' <marcandre.lureau@redhat.com>; Paolo Bonzini

> <pbonzini@redhat.com>; Edgar Iglesias <edgari@xilinx.com>; Francisco

> Eduardo Iglesias <figlesia@xilinx.com>; qemu-devel@nongnu.org; Alistair

> Francis <alistair.francis@wdc.com>; Eduardo Habkost

> <ehabkost@redhat.com>; Ying Fang <fangying1@huawei.com>; 'Philippe

> Mathieu-Daudé' <philmd@redhat.com>; Vikram Garhwal

> <fnuv@xilinx.com>; Paul Zimmerman <pauldzim@gmail.com>; Sai Pavan

> Boddu <saipava@xilinx.com>

> Subject: Re: [PATCH v10 7/7] Versal: Connect DWC3 controller with virt-versal

> 

> On Fri, Sep 25, 2020 at 08:39:46PM +0200, Edgar E. Iglesias wrote:

> > On Thu, Sep 24, 2020 at 07:50:56PM +0530, Sai Pavan Boddu wrote:

> > > From: Vikram Garhwal <fnu.vikram@xilinx.com>

> > >

> > > Connect dwc3 controller and usb2-reg module to xlnx-versal SOC, its

> > > placed in iou of lpd domain and configure it as dual port host

> > > controller. Add the respective guest dts nodes for "xlnx-versal-virt"

> machine.

> >

> > Hi Sai,

> >

> > One minor comment inline.

> 

> Cherry-picked patches 1-4 for the usb queue, leaving 5-7 for later (or maybe

> the arm queue).

[Sai Pavan Boddu] Thanks, 
I would make new patch series for pending ones.

Regards,
Sai Pavan
> 

> take care,

>   Gerd
diff mbox series

Patch

diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index 03e2320..f0ac5ba 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -39,6 +39,8 @@  struct VersalVirt {
         uint32_t ethernet_phy[2];
         uint32_t clk_125Mhz;
         uint32_t clk_25Mhz;
+        uint32_t usb;
+        uint32_t dwc;
     } phandle;
     struct arm_boot_info binfo;
 
@@ -66,6 +68,8 @@  static void fdt_create(VersalVirt *s)
     s->phandle.clk_25Mhz = qemu_fdt_alloc_phandle(s->fdt);
     s->phandle.clk_125Mhz = qemu_fdt_alloc_phandle(s->fdt);
 
+    s->phandle.usb = qemu_fdt_alloc_phandle(s->fdt);
+    s->phandle.dwc = qemu_fdt_alloc_phandle(s->fdt);
     /* Create /chosen node for load_dtb.  */
     qemu_fdt_add_subnode(s->fdt, "/chosen");
 
@@ -148,6 +152,59 @@  static void fdt_add_timer_nodes(VersalVirt *s)
                      compat, sizeof(compat));
 }
 
+static void fdt_add_usb_xhci_nodes(VersalVirt *s)
+{
+    const char clocknames[] = "bus_clk\0ref_clk";
+    char *name = g_strdup_printf("/usb@%" PRIx32, MM_USB2_CTRL_REGS);
+    const char compat[] = "xlnx,versal-dwc3";
+
+    qemu_fdt_add_subnode(s->fdt, name);
+    qemu_fdt_setprop(s->fdt, name, "compatible",
+                         compat, sizeof(compat));
+    qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
+                                 2, MM_USB2_CTRL_REGS,
+                                 2, MM_USB2_CTRL_REGS_SIZE);
+    qemu_fdt_setprop(s->fdt, name, "clock-names",
+                         clocknames, sizeof(clocknames));
+    qemu_fdt_setprop_cells(s->fdt, name, "clocks",
+                               s->phandle.clk_25Mhz, s->phandle.clk_125Mhz);
+    qemu_fdt_setprop(s->fdt, name, "ranges", NULL, 0);
+    qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 2);
+    qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 2);
+    qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.usb);
+    g_free(name);
+
+    {
+        const char irq_name[] = "dwc_usb3";
+        const char compat[] = "snps,dwc3";
+
+        name = g_strdup_printf("/usb@%" PRIx32 "/dwc3@%" PRIx32,
+                               MM_USB2_CTRL_REGS, MM_USB_XHCI_0);
+        qemu_fdt_add_subnode(s->fdt, name);
+        qemu_fdt_setprop(s->fdt, name, "compatible",
+                         compat, sizeof(compat));
+        qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
+                                     2, MM_USB_XHCI_0, 2, MM_USB_XHCI_0_SIZE);
+        qemu_fdt_setprop(s->fdt, name, "interrupt-names",
+                         irq_name, sizeof(irq_name));
+        qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
+                                   GIC_FDT_IRQ_TYPE_SPI, VERSAL_USB0_IRQ_0,
+                                   GIC_FDT_IRQ_FLAGS_LEVEL_HI);
+        qemu_fdt_setprop_cell(s->fdt, name,
+                              "snps,quirk-frame-length-adjustment", 0x20);
+        qemu_fdt_setprop_cells(s->fdt, name, "#stream-id-cells", 1);
+        qemu_fdt_setprop_string(s->fdt, name, "dr_mode", "host");
+        qemu_fdt_setprop_string(s->fdt, name, "phy-names", "usb3-phy");
+        qemu_fdt_setprop(s->fdt, name, "snps,dis_u2_susphy_quirk", NULL, 0);
+        qemu_fdt_setprop(s->fdt, name, "snps,dis_u3_susphy_quirk", NULL, 0);
+        qemu_fdt_setprop(s->fdt, name, "snps,refclk_fladj", NULL, 0);
+        qemu_fdt_setprop(s->fdt, name, "snps,mask_phy_reset", NULL, 0);
+        qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.dwc);
+        qemu_fdt_setprop_string(s->fdt, name, "maximum-speed", "high-speed");
+        g_free(name);
+    }
+}
+
 static void fdt_add_uart_nodes(VersalVirt *s)
 {
     uint64_t addrs[] = { MM_UART1, MM_UART0 };
@@ -515,6 +572,7 @@  static void versal_virt_init(MachineState *machine)
     fdt_add_gic_nodes(s);
     fdt_add_timer_nodes(s);
     fdt_add_zdma_nodes(s);
+    fdt_add_usb_xhci_nodes(s);
     fdt_add_sd_nodes(s);
     fdt_add_rtc_node(s);
     fdt_add_cpu_nodes(s, psci_conduit);
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index 12ba6c4..64b0d0a 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -145,6 +145,39 @@  static void versal_create_uarts(Versal *s, qemu_irq *pic)
     }
 }
 
+static void versal_create_usbs(Versal *s, qemu_irq *pic)
+{
+    DeviceState *dev, *xhci_dev;
+    MemoryRegion *mr;
+
+    object_initialize_child(OBJECT(s), "dwc3-0", &s->lpd.iou.usb.dwc3,
+                            TYPE_USB_DWC3);
+    dev = DEVICE(&s->lpd.iou.usb.dwc3);
+    xhci_dev = DEVICE(&s->lpd.iou.usb.dwc3.sysbus_xhci);
+
+    object_property_set_link(OBJECT(xhci_dev), "dma", OBJECT(&s->mr_ps),
+                             &error_abort);
+    qdev_prop_set_uint32(xhci_dev, "intrs", 1);
+    qdev_prop_set_uint32(xhci_dev, "slots", 2);
+
+    sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
+
+    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
+    memory_region_add_subregion(&s->mr_ps, MM_USB_XHCI_0_DWC3_GLOBAL, mr);
+    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(xhci_dev), 0);
+    memory_region_add_subregion(&s->mr_ps, MM_USB_XHCI_0, mr);
+
+    sysbus_connect_irq(SYS_BUS_DEVICE(xhci_dev), 0, pic[VERSAL_USB0_IRQ_0]);
+
+    object_initialize_child(OBJECT(s), "usb2reg-0", &s->lpd.iou.usb.Usb2Regs,
+                           TYPE_XILINX_VERSAL_USB2_CTRL_REGS);
+    dev = DEVICE(&s->lpd.iou.usb.Usb2Regs);
+    sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
+
+    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
+    memory_region_add_subregion(&s->mr_ps, MM_USB2_CTRL_REGS, mr);
+}
+
 static void versal_create_gems(Versal *s, qemu_irq *pic)
 {
     int i;
@@ -333,6 +366,7 @@  static void versal_realize(DeviceState *dev, Error **errp)
     versal_create_apu_cpus(s);
     versal_create_apu_gic(s, pic);
     versal_create_uarts(s, pic);
+    versal_create_usbs(s, pic);
     versal_create_gems(s, pic);
     versal_create_admas(s, pic);
     versal_create_sds(s, pic);
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index 8ce8e63..743e4f7 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -21,6 +21,8 @@ 
 #include "hw/net/cadence_gem.h"
 #include "hw/rtc/xlnx-zynqmp-rtc.h"
 #include "qom/object.h"
+#include "hw/usb/hcd-dwc3.h"
+#include "hw/misc/xlnx-versal-usb2-ctrl-regs.h"
 
 #define TYPE_XLNX_VERSAL "xlnx-versal"
 OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
@@ -59,6 +61,10 @@  struct Versal {
             PL011State uart[XLNX_VERSAL_NR_UARTS];
             CadenceGEMState gem[XLNX_VERSAL_NR_GEMS];
             XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS];
+            struct {
+                USBDWC3 dwc3;
+                VersalUsb2CtrlRegs Usb2Regs;
+            } usb;
         } iou;
     } lpd;
 
@@ -88,6 +94,7 @@  struct Versal {
 
 #define VERSAL_UART0_IRQ_0         18
 #define VERSAL_UART1_IRQ_0         19
+#define VERSAL_USB0_IRQ_0          22
 #define VERSAL_GEM0_IRQ_0          56
 #define VERSAL_GEM0_WAKE_IRQ_0     57
 #define VERSAL_GEM1_IRQ_0          58
@@ -125,6 +132,13 @@  struct Versal {
 #define MM_OCM                      0xfffc0000U
 #define MM_OCM_SIZE                 0x40000
 
+#define MM_USB2_CTRL_REGS           0xFF9D0000
+#define MM_USB2_CTRL_REGS_SIZE      0x10000
+
+#define MM_USB_XHCI_0               0xFE200000
+#define MM_USB_XHCI_0_SIZE          0x10000
+#define MM_USB_XHCI_0_DWC3_GLOBAL   (MM_USB_XHCI_0 + 0xC100)
+
 #define MM_TOP_DDR                  0x0
 #define MM_TOP_DDR_SIZE             0x80000000U
 #define MM_TOP_DDR_2                0x800000000ULL