| Message ID | 1598633743-1023-2-git-send-email-sagar.kadam@sifive.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [RESEND,v2,1/1] dt-bindings: riscv: sifive-l2-cache: convert bindings to json-schema | expand |
On Fri, Aug 28, 2020 at 10:25:43PM +0530, Sagar Kadam wrote: > Convert the device tree bindings for the SiFive's FU540-C000 SoC's L2 Cache > controller to YAML format. > > Signed-off-by: Sagar Kadam <sagar.kadam@sifive.com> > --- > .../devicetree/bindings/riscv/sifive-l2-cache.txt | 51 ------------ > .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 92 ++++++++++++++++++++++ > 2 files changed, 92 insertions(+), 51 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > create mode 100644 Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > > diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > deleted file mode 100644 > index 73d8f19..0000000 > --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > +++ /dev/null > @@ -1,51 +0,0 @@ > -SiFive L2 Cache Controller > --------------------------- > -The SiFive Level 2 Cache Controller is used to provide access to fast copies > -of memory for masters in a Core Complex. The Level 2 Cache Controller also > -acts as directory-based coherency manager. > -All the properties in ePAPR/DeviceTree specification applies for this platform > - > -Required Properties: > --------------------- > -- compatible: Should be "sifive,fu540-c000-ccache" and "cache" > - > -- cache-block-size: Specifies the block size in bytes of the cache. > - Should be 64 > - > -- cache-level: Should be set to 2 for a level 2 cache > - > -- cache-sets: Specifies the number of associativity sets of the cache. > - Should be 1024 > - > -- cache-size: Specifies the size in bytes of the cache. Should be 2097152 > - > -- cache-unified: Specifies the cache is a unified cache > - > -- interrupts: Must contain 3 entries (DirError, DataError and DataFail signals) > - > -- reg: Physical base address and size of L2 cache controller registers map > - > -Optional Properties: > --------------------- > -- next-level-cache: phandle to the next level cache if present. > - > -- memory-region: reference to the reserved-memory for the L2 Loosely Integrated > - Memory region. The reserved memory node should be defined as per the bindings > - in reserved-memory.txt > - > - > -Example: > - > - cache-controller@2010000 { > - compatible = "sifive,fu540-c000-ccache", "cache"; > - cache-block-size = <64>; > - cache-level = <2>; > - cache-sets = <1024>; > - cache-size = <2097152>; > - cache-unified; > - interrupt-parent = <&plic0>; > - interrupts = <1 2 3>; > - reg = <0x0 0x2010000 0x0 0x1000>; > - next-level-cache = <&L25 &L40 &L36>; > - memory-region = <&l2_lim>; > - }; > diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > new file mode 100644 > index 0000000..e14c8c6 > --- /dev/null > +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > @@ -0,0 +1,92 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +# Copyright (C) 2020 SiFive, Inc. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: SiFive L2 Cache Controller > + > +maintainers: > + - Sagar Kadam <sagar.kadam@sifive.com> > + - Yash Shah <yash.shah@sifive.com> > + - Paul Walmsley <paul.walmsley@sifive.com> > + > +description: > + The SiFive Level 2 Cache Controller is used to provide access to fast copies > + of memory for masters in a Core Complex. The Level 2 Cache Controller also > + acts as directory-based coherency manager. > + All the properties in ePAPR/DeviceTree specification applies for this platform. > + > +allOf: > + - $ref: /schemas/cache-controller.yaml# > + > +properties: > + compatible: > + items: > + - enum: > + - sifive,fu540-c000-ccache > + description: | > + Should have "sifive,<soc>-cache" and "cache". That's not what the schema describes or the example has (the 'cache' fallback). > + > + cache-block-size: > + const: 64 > + > + cache-level: > + const: 2 > + > + cache-sets: > + const: 1024 > + > + cache-size: > + const: 2097152 > + > + cache-unified: true > + > + interrupts: > + description: | > + Must contain entries for DirError, DataError and DataFail signals. > + minItems: 1 The old doc said must have 3 entries. > + maxItems: 3 > + > + reg: > + maxItems: 1 > + description: address of cache controller's registers. Drop this. > + > + One blank line please. > + next-level-cache: > + description: | > + Phandle to the next level cache if present. No need to re-describe common properties unless you have something unique to this device to say. Just: 'next-level-cache: true' > + > + memory-region: > + description: | > + The reference to the reserved-memory for the L2 Loosely Integrated memory region. > + The reserved memory node should be defined as per the bindings in reserved-memory.txt. > + > +additionalProperties: false > + > +required: > + - compatible > + - cache-block-size > + - cache-level > + - cache-sets > + - cache-size > + - cache-unified > + - interrupts > + - reg > + > +examples: > + - | > + cache-controller@2010000 { > + compatible = "sifive,fu540-c000-ccache"; > + cache-block-size = <64>; > + cache-level = <2>; > + cache-sets = <1024>; > + cache-size = <2097152>; > + cache-unified; > + reg = <0x2010000 0x1000>; > + interrupt-parent = <&plic0>; > + interrupts = <1 2 3>; > + next-level-cache = <&L25>; > + memory-region = <&l2_lim>; > + }; > -- > 2.7.4 >
Hello Rob, > -----Original Message----- > From: Rob Herring <robh@kernel.org> > Sent: Monday, September 14, 2020 11:30 PM > To: Sagar Kadam <sagar.kadam@openfive.com> > Cc: linux-kernel@vger.kernel.org; linux-riscv@lists.infradead.org; > devicetree@vger.kernel.org; Paul Walmsley ( Sifive) > <paul.walmsley@sifive.com>; palmer@dabbelt.com; > aou@eecs.berkeley.edu; Yash Shah <yash.shah@openfive.com> > Subject: Re: [RESEND PATCH v2 1/1] dt-bindings: riscv: sifive-l2-cache: > convert bindings to json-schema > > [External Email] Do not click links or attachments unless you recognize the > sender and know the content is safe > > On Fri, Aug 28, 2020 at 10:25:43PM +0530, Sagar Kadam wrote: > > Convert the device tree bindings for the SiFive's FU540-C000 SoC's L2 > Cache > > controller to YAML format. > > > > Signed-off-by: Sagar Kadam <sagar.kadam@sifive.com> > > --- > > .../devicetree/bindings/riscv/sifive-l2-cache.txt | 51 ------------ > > .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 92 > ++++++++++++++++++++++ > > 2 files changed, 92 insertions(+), 51 deletions(-) > > delete mode 100644 Documentation/devicetree/bindings/riscv/sifive-l2- > cache.txt > > create mode 100644 Documentation/devicetree/bindings/riscv/sifive-l2- > cache.yaml > > > > diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > deleted file mode 100644 > > index 73d8f19..0000000 > > --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > +++ /dev/null > > @@ -1,51 +0,0 @@ > > -SiFive L2 Cache Controller > > --------------------------- > > -The SiFive Level 2 Cache Controller is used to provide access to fast > copies > > -of memory for masters in a Core Complex. The Level 2 Cache Controller > also > > -acts as directory-based coherency manager. > > -All the properties in ePAPR/DeviceTree specification applies for this > platform > > - > > -Required Properties: > > --------------------- > > -- compatible: Should be "sifive,fu540-c000-ccache" and "cache" > > - > > -- cache-block-size: Specifies the block size in bytes of the cache. > > - Should be 64 > > - > > -- cache-level: Should be set to 2 for a level 2 cache > > - > > -- cache-sets: Specifies the number of associativity sets of the cache. > > - Should be 1024 > > - > > -- cache-size: Specifies the size in bytes of the cache. Should be 2097152 > > - > > -- cache-unified: Specifies the cache is a unified cache > > - > > -- interrupts: Must contain 3 entries (DirError, DataError and DataFail > signals) > > - > > -- reg: Physical base address and size of L2 cache controller registers map > > - > > -Optional Properties: > > --------------------- > > -- next-level-cache: phandle to the next level cache if present. > > - > > -- memory-region: reference to the reserved-memory for the L2 Loosely > Integrated > > - Memory region. The reserved memory node should be defined as per > the bindings > > - in reserved-memory.txt > > - > > - > > -Example: > > - > > - cache-controller@2010000 { > > - compatible = "sifive,fu540-c000-ccache", "cache"; > > - cache-block-size = <64>; > > - cache-level = <2>; > > - cache-sets = <1024>; > > - cache-size = <2097152>; > > - cache-unified; > > - interrupt-parent = <&plic0>; > > - interrupts = <1 2 3>; > > - reg = <0x0 0x2010000 0x0 0x1000>; > > - next-level-cache = <&L25 &L40 &L36>; > > - memory-region = <&l2_lim>; > > - }; > > diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > > new file mode 100644 > > index 0000000..e14c8c6 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > > @@ -0,0 +1,92 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +# Copyright (C) 2020 SiFive, Inc. > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: SiFive L2 Cache Controller > > + > > +maintainers: > > + - Sagar Kadam <sagar.kadam@sifive.com> > > + - Yash Shah <yash.shah@sifive.com> > > + - Paul Walmsley <paul.walmsley@sifive.com> > > + > > +description: > > + The SiFive Level 2 Cache Controller is used to provide access to fast > copies > > + of memory for masters in a Core Complex. The Level 2 Cache Controller > also > > + acts as directory-based coherency manager. > > + All the properties in ePAPR/DeviceTree specification applies for this > platform. > > + > > +allOf: > > + - $ref: /schemas/cache-controller.yaml# > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - sifive,fu540-c000-ccache > > + description: | > > + Should have "sifive,<soc>-cache" and "cache". > > That's not what the schema describes or the example has (the 'cache' > fallback). > Thanks for your suggestions. I see that if we include the standard 'cache' property here, it injects error's in other yaml's as reported here [1] In plain txt format of this binding the standard "cache" property is mentioned to be also included along with soc specific compatible string. Please correct me if I am wrong here: So in order to retain the earlier description as Should have "sifive,<soc>-cache" and "cache", I excluded "cache" property from example as I assumed it is implied for cacheinfo infrastructure to work properly. I will retain the earlier description (from.txt) which was "sifive,fu540-c000-ccache" and "cache" [1] https://patchwork.ozlabs.org/patch/1350111 > > + > > + cache-block-size: > > + const: 64 > > + > > + cache-level: > > + const: 2 > > + > > + cache-sets: > > + const: 1024 > > + > > + cache-size: > > + const: 2097152 > > + > > + cache-unified: true > > + > > + interrupts: > > + description: | > > + Must contain entries for DirError, DataError and DataFail signals. > > + minItems: 1 > > The old doc said must have 3 entries. Will rectify. > > > + maxItems: 3 > > + > > + reg: > > + maxItems: 1 > > + description: address of cache controller's registers. > > Drop this. > Will drop the reg description in next version. > > + > > + > > One blank line please. > Will address this as well. > > + next-level-cache: > > + description: | > > + Phandle to the next level cache if present. > > No need to re-describe common properties unless you have something > unique to this device to say. Just: > > 'next-level-cache: true' > Ok. I will remove un-necessary description. Thanks & BR, Sagar > > + > > + memory-region: > > + description: | > > + The reference to the reserved-memory for the L2 Loosely Integrated > memory region. > > + The reserved memory node should be defined as per the bindings in > reserved-memory.txt. > > + > > +additionalProperties: false > > + > > +required: > > + - compatible > > + - cache-block-size > > + - cache-level > > + - cache-sets > > + - cache-size > > + - cache-unified > > + - interrupts > > + - reg > > + > > +examples: > > + - | > > + cache-controller@2010000 { > > + compatible = "sifive,fu540-c000-ccache"; > > + cache-block-size = <64>; > > + cache-level = <2>; > > + cache-sets = <1024>; > > + cache-size = <2097152>; > > + cache-unified; > > + reg = <0x2010000 0x1000>; > > + interrupt-parent = <&plic0>; > > + interrupts = <1 2 3>; > > + next-level-cache = <&L25>; > > + memory-region = <&l2_lim>; > > + }; > > -- > > 2.7.4 > >
On Tue, Sep 15, 2020 at 9:17 AM Sagar Kadam <sagar.kadam@openfive.com> wrote: > > Hello Rob, > > > -----Original Message----- > > From: Rob Herring <robh@kernel.org> > > Sent: Monday, September 14, 2020 11:30 PM > > To: Sagar Kadam <sagar.kadam@openfive.com> > > Cc: linux-kernel@vger.kernel.org; linux-riscv@lists.infradead.org; > > devicetree@vger.kernel.org; Paul Walmsley ( Sifive) > > <paul.walmsley@sifive.com>; palmer@dabbelt.com; > > aou@eecs.berkeley.edu; Yash Shah <yash.shah@openfive.com> > > Subject: Re: [RESEND PATCH v2 1/1] dt-bindings: riscv: sifive-l2-cache: > > convert bindings to json-schema > > > > [External Email] Do not click links or attachments unless you recognize the > > sender and know the content is safe > > > > On Fri, Aug 28, 2020 at 10:25:43PM +0530, Sagar Kadam wrote: > > > Convert the device tree bindings for the SiFive's FU540-C000 SoC's L2 > > Cache > > > controller to YAML format. > > > > > > Signed-off-by: Sagar Kadam <sagar.kadam@sifive.com> > > > --- > > > .../devicetree/bindings/riscv/sifive-l2-cache.txt | 51 ------------ > > > .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 92 > > ++++++++++++++++++++++ > > > 2 files changed, 92 insertions(+), 51 deletions(-) > > > delete mode 100644 Documentation/devicetree/bindings/riscv/sifive-l2- > > cache.txt > > > create mode 100644 Documentation/devicetree/bindings/riscv/sifive-l2- > > cache.yaml > > > > > > diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > > deleted file mode 100644 > > > index 73d8f19..0000000 > > > --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > > +++ /dev/null > > > @@ -1,51 +0,0 @@ > > > -SiFive L2 Cache Controller > > > --------------------------- > > > -The SiFive Level 2 Cache Controller is used to provide access to fast > > copies > > > -of memory for masters in a Core Complex. The Level 2 Cache Controller > > also > > > -acts as directory-based coherency manager. > > > -All the properties in ePAPR/DeviceTree specification applies for this > > platform > > > - > > > -Required Properties: > > > --------------------- > > > -- compatible: Should be "sifive,fu540-c000-ccache" and "cache" > > > - > > > -- cache-block-size: Specifies the block size in bytes of the cache. > > > - Should be 64 > > > - > > > -- cache-level: Should be set to 2 for a level 2 cache > > > - > > > -- cache-sets: Specifies the number of associativity sets of the cache. > > > - Should be 1024 > > > - > > > -- cache-size: Specifies the size in bytes of the cache. Should be 2097152 > > > - > > > -- cache-unified: Specifies the cache is a unified cache > > > - > > > -- interrupts: Must contain 3 entries (DirError, DataError and DataFail > > signals) > > > - > > > -- reg: Physical base address and size of L2 cache controller registers map > > > - > > > -Optional Properties: > > > --------------------- > > > -- next-level-cache: phandle to the next level cache if present. > > > - > > > -- memory-region: reference to the reserved-memory for the L2 Loosely > > Integrated > > > - Memory region. The reserved memory node should be defined as per > > the bindings > > > - in reserved-memory.txt > > > - > > > - > > > -Example: > > > - > > > - cache-controller@2010000 { > > > - compatible = "sifive,fu540-c000-ccache", "cache"; > > > - cache-block-size = <64>; > > > - cache-level = <2>; > > > - cache-sets = <1024>; > > > - cache-size = <2097152>; > > > - cache-unified; > > > - interrupt-parent = <&plic0>; > > > - interrupts = <1 2 3>; > > > - reg = <0x0 0x2010000 0x0 0x1000>; > > > - next-level-cache = <&L25 &L40 &L36>; > > > - memory-region = <&l2_lim>; > > > - }; > > > diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > > b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > > > new file mode 100644 > > > index 0000000..e14c8c6 > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > > > @@ -0,0 +1,92 @@ > > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > > +# Copyright (C) 2020 SiFive, Inc. > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: SiFive L2 Cache Controller > > > + > > > +maintainers: > > > + - Sagar Kadam <sagar.kadam@sifive.com> > > > + - Yash Shah <yash.shah@sifive.com> > > > + - Paul Walmsley <paul.walmsley@sifive.com> > > > + > > > +description: > > > + The SiFive Level 2 Cache Controller is used to provide access to fast > > copies > > > + of memory for masters in a Core Complex. The Level 2 Cache Controller > > also > > > + acts as directory-based coherency manager. > > > + All the properties in ePAPR/DeviceTree specification applies for this > > platform. > > > + > > > +allOf: > > > + - $ref: /schemas/cache-controller.yaml# > > > + > > > +properties: > > > + compatible: > > > + items: > > > + - enum: > > > + - sifive,fu540-c000-ccache > > > + description: | > > > + Should have "sifive,<soc>-cache" and "cache". > > > > That's not what the schema describes or the example has (the 'cache' > > fallback). > > > Thanks for your suggestions. > I see that if we include the standard 'cache' property here, it injects error's in other yaml's as reported here [1] > In plain txt format of this binding the standard "cache" property is mentioned to be also included along with soc specific compatible string. > > Please correct me if I am wrong here: > So in order to retain the earlier description as Should have "sifive,<soc>-cache" and "cache", I excluded "cache" property from example > as I assumed it is implied for cacheinfo infrastructure to work properly. > I will retain the earlier description (from.txt) which was "sifive,fu540-c000-ccache" and "cache" You will need a custom 'select' schema to only match on "sifive,fu540-c000-ccache". There's numerous examples in the tree. Rob
Hello Rob, > -----Original Message----- > From: Rob Herring <robh@kernel.org> > Sent: Wednesday, September 23, 2020 12:57 AM > To: Sagar Kadam <sagar.kadam@openfive.com> > Cc: linux-kernel@vger.kernel.org; linux-riscv@lists.infradead.org; > devicetree@vger.kernel.org; Paul Walmsley ( Sifive) > <paul.walmsley@sifive.com>; palmer@dabbelt.com; > aou@eecs.berkeley.edu; Yash Shah <yash.shah@openfive.com> > Subject: Re: [RESEND PATCH v2 1/1] dt-bindings: riscv: sifive-l2-cache: convert > bindings to json-schema > > [External Email] Do not click links or attachments unless you recognize the > sender and know the content is safe > > On Tue, Sep 15, 2020 at 9:17 AM Sagar Kadam > <sagar.kadam@openfive.com> wrote: > > > > Hello Rob, > > > > > -----Original Message----- > > > From: Rob Herring <robh@kernel.org> > > > Sent: Monday, September 14, 2020 11:30 PM > > > To: Sagar Kadam <sagar.kadam@openfive.com> > > > Cc: linux-kernel@vger.kernel.org; linux-riscv@lists.infradead.org; > > > devicetree@vger.kernel.org; Paul Walmsley ( Sifive) > > > <paul.walmsley@sifive.com>; palmer@dabbelt.com; > > > aou@eecs.berkeley.edu; Yash Shah <yash.shah@openfive.com> > > > Subject: Re: [RESEND PATCH v2 1/1] dt-bindings: riscv: sifive-l2-cache: > > > convert bindings to json-schema > > > > > > [External Email] Do not click links or attachments unless you recognize the > > > sender and know the content is safe > > > > > > On Fri, Aug 28, 2020 at 10:25:43PM +0530, Sagar Kadam wrote: > > > > Convert the device tree bindings for the SiFive's FU540-C000 SoC's L2 > > > Cache > > > > controller to YAML format. > > > > > > > > Signed-off-by: Sagar Kadam <sagar.kadam@sifive.com> > > > > --- > > > > .../devicetree/bindings/riscv/sifive-l2-cache.txt | 51 ------------ > > > > .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 92 > > > ++++++++++++++++++++++ > > > > 2 files changed, 92 insertions(+), 51 deletions(-) > > > > delete mode 100644 Documentation/devicetree/bindings/riscv/sifive- > l2- > > > cache.txt > > > > create mode 100644 Documentation/devicetree/bindings/riscv/sifive- > l2- > > > cache.yaml > > > > > > > > diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > > b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > > > deleted file mode 100644 > > > > index 73d8f19..0000000 > > > > --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > > > +++ /dev/null > > > > @@ -1,51 +0,0 @@ > > > > -SiFive L2 Cache Controller > > > > --------------------------- > > > > -The SiFive Level 2 Cache Controller is used to provide access to fast > > > copies > > > > -of memory for masters in a Core Complex. The Level 2 Cache > Controller > > > also > > > > -acts as directory-based coherency manager. > > > > -All the properties in ePAPR/DeviceTree specification applies for this > > > platform > > > > - > > > > -Required Properties: > > > > --------------------- > > > > -- compatible: Should be "sifive,fu540-c000-ccache" and "cache" > > > > - > > > > -- cache-block-size: Specifies the block size in bytes of the cache. > > > > - Should be 64 > > > > - > > > > -- cache-level: Should be set to 2 for a level 2 cache > > > > - > > > > -- cache-sets: Specifies the number of associativity sets of the cache. > > > > - Should be 1024 > > > > - > > > > -- cache-size: Specifies the size in bytes of the cache. Should be 2097152 > > > > - > > > > -- cache-unified: Specifies the cache is a unified cache > > > > - > > > > -- interrupts: Must contain 3 entries (DirError, DataError and DataFail > > > signals) > > > > - > > > > -- reg: Physical base address and size of L2 cache controller registers > map > > > > - > > > > -Optional Properties: > > > > --------------------- > > > > -- next-level-cache: phandle to the next level cache if present. > > > > - > > > > -- memory-region: reference to the reserved-memory for the L2 Loosely > > > Integrated > > > > - Memory region. The reserved memory node should be defined as per > > > the bindings > > > > - in reserved-memory.txt > > > > - > > > > - > > > > -Example: > > > > - > > > > - cache-controller@2010000 { > > > > - compatible = "sifive,fu540-c000-ccache", "cache"; > > > > - cache-block-size = <64>; > > > > - cache-level = <2>; > > > > - cache-sets = <1024>; > > > > - cache-size = <2097152>; > > > > - cache-unified; > > > > - interrupt-parent = <&plic0>; > > > > - interrupts = <1 2 3>; > > > > - reg = <0x0 0x2010000 0x0 0x1000>; > > > > - next-level-cache = <&L25 &L40 &L36>; > > > > - memory-region = <&l2_lim>; > > > > - }; > > > > diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2- > cache.yaml > > > b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > > > > new file mode 100644 > > > > index 0000000..e14c8c6 > > > > --- /dev/null > > > > +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > > > > @@ -0,0 +1,92 @@ > > > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > > > +# Copyright (C) 2020 SiFive, Inc. > > > > +%YAML 1.2 > > > > +--- > > > > +$id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml# > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > > + > > > > +title: SiFive L2 Cache Controller > > > > + > > > > +maintainers: > > > > + - Sagar Kadam <sagar.kadam@sifive.com> > > > > + - Yash Shah <yash.shah@sifive.com> > > > > + - Paul Walmsley <paul.walmsley@sifive.com> > > > > + > > > > +description: > > > > + The SiFive Level 2 Cache Controller is used to provide access to fast > > > copies > > > > + of memory for masters in a Core Complex. The Level 2 Cache > Controller > > > also > > > > + acts as directory-based coherency manager. > > > > + All the properties in ePAPR/DeviceTree specification applies for this > > > platform. > > > > + > > > > +allOf: > > > > + - $ref: /schemas/cache-controller.yaml# > > > > + > > > > +properties: > > > > + compatible: > > > > + items: > > > > + - enum: > > > > + - sifive,fu540-c000-ccache > > > > + description: | > > > > + Should have "sifive,<soc>-cache" and "cache". > > > > > > That's not what the schema describes or the example has (the 'cache' > > > fallback). > > > > > Thanks for your suggestions. > > I see that if we include the standard 'cache' property here, it injects error's > in other yaml's as reported here [1] > > In plain txt format of this binding the standard "cache" property is > mentioned to be also included along with soc specific compatible string. > > > > Please correct me if I am wrong here: > > So in order to retain the earlier description as Should have "sifive,<soc>- > cache" and "cache", I excluded "cache" property from example > > as I assumed it is implied for cacheinfo infrastructure to work properly. > > I will retain the earlier description (from.txt) which was "sifive,fu540-c000- > ccache" and "cache" > > You will need a custom 'select' schema to only match on > "sifive,fu540-c000-ccache". There's numerous examples in the tree. > > Rob Thanks for the suggestion, this is useful to me. I will refer to some examples using "select" BR, Sagar Kadam
diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt deleted file mode 100644 index 73d8f19..0000000 --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt +++ /dev/null @@ -1,51 +0,0 @@ -SiFive L2 Cache Controller --------------------------- -The SiFive Level 2 Cache Controller is used to provide access to fast copies -of memory for masters in a Core Complex. The Level 2 Cache Controller also -acts as directory-based coherency manager. -All the properties in ePAPR/DeviceTree specification applies for this platform - -Required Properties: --------------------- -- compatible: Should be "sifive,fu540-c000-ccache" and "cache" - -- cache-block-size: Specifies the block size in bytes of the cache. - Should be 64 - -- cache-level: Should be set to 2 for a level 2 cache - -- cache-sets: Specifies the number of associativity sets of the cache. - Should be 1024 - -- cache-size: Specifies the size in bytes of the cache. Should be 2097152 - -- cache-unified: Specifies the cache is a unified cache - -- interrupts: Must contain 3 entries (DirError, DataError and DataFail signals) - -- reg: Physical base address and size of L2 cache controller registers map - -Optional Properties: --------------------- -- next-level-cache: phandle to the next level cache if present. - -- memory-region: reference to the reserved-memory for the L2 Loosely Integrated - Memory region. The reserved memory node should be defined as per the bindings - in reserved-memory.txt - - -Example: - - cache-controller@2010000 { - compatible = "sifive,fu540-c000-ccache", "cache"; - cache-block-size = <64>; - cache-level = <2>; - cache-sets = <1024>; - cache-size = <2097152>; - cache-unified; - interrupt-parent = <&plic0>; - interrupts = <1 2 3>; - reg = <0x0 0x2010000 0x0 0x1000>; - next-level-cache = <&L25 &L40 &L36>; - memory-region = <&l2_lim>; - }; diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml new file mode 100644 index 0000000..e14c8c6 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2020 SiFive, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive L2 Cache Controller + +maintainers: + - Sagar Kadam <sagar.kadam@sifive.com> + - Yash Shah <yash.shah@sifive.com> + - Paul Walmsley <paul.walmsley@sifive.com> + +description: + The SiFive Level 2 Cache Controller is used to provide access to fast copies + of memory for masters in a Core Complex. The Level 2 Cache Controller also + acts as directory-based coherency manager. + All the properties in ePAPR/DeviceTree specification applies for this platform. + +allOf: + - $ref: /schemas/cache-controller.yaml# + +properties: + compatible: + items: + - enum: + - sifive,fu540-c000-ccache + description: | + Should have "sifive,<soc>-cache" and "cache". + + cache-block-size: + const: 64 + + cache-level: + const: 2 + + cache-sets: + const: 1024 + + cache-size: + const: 2097152 + + cache-unified: true + + interrupts: + description: | + Must contain entries for DirError, DataError and DataFail signals. + minItems: 1 + maxItems: 3 + + reg: + maxItems: 1 + description: address of cache controller's registers. + + + next-level-cache: + description: | + Phandle to the next level cache if present. + + memory-region: + description: | + The reference to the reserved-memory for the L2 Loosely Integrated memory region. + The reserved memory node should be defined as per the bindings in reserved-memory.txt. + +additionalProperties: false + +required: + - compatible + - cache-block-size + - cache-level + - cache-sets + - cache-size + - cache-unified + - interrupts + - reg + +examples: + - | + cache-controller@2010000 { + compatible = "sifive,fu540-c000-ccache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <1024>; + cache-size = <2097152>; + cache-unified; + reg = <0x2010000 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <1 2 3>; + next-level-cache = <&L25>; + memory-region = <&l2_lim>; + };
Convert the device tree bindings for the SiFive's FU540-C000 SoC's L2 Cache controller to YAML format. Signed-off-by: Sagar Kadam <sagar.kadam@sifive.com> --- .../devicetree/bindings/riscv/sifive-l2-cache.txt | 51 ------------ .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 92 ++++++++++++++++++++++ 2 files changed, 92 insertions(+), 51 deletions(-) delete mode 100644 Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt create mode 100644 Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml