[v2] serial: max310x: rework RX interrupt handling

Currently, the RX interrupt logic uses the RXEMPTY interrupt, with the
RXEMPTYINV bit set, which means we get an RX interrupt as soon as the
RX FIFO is non-empty.

However, with the MAX310X having a FIFO of 128 bytes, this makes very
poor use of the FIFO: we trigger an interrupt as soon as the RX FIFO
has one byte, which means a lot of interrupts, each only collecting a
few bytes from the FIFO, causing a significant CPU load.

Instead this commit relies on two other RX interrupt events:

 - MAX310X_IRQ_RXFIFO_BIT, which triggers when the RX FIFO has reached
   a certain threshold, which we define to be half of the FIFO
   size. This ensure we get an interrupt before the RX FIFO fills up.

 - MAX310X_LSR_RXTO_BIT, which triggers when the RX FIFO has received
   some bytes, and then no more bytes are received for a certain
   time. Arbitrarily, this time is defined to the time is takes to
   receive 4 characters.

On a Microchip SAMA5D3 platform that is receiving 20 bytes every 16ms
over one MAX310X UART, this patch has allowed to reduce the CPU
consumption of the interrupt handler thread from ~25% to 6-7%.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
---
Changes since v1:
- Fix missing space when closing a comment
---
 drivers/tty/serial/max310x.c | 29 ++++++++++++++++++++++++-----
 1 file changed, 24 insertions(+), 5 deletions(-)

On čtvrtek 1. října 2020 9:44:15 CEST, Thomas Petazzoni wrote:
> Currently, the RX interrupt logic uses the RXEMPTY interrupt, with the
> RXEMPTYINV bit set, which means we get an RX interrupt as soon as the
> RX FIFO is non-empty.
>
> However, with the MAX310X having a FIFO of 128 bytes, this makes very
> poor use of the FIFO: we trigger an interrupt as soon as the RX FIFO
> has one byte, which means a lot of interrupts, each only collecting a
> few bytes from the FIFO, causing a significant CPU load.

Thanks for taking the time to write this patch. We're using MAX14830 on a 
Clearfog Base board via a 26 MHz SPI bus. Our code polls a custom 
peripheral over UART at 115200 baud ten times a second; the messages are 
typically shorter than 50 chars. Before this patch, `perf top --sort 
comm,dso` showed about 28% CPU load for the corresponding SPI kthread, 
after applying this patch it's between 3 and 5%. That's cool :).

Tested-by: Jan Kundrát <jan.kundrat@cesnet.cz>
Reviewed-by: Jan Kundrát <jan.kundrat@cesnet.cz>

(but see below, please)

> +	/* Enable LSR, RX FIFO trigger, CTS change interrupts */
> +	val = MAX310X_IRQ_LSR_BIT  | MAX310X_IRQ_RXFIFO_BIT | 
> MAX310X_IRQ_TXEMPTY_BIT;
>  	max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT);

This comment doesn't fully match that code, and also the effective value 
that is written to the register is split into two statements. What about 
just:

+	/* Enable LSR, RX FIFO trigger, TX FIFO empty, CTS change interrupts */
+ 	max310x_port_write(port, MAX310X_IRQEN_REG, MAX310X_IRQ_LSR_BIT | 
MAX310X_IRQ_RXFIFO_BIT | MAX310X_IRQ_TXEMPTY_BIT | MAX310X_IRQ_CTS_BIT);

With kind regards,
Jan

Hello,

On Wed, 28 Oct 2020 18:06:51 +0100
Thomas Petazzoni <thomas.petazzoni@bootlin.com> wrote:

> On my way to send a v3 :-)

Well, in fact the patch is upstream already:

  https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/tty/serial/max310x.c?id=fce3c5c1a2d9cd888f2987662ce17c0c651916b2

So I'll send a follow-up patch instead.

Thanks,

Thomas