| Message ID | 20200818215227.181654-1-jusual@redhat.com |
|---|---|
| Headers | show |
| Series | Use ACPI PCI hot-plug for q35 | expand |
On Fri, Aug 21, 2020 at 2:13 PM Igor Mammedov <imammedo@redhat.com> wrote: > > On Tue, 18 Aug 2020 23:52:26 +0200 > Julia Suvorova <jusual@redhat.com> wrote: > > > Other methods may be used if the system is capable of this and the _OSC bit > > is set. Disable them explicitly to force ACPI PCI hot-plug use. The older > > versions will still use PCIe native. > > > > Signed-off-by: Julia Suvorova <jusual@redhat.com> > > --- > > hw/i386/acpi-build.h | 11 +++++++++++ > > hw/i386/acpi-build.c | 21 +++++++++++++++------ > > 2 files changed, 26 insertions(+), 6 deletions(-) > > > > diff --git a/hw/i386/acpi-build.h b/hw/i386/acpi-build.h > > index 74df5fc612..6f94312c39 100644 > > --- a/hw/i386/acpi-build.h > > +++ b/hw/i386/acpi-build.h > > @@ -5,6 +5,17 @@ > > > > extern const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio; > > > > +/* PCI Firmware Specification 3.2, Table 4-5 */ > > +typedef enum { > > + ACPI_OSC_NATIVE_HP_EN = 0, > > + ACPI_OSC_SHPC_EN = 1, > > + ACPI_OSC_PME_EN = 2, > > + ACPI_OSC_AER_EN = 3, > > + ACPI_OSC_PCIE_CAP_EN = 4, > > + ACPI_OSC_LTR_EN = 5, > > + ACPI_OSC_ALLONES_INVALID = 6, > > +} AcpiOSCField; > > + > > void acpi_setup(void); > > > > #endif > > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c > > index f3cd52bd06..c5f4802b8c 100644 > > --- a/hw/i386/acpi-build.c > > +++ b/hw/i386/acpi-build.c > > @@ -1411,7 +1411,7 @@ static void build_i386_pci_hotplug(Aml *table, uint64_t pcihp_addr) > > aml_append(table, scope); > > } > > > > -static Aml *build_q35_osc_method(void) > > +static Aml *build_q35_osc_method(AcpiPmInfo *pm) > > { > > Aml *if_ctx; > > Aml *if_ctx2; > > @@ -1419,6 +1419,7 @@ static Aml *build_q35_osc_method(void) > > Aml *method; > > Aml *a_cwd1 = aml_name("CDW1"); > > Aml *a_ctrl = aml_local(0); > > + unsigned osc_ctrl; > > > > method = aml_method("_OSC", 4, AML_NOTSERIALIZED); > > aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); > > @@ -1430,11 +1431,19 @@ static Aml *build_q35_osc_method(void) > > > > aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); > > > > + /* Always allow native PME, AER (depend on PCIE Capability Control) */ > > + osc_ctrl = BIT(ACPI_OSC_PME_EN) | BIT(ACPI_OSC_AER_EN) | > > + BIT(ACPI_OSC_PCIE_CAP_EN); > > + > > /* > > - * Always allow native PME, AER (no dependencies) > > - * Allow SHPC (PCI bridges can have SHPC controller) > > + * Guests seem to generally prefer native hot-plug control. > > + * Enable it only when we do not use ACPI hot-plug. > > */ > > - aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl)); > > + if (!pm->pcihp_bridge_en) { > > + osc_ctrl |= BIT(ACPI_OSC_NATIVE_HP_EN) | BIT(ACPI_OSC_SHPC_EN); > > + } > > ACPI hotplug works only for coldplugged bridges, and native one is used > on hotplugged ones. > Wouldn't that break SHPC/Native hotplug on hotplugged PCI/PCI-E bridge? Yes, it would. I'll mention it in the commit message. > > + aml_append(if_ctx, aml_and(a_ctrl, aml_int(osc_ctrl), a_ctrl)); > > > > if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); > > /* Unknown revision */ > > @@ -1514,7 +1523,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > > aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); > > aml_append(dev, aml_name_decl("_ADR", aml_int(0))); > > aml_append(dev, aml_name_decl("_UID", aml_int(1))); > > - aml_append(dev, build_q35_osc_method()); > > + aml_append(dev, build_q35_osc_method(pm)); > > aml_append(sb_scope, dev); > > aml_append(dsdt, sb_scope); > > > > @@ -1590,7 +1599,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > > if (pci_bus_is_express(bus)) { > > aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); > > aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); > > - aml_append(dev, build_q35_osc_method()); > > + aml_append(dev, build_q35_osc_method(pm)); > > } else { > > aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); > > } >
On Fri, Aug 21, 2020 at 2:08 PM Igor Mammedov <imammedo@redhat.com> wrote: > > On Tue, 18 Aug 2020 23:52:25 +0200 > Julia Suvorova <jusual@redhat.com> wrote: > > > Implement notifications and gpe to support q35 ACPI PCI hot-plug. > > Use 0xcc4 - 0xcd7 range for 'acpi-pci-hotplug' io ports. > > in addition to comment from Philippe > > > > > > Signed-off-by: Julia Suvorova <jusual@redhat.com> > > --- > > include/hw/acpi/pcihp.h | 3 ++- > > hw/acpi/pcihp.c | 10 ++++++---- > > hw/acpi/piix4.c | 2 +- > > hw/i386/acpi-build.c | 25 ++++++++++++++----------- > > 4 files changed, 23 insertions(+), 17 deletions(-) > > > > diff --git a/include/hw/acpi/pcihp.h b/include/hw/acpi/pcihp.h > > index 8bc4a4c01d..1e9d246f57 100644 > > --- a/include/hw/acpi/pcihp.h > > +++ b/include/hw/acpi/pcihp.h > > @@ -54,7 +54,8 @@ typedef struct AcpiPciHpState { > > } AcpiPciHpState; > > > > void acpi_pcihp_init(Object *owner, AcpiPciHpState *, PCIBus *root, > > - MemoryRegion *address_space_io, bool bridges_enabled); > > + MemoryRegion *address_space_io, bool bridges_enabled, > > + bool is_piix4); > > > > void acpi_pcihp_device_pre_plug_cb(HotplugHandler *hotplug_dev, > > DeviceState *dev, Error **errp); > > diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c > > index 9e31ab2da4..9a35ed6c83 100644 > > --- a/hw/acpi/pcihp.c > > +++ b/hw/acpi/pcihp.c > > @@ -38,7 +38,8 @@ > > #include "qom/qom-qobject.h" > > #include "trace.h" > > > > -#define ACPI_PCIHP_ADDR 0xae00 > > +#define ACPI_PCIHP_ADDR_PIIX4 0xae00 > > +#define ACPI_PCIHP_ADDR_Q35 0x0cc4 > > #define ACPI_PCIHP_SIZE 0x0014 > > #define PCI_UP_BASE 0x0000 > > #define PCI_DOWN_BASE 0x0004 > > @@ -359,12 +360,13 @@ static const MemoryRegionOps acpi_pcihp_io_ops = { > > }; > > > > void acpi_pcihp_init(Object *owner, AcpiPciHpState *s, PCIBus *root_bus, > > - MemoryRegion *address_space_io, bool bridges_enabled) > > + MemoryRegion *address_space_io, bool bridges_enabled, > > + bool is_piix4) > > { > > s->io_len = ACPI_PCIHP_SIZE; > > - s->io_base = ACPI_PCIHP_ADDR; > > + s->io_base = is_piix4 ? ACPI_PCIHP_ADDR_PIIX4 : ACPI_PCIHP_ADDR_Q35; > > > > - s->root= root_bus; > > + s->root = root_bus; > > s->legacy_piix = !bridges_enabled; > > > > memory_region_init_io(&s->io, owner, &acpi_pcihp_io_ops, s, > > diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c > > index cdfa0e2998..1f27bfbd06 100644 > > --- a/hw/acpi/piix4.c > > +++ b/hw/acpi/piix4.c > > @@ -596,7 +596,7 @@ static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, > > memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe); > > > > acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent, > > - s->use_acpi_hotplug_bridge); > > + s->use_acpi_hotplug_bridge, true); > > > > s->cpu_hotplug_legacy = true; > > object_property_add_bool(OBJECT(s), "cpu-hotplug-legacy", > > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c > > index b7bcbbbb2a..f3cd52bd06 100644 > > --- a/hw/i386/acpi-build.c > > +++ b/hw/i386/acpi-build.c > > @@ -201,10 +201,6 @@ static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) > > /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ > > pm->fadt.rev = 1; > > pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; > > - pm->pcihp_io_base = > > - object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); > > - pm->pcihp_io_len = > > - object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); > > } > > if (lpc) { > > struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, > > @@ -214,6 +210,10 @@ static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) > > pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; > > pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; > > } > > + pm->pcihp_io_base = > > + object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); > > + pm->pcihp_io_len = > > + object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); > > > > /* The above need not be conditional on machine type because the reset port > > * happens to be the same on PIIX (pc) and ICH9 (q35). */ > > @@ -472,7 +472,7 @@ static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, > > QLIST_FOREACH(sec, &bus->child, sibling) { > > int32_t devfn = sec->parent_dev->devfn; > > > > - if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) { > > + if (pci_bus_is_root(sec)) { > Does pcie bus on hostbridge fall into pci_bus_is_express() categiry or not? I don't understand why it's there in the first place. pci_bus_is_root() check is for pxb, but pci_bus_is_express() is useless because everything is under 'if (pcihp_bridge_en) {', which means that no pcie bus will get there (before this patch). > > continue; > > } > > > > @@ -1368,7 +1368,7 @@ static void build_piix4_isa_bridge(Aml *table) > > aml_append(table, scope); > > } > > > > -static void build_piix4_pci_hotplug(Aml *table) > > +static void build_i386_pci_hotplug(Aml *table, uint64_t pcihp_addr) > > { > > Aml *scope; > > Aml *field; > > @@ -1377,20 +1377,22 @@ static void build_piix4_pci_hotplug(Aml *table) > > scope = aml_scope("_SB.PCI0"); > > > > aml_append(scope, > > - aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08)); > > + aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08)); > > field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); > > aml_append(field, aml_named_field("PCIU", 32)); > > aml_append(field, aml_named_field("PCID", 32)); > > aml_append(scope, field); > > > > aml_append(scope, > > - aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04)); > > + aml_operation_region("SEJ", AML_SYSTEM_IO, > > + aml_int(pcihp_addr + 0x08), 0x04)); > ^^^^ > how about turning this offset into macro? > > > field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); > > aml_append(field, aml_named_field("B0EJ", 32)); > > aml_append(scope, field); > > > > aml_append(scope, > > - aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04)); > > + aml_operation_region("BNMR", AML_SYSTEM_IO, > > + aml_int(pcihp_addr + 0x10), 0x04)); > ditto > > > field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); > > aml_append(field, aml_named_field("BNUM", 32)); > > aml_append(scope, field); > > @@ -1504,7 +1506,6 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > > build_hpet_aml(dsdt); > > build_piix4_isa_bridge(dsdt); > > build_isa_devices_aml(dsdt); > > - build_piix4_pci_hotplug(dsdt); > > build_piix4_pci0_int(dsdt); > > } else { > > sb_scope = aml_scope("_SB"); > > @@ -1526,6 +1527,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > > } > > } > > > > + build_i386_pci_hotplug(dsdt, pm->pcihp_io_base); > > + > > if (pcmc->legacy_cpu_hotplug) { > > build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); > > } else { > > @@ -1546,7 +1549,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > > { > > aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); > > > > - if (misc->is_piix4) { > > + if (misc->is_piix4 || pm->pcihp_bridge_en) { > > method = aml_method("_E01", 0, AML_NOTSERIALIZED); > > aml_append(method, > > aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); >
On Wed, Sep 16, 2020 at 8:03 PM Julia Suvorova <jusual@redhat.com> wrote: > > On Fri, Aug 21, 2020 at 2:13 PM Igor Mammedov <imammedo@redhat.com> wrote: > > > > On Tue, 18 Aug 2020 23:52:26 +0200 > > Julia Suvorova <jusual@redhat.com> wrote: > > > > > Other methods may be used if the system is capable of this and the _OSC bit > > > is set. Disable them explicitly to force ACPI PCI hot-plug use. The older > > > versions will still use PCIe native. > > > > > > Signed-off-by: Julia Suvorova <jusual@redhat.com> > > > --- > > > hw/i386/acpi-build.h | 11 +++++++++++ > > > hw/i386/acpi-build.c | 21 +++++++++++++++------ > > > 2 files changed, 26 insertions(+), 6 deletions(-) > > > > > > diff --git a/hw/i386/acpi-build.h b/hw/i386/acpi-build.h > > > index 74df5fc612..6f94312c39 100644 > > > --- a/hw/i386/acpi-build.h > > > +++ b/hw/i386/acpi-build.h > > > @@ -5,6 +5,17 @@ > > > > > > extern const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio; > > > > > > +/* PCI Firmware Specification 3.2, Table 4-5 */ > > > +typedef enum { > > > + ACPI_OSC_NATIVE_HP_EN = 0, > > > + ACPI_OSC_SHPC_EN = 1, > > > + ACPI_OSC_PME_EN = 2, > > > + ACPI_OSC_AER_EN = 3, > > > + ACPI_OSC_PCIE_CAP_EN = 4, > > > + ACPI_OSC_LTR_EN = 5, > > > + ACPI_OSC_ALLONES_INVALID = 6, > > > +} AcpiOSCField; > > > + > > > void acpi_setup(void); > > > > > > #endif > > > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c > > > index f3cd52bd06..c5f4802b8c 100644 > > > --- a/hw/i386/acpi-build.c > > > +++ b/hw/i386/acpi-build.c > > > @@ -1411,7 +1411,7 @@ static void build_i386_pci_hotplug(Aml *table, uint64_t pcihp_addr) > > > aml_append(table, scope); > > > } > > > > > > -static Aml *build_q35_osc_method(void) > > > +static Aml *build_q35_osc_method(AcpiPmInfo *pm) > > > { > > > Aml *if_ctx; > > > Aml *if_ctx2; > > > @@ -1419,6 +1419,7 @@ static Aml *build_q35_osc_method(void) > > > Aml *method; > > > Aml *a_cwd1 = aml_name("CDW1"); > > > Aml *a_ctrl = aml_local(0); > > > + unsigned osc_ctrl; > > > > > > method = aml_method("_OSC", 4, AML_NOTSERIALIZED); > > > aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); > > > @@ -1430,11 +1431,19 @@ static Aml *build_q35_osc_method(void) > > > > > > aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); > > > > > > + /* Always allow native PME, AER (depend on PCIE Capability Control) */ > > > + osc_ctrl = BIT(ACPI_OSC_PME_EN) | BIT(ACPI_OSC_AER_EN) | > > > + BIT(ACPI_OSC_PCIE_CAP_EN); > > > + > > > /* > > > - * Always allow native PME, AER (no dependencies) > > > - * Allow SHPC (PCI bridges can have SHPC controller) > > > + * Guests seem to generally prefer native hot-plug control. > > > + * Enable it only when we do not use ACPI hot-plug. > > > */ > > > - aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl)); > > > + if (!pm->pcihp_bridge_en) { > > > + osc_ctrl |= BIT(ACPI_OSC_NATIVE_HP_EN) | BIT(ACPI_OSC_SHPC_EN); > > > + } > > > > ACPI hotplug works only for coldplugged bridges, and native one is used > > on hotplugged ones. > > Wouldn't that break SHPC/Native hotplug on hotplugged PCI/PCI-E bridge? Wait, what configuration are you talking about exactly? > > > + aml_append(if_ctx, aml_and(a_ctrl, aml_int(osc_ctrl), a_ctrl)); > > > > > > if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); > > > /* Unknown revision */ > > > @@ -1514,7 +1523,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > > > aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); > > > aml_append(dev, aml_name_decl("_ADR", aml_int(0))); > > > aml_append(dev, aml_name_decl("_UID", aml_int(1))); > > > - aml_append(dev, build_q35_osc_method()); > > > + aml_append(dev, build_q35_osc_method(pm)); > > > aml_append(sb_scope, dev); > > > aml_append(dsdt, sb_scope); > > > > > > @@ -1590,7 +1599,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > > > if (pci_bus_is_express(bus)) { > > > aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); > > > aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); > > > - aml_append(dev, build_q35_osc_method()); > > > + aml_append(dev, build_q35_osc_method(pm)); > > > } else { > > > aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); > > > } > >
On Wed, Aug 19, 2020 at 5:21 AM Philippe Mathieu-Daudé <philmd@redhat.com> wrote: > > Hi Julia, > > On 8/18/20 11:52 PM, Julia Suvorova wrote: > > Implement notifications and gpe to support q35 ACPI PCI hot-plug. > > Use 0xcc4 - 0xcd7 range for 'acpi-pci-hotplug' io ports. > > > > Signed-off-by: Julia Suvorova <jusual@redhat.com> > > --- > > include/hw/acpi/pcihp.h | 3 ++- > > hw/acpi/pcihp.c | 10 ++++++---- > > hw/acpi/piix4.c | 2 +- > > hw/i386/acpi-build.c | 25 ++++++++++++++----------- > > 4 files changed, 23 insertions(+), 17 deletions(-) > > > > diff --git a/include/hw/acpi/pcihp.h b/include/hw/acpi/pcihp.h > > index 8bc4a4c01d..1e9d246f57 100644 > > --- a/include/hw/acpi/pcihp.h > > +++ b/include/hw/acpi/pcihp.h > > @@ -54,7 +54,8 @@ typedef struct AcpiPciHpState { > > } AcpiPciHpState; > > > > void acpi_pcihp_init(Object *owner, AcpiPciHpState *, PCIBus *root, > > - MemoryRegion *address_space_io, bool bridges_enabled); > > + MemoryRegion *address_space_io, bool bridges_enabled, > > + bool is_piix4); > > > > void acpi_pcihp_device_pre_plug_cb(HotplugHandler *hotplug_dev, > > DeviceState *dev, Error **errp); > > diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c > > index 9e31ab2da4..9a35ed6c83 100644 > > --- a/hw/acpi/pcihp.c > > +++ b/hw/acpi/pcihp.c > > @@ -38,7 +38,8 @@ > > #include "qom/qom-qobject.h" > > #include "trace.h" > > > > -#define ACPI_PCIHP_ADDR 0xae00 > > +#define ACPI_PCIHP_ADDR_PIIX4 0xae00 > > +#define ACPI_PCIHP_ADDR_Q35 0x0cc4 > > #define ACPI_PCIHP_SIZE 0x0014 > > #define PCI_UP_BASE 0x0000 > > #define PCI_DOWN_BASE 0x0004 > > @@ -359,12 +360,13 @@ static const MemoryRegionOps acpi_pcihp_io_ops = { > > }; > > > > void acpi_pcihp_init(Object *owner, AcpiPciHpState *s, PCIBus *root_bus, > > - MemoryRegion *address_space_io, bool bridges_enabled) > > + MemoryRegion *address_space_io, bool bridges_enabled, > > + bool is_piix4) > > Instead of adding implementation knowledge to this generic function, can > you instead pass it a 'io_base' argument (or 'pcihp_addr')? Ok. > > { > > s->io_len = ACPI_PCIHP_SIZE; > > - s->io_base = ACPI_PCIHP_ADDR; > > + s->io_base = is_piix4 ? ACPI_PCIHP_ADDR_PIIX4 : ACPI_PCIHP_ADDR_Q35; > > > > - s->root= root_bus; > > + s->root = root_bus; > > s->legacy_piix = !bridges_enabled; > > > > memory_region_init_io(&s->io, owner, &acpi_pcihp_io_ops, s, > > diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c > > index cdfa0e2998..1f27bfbd06 100644 > > --- a/hw/acpi/piix4.c > > +++ b/hw/acpi/piix4.c > > @@ -596,7 +596,7 @@ static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, > > memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe); > > > > acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent, > > - s->use_acpi_hotplug_bridge); > > + s->use_acpi_hotplug_bridge, true); > > > > s->cpu_hotplug_legacy = true; > > object_property_add_bool(OBJECT(s), "cpu-hotplug-legacy", > > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c > > index b7bcbbbb2a..f3cd52bd06 100644 > > --- a/hw/i386/acpi-build.c > > +++ b/hw/i386/acpi-build.c > > @@ -201,10 +201,6 @@ static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) > > /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ > > pm->fadt.rev = 1; > > pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; > > - pm->pcihp_io_base = > > - object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); > > - pm->pcihp_io_len = > > - object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); > > } > > if (lpc) { > > struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, > > @@ -214,6 +210,10 @@ static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) > > pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; > > pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; > > } > > + pm->pcihp_io_base = > > + object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); > > + pm->pcihp_io_len = > > + object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); > > > > /* The above need not be conditional on machine type because the reset port > > * happens to be the same on PIIX (pc) and ICH9 (q35). */ > > @@ -472,7 +472,7 @@ static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, > > QLIST_FOREACH(sec, &bus->child, sibling) { > > int32_t devfn = sec->parent_dev->devfn; > > > > - if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) { > > + if (pci_bus_is_root(sec)) { > > Different patch? PCNT method is part of ACPI hot-plug, and we add it to q35 (pcie). > > continue; > > } > > > > @@ -1368,7 +1368,7 @@ static void build_piix4_isa_bridge(Aml *table) > > aml_append(table, scope); > > } > > > > -static void build_piix4_pci_hotplug(Aml *table) > > +static void build_i386_pci_hotplug(Aml *table, uint64_t pcihp_addr) > > Being common to 32/64-bit, I'd name that build_x86_pci_hotplug(). > > > { > > Aml *scope; > > Aml *field; > > @@ -1377,20 +1377,22 @@ static void build_piix4_pci_hotplug(Aml *table) > > scope = aml_scope("_SB.PCI0"); > > > > aml_append(scope, > > - aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08)); > > + aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08)); > > field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); > > aml_append(field, aml_named_field("PCIU", 32)); > > aml_append(field, aml_named_field("PCID", 32)); > > aml_append(scope, field); > > > > aml_append(scope, > > - aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04)); > > + aml_operation_region("SEJ", AML_SYSTEM_IO, > > + aml_int(pcihp_addr + 0x08), 0x04)); > > field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); > > aml_append(field, aml_named_field("B0EJ", 32)); > > aml_append(scope, field); > > > > aml_append(scope, > > - aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04)); > > + aml_operation_region("BNMR", AML_SYSTEM_IO, > > + aml_int(pcihp_addr + 0x10), 0x04)); > > field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); > > aml_append(field, aml_named_field("BNUM", 32)); > > aml_append(scope, field); > > @@ -1504,7 +1506,6 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > > build_hpet_aml(dsdt); > > build_piix4_isa_bridge(dsdt); > > build_isa_devices_aml(dsdt); > > - build_piix4_pci_hotplug(dsdt); > > build_piix4_pci0_int(dsdt); > > } else { > > sb_scope = aml_scope("_SB"); > > @@ -1526,6 +1527,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > > } > > } > > > > + build_i386_pci_hotplug(dsdt, pm->pcihp_io_base); > > + > > if (pcmc->legacy_cpu_hotplug) { > > build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); > > } else { > > @@ -1546,7 +1549,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > > { > > aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); > > > > - if (misc->is_piix4) { > > + if (misc->is_piix4 || pm->pcihp_bridge_en) { > > Why not directly check 'if (pm->pcihp_bridge_en) {'? GPE.1 should be implemented for pci root hotplug on piix4 even if pcihp_bridge_en is disabled. There will be a bit different logic with "[PATCH v5 09/11] piix4: don't reserve hw resources when hotplug is off globally", but it's not merged yet. > > method = aml_method("_E01", 0, AML_NOTSERIALIZED); > > aml_append(method, > > aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); > > > > Regards, > > Phil. >
On Wed, 16 Sep 2020 21:14:36 +0200 Julia Suvorova <jusual@redhat.com> wrote: > On Wed, Sep 16, 2020 at 8:03 PM Julia Suvorova <jusual@redhat.com> wrote: > > > > On Fri, Aug 21, 2020 at 2:13 PM Igor Mammedov <imammedo@redhat.com> wrote: > > > > > > On Tue, 18 Aug 2020 23:52:26 +0200 > > > Julia Suvorova <jusual@redhat.com> wrote: > > > > > > > Other methods may be used if the system is capable of this and the _OSC bit > > > > is set. Disable them explicitly to force ACPI PCI hot-plug use. The older > > > > versions will still use PCIe native. > > > > > > > > Signed-off-by: Julia Suvorova <jusual@redhat.com> > > > > --- > > > > hw/i386/acpi-build.h | 11 +++++++++++ > > > > hw/i386/acpi-build.c | 21 +++++++++++++++------ > > > > 2 files changed, 26 insertions(+), 6 deletions(-) > > > > > > > > diff --git a/hw/i386/acpi-build.h b/hw/i386/acpi-build.h > > > > index 74df5fc612..6f94312c39 100644 > > > > --- a/hw/i386/acpi-build.h > > > > +++ b/hw/i386/acpi-build.h > > > > @@ -5,6 +5,17 @@ > > > > > > > > extern const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio; > > > > > > > > +/* PCI Firmware Specification 3.2, Table 4-5 */ > > > > +typedef enum { > > > > + ACPI_OSC_NATIVE_HP_EN = 0, > > > > + ACPI_OSC_SHPC_EN = 1, > > > > + ACPI_OSC_PME_EN = 2, > > > > + ACPI_OSC_AER_EN = 3, > > > > + ACPI_OSC_PCIE_CAP_EN = 4, > > > > + ACPI_OSC_LTR_EN = 5, > > > > + ACPI_OSC_ALLONES_INVALID = 6, > > > > +} AcpiOSCField; > > > > + > > > > void acpi_setup(void); > > > > > > > > #endif > > > > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c > > > > index f3cd52bd06..c5f4802b8c 100644 > > > > --- a/hw/i386/acpi-build.c > > > > +++ b/hw/i386/acpi-build.c > > > > @@ -1411,7 +1411,7 @@ static void build_i386_pci_hotplug(Aml *table, uint64_t pcihp_addr) > > > > aml_append(table, scope); > > > > } > > > > > > > > -static Aml *build_q35_osc_method(void) > > > > +static Aml *build_q35_osc_method(AcpiPmInfo *pm) > > > > { > > > > Aml *if_ctx; > > > > Aml *if_ctx2; > > > > @@ -1419,6 +1419,7 @@ static Aml *build_q35_osc_method(void) > > > > Aml *method; > > > > Aml *a_cwd1 = aml_name("CDW1"); > > > > Aml *a_ctrl = aml_local(0); > > > > + unsigned osc_ctrl; > > > > > > > > method = aml_method("_OSC", 4, AML_NOTSERIALIZED); > > > > aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); > > > > @@ -1430,11 +1431,19 @@ static Aml *build_q35_osc_method(void) > > > > > > > > aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); > > > > > > > > + /* Always allow native PME, AER (depend on PCIE Capability Control) */ > > > > + osc_ctrl = BIT(ACPI_OSC_PME_EN) | BIT(ACPI_OSC_AER_EN) | > > > > + BIT(ACPI_OSC_PCIE_CAP_EN); > > > > + > > > > /* > > > > - * Always allow native PME, AER (no dependencies) > > > > - * Allow SHPC (PCI bridges can have SHPC controller) > > > > + * Guests seem to generally prefer native hot-plug control. > > > > + * Enable it only when we do not use ACPI hot-plug. > > > > */ > > > > - aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl)); > > > > + if (!pm->pcihp_bridge_en) { > > > > + osc_ctrl |= BIT(ACPI_OSC_NATIVE_HP_EN) | BIT(ACPI_OSC_SHPC_EN); > > > > + } > > > > > > ACPI hotplug works only for coldplugged bridges, and native one is used > > > on hotplugged ones. > > > Wouldn't that break SHPC/Native hotplug on hotplugged PCI/PCI-E bridge? > > Wait, what configuration are you talking about exactly? Currently on piix4, we have ACPI and native hotplug working simultaneously the former works on cold-plugged bridges and if you hotplug another bridge, that one will use native method. With above hunk it probably will break. > > > > > + aml_append(if_ctx, aml_and(a_ctrl, aml_int(osc_ctrl), a_ctrl)); > > > > > > > > if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); > > > > /* Unknown revision */ > > > > @@ -1514,7 +1523,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > > > > aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); > > > > aml_append(dev, aml_name_decl("_ADR", aml_int(0))); > > > > aml_append(dev, aml_name_decl("_UID", aml_int(1))); > > > > - aml_append(dev, build_q35_osc_method()); > > > > + aml_append(dev, build_q35_osc_method(pm)); > > > > aml_append(sb_scope, dev); > > > > aml_append(dsdt, sb_scope); > > > > > > > > @@ -1590,7 +1599,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > > > > if (pci_bus_is_express(bus)) { > > > > aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); > > > > aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); > > > > - aml_append(dev, build_q35_osc_method()); > > > > + aml_append(dev, build_q35_osc_method(pm)); > > > > } else { > > > > aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); > > > > } > > > >
On Thu, Sep 17, 2020 at 8:01 AM Igor Mammedov <imammedo@redhat.com> wrote: > > On Wed, 16 Sep 2020 21:14:36 +0200 > Julia Suvorova <jusual@redhat.com> wrote: > > > On Wed, Sep 16, 2020 at 8:03 PM Julia Suvorova <jusual@redhat.com> wrote: > > > > > > On Fri, Aug 21, 2020 at 2:13 PM Igor Mammedov <imammedo@redhat.com> wrote: > > > > > > > > On Tue, 18 Aug 2020 23:52:26 +0200 > > > > Julia Suvorova <jusual@redhat.com> wrote: > > > > > > > > > Other methods may be used if the system is capable of this and the _OSC bit > > > > > is set. Disable them explicitly to force ACPI PCI hot-plug use. The older > > > > > versions will still use PCIe native. > > > > > > > > > > Signed-off-by: Julia Suvorova <jusual@redhat.com> > > > > > --- > > > > > hw/i386/acpi-build.h | 11 +++++++++++ > > > > > hw/i386/acpi-build.c | 21 +++++++++++++++------ > > > > > 2 files changed, 26 insertions(+), 6 deletions(-) > > > > > > > > > > diff --git a/hw/i386/acpi-build.h b/hw/i386/acpi-build.h > > > > > index 74df5fc612..6f94312c39 100644 > > > > > --- a/hw/i386/acpi-build.h > > > > > +++ b/hw/i386/acpi-build.h > > > > > @@ -5,6 +5,17 @@ > > > > > > > > > > extern const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio; > > > > > > > > > > +/* PCI Firmware Specification 3.2, Table 4-5 */ > > > > > +typedef enum { > > > > > + ACPI_OSC_NATIVE_HP_EN = 0, > > > > > + ACPI_OSC_SHPC_EN = 1, > > > > > + ACPI_OSC_PME_EN = 2, > > > > > + ACPI_OSC_AER_EN = 3, > > > > > + ACPI_OSC_PCIE_CAP_EN = 4, > > > > > + ACPI_OSC_LTR_EN = 5, > > > > > + ACPI_OSC_ALLONES_INVALID = 6, > > > > > +} AcpiOSCField; > > > > > + > > > > > void acpi_setup(void); > > > > > > > > > > #endif > > > > > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c > > > > > index f3cd52bd06..c5f4802b8c 100644 > > > > > --- a/hw/i386/acpi-build.c > > > > > +++ b/hw/i386/acpi-build.c > > > > > @@ -1411,7 +1411,7 @@ static void build_i386_pci_hotplug(Aml *table, uint64_t pcihp_addr) > > > > > aml_append(table, scope); > > > > > } > > > > > > > > > > -static Aml *build_q35_osc_method(void) > > > > > +static Aml *build_q35_osc_method(AcpiPmInfo *pm) > > > > > { > > > > > Aml *if_ctx; > > > > > Aml *if_ctx2; > > > > > @@ -1419,6 +1419,7 @@ static Aml *build_q35_osc_method(void) > > > > > Aml *method; > > > > > Aml *a_cwd1 = aml_name("CDW1"); > > > > > Aml *a_ctrl = aml_local(0); > > > > > + unsigned osc_ctrl; > > > > > > > > > > method = aml_method("_OSC", 4, AML_NOTSERIALIZED); > > > > > aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); > > > > > @@ -1430,11 +1431,19 @@ static Aml *build_q35_osc_method(void) > > > > > > > > > > aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); > > > > > > > > > > + /* Always allow native PME, AER (depend on PCIE Capability Control) */ > > > > > + osc_ctrl = BIT(ACPI_OSC_PME_EN) | BIT(ACPI_OSC_AER_EN) | > > > > > + BIT(ACPI_OSC_PCIE_CAP_EN); > > > > > + > > > > > /* > > > > > - * Always allow native PME, AER (no dependencies) > > > > > - * Allow SHPC (PCI bridges can have SHPC controller) > > > > > + * Guests seem to generally prefer native hot-plug control. > > > > > + * Enable it only when we do not use ACPI hot-plug. > > > > > */ > > > > > - aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl)); > > > > > + if (!pm->pcihp_bridge_en) { > > > > > + osc_ctrl |= BIT(ACPI_OSC_NATIVE_HP_EN) | BIT(ACPI_OSC_SHPC_EN); > > > > > + } > > > > > > > > ACPI hotplug works only for coldplugged bridges, and native one is used > > > > on hotplugged ones. > > > > Wouldn't that break SHPC/Native hotplug on hotplugged PCI/PCI-E bridge? > > > > Wait, what configuration are you talking about exactly? > Currently on piix4, we have ACPI and native hotplug working simultaneously > the former works on cold-plugged bridges and if you hotplug another bridge, > that one will use native method. > With above hunk it probably will break. Ok, I will add a check for piix4. > > > > > > > + aml_append(if_ctx, aml_and(a_ctrl, aml_int(osc_ctrl), a_ctrl)); > > > > > > > > > > if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); > > > > > /* Unknown revision */ > > > > > @@ -1514,7 +1523,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > > > > > aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); > > > > > aml_append(dev, aml_name_decl("_ADR", aml_int(0))); > > > > > aml_append(dev, aml_name_decl("_UID", aml_int(1))); > > > > > - aml_append(dev, build_q35_osc_method()); > > > > > + aml_append(dev, build_q35_osc_method(pm)); > > > > > aml_append(sb_scope, dev); > > > > > aml_append(dsdt, sb_scope); > > > > > > > > > > @@ -1590,7 +1599,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > > > > > if (pci_bus_is_express(bus)) { > > > > > aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); > > > > > aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); > > > > > - aml_append(dev, build_q35_osc_method()); > > > > > + aml_append(dev, build_q35_osc_method(pm)); > > > > > } else { > > > > > aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); > > > > > } > > > > > > >
On Thu, 17 Sep 2020 12:40:16 +0200 Julia Suvorova <jusual@redhat.com> wrote: > On Thu, Sep 17, 2020 at 8:01 AM Igor Mammedov <imammedo@redhat.com> wrote: > > > > On Wed, 16 Sep 2020 21:14:36 +0200 > > Julia Suvorova <jusual@redhat.com> wrote: > > > > > On Wed, Sep 16, 2020 at 8:03 PM Julia Suvorova <jusual@redhat.com> wrote: > > > > > > > > On Fri, Aug 21, 2020 at 2:13 PM Igor Mammedov <imammedo@redhat.com> wrote: > > > > > > > > > > On Tue, 18 Aug 2020 23:52:26 +0200 > > > > > Julia Suvorova <jusual@redhat.com> wrote: > > > > > > > > > > > Other methods may be used if the system is capable of this and the _OSC bit > > > > > > is set. Disable them explicitly to force ACPI PCI hot-plug use. The older > > > > > > versions will still use PCIe native. > > > > > > > > > > > > Signed-off-by: Julia Suvorova <jusual@redhat.com> > > > > > > --- > > > > > > hw/i386/acpi-build.h | 11 +++++++++++ > > > > > > hw/i386/acpi-build.c | 21 +++++++++++++++------ > > > > > > 2 files changed, 26 insertions(+), 6 deletions(-) > > > > > > > > > > > > diff --git a/hw/i386/acpi-build.h b/hw/i386/acpi-build.h > > > > > > index 74df5fc612..6f94312c39 100644 > > > > > > --- a/hw/i386/acpi-build.h > > > > > > +++ b/hw/i386/acpi-build.h > > > > > > @@ -5,6 +5,17 @@ > > > > > > > > > > > > extern const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio; > > > > > > > > > > > > +/* PCI Firmware Specification 3.2, Table 4-5 */ > > > > > > +typedef enum { > > > > > > + ACPI_OSC_NATIVE_HP_EN = 0, > > > > > > + ACPI_OSC_SHPC_EN = 1, > > > > > > + ACPI_OSC_PME_EN = 2, > > > > > > + ACPI_OSC_AER_EN = 3, > > > > > > + ACPI_OSC_PCIE_CAP_EN = 4, > > > > > > + ACPI_OSC_LTR_EN = 5, > > > > > > + ACPI_OSC_ALLONES_INVALID = 6, > > > > > > +} AcpiOSCField; > > > > > > + > > > > > > void acpi_setup(void); > > > > > > > > > > > > #endif > > > > > > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c > > > > > > index f3cd52bd06..c5f4802b8c 100644 > > > > > > --- a/hw/i386/acpi-build.c > > > > > > +++ b/hw/i386/acpi-build.c > > > > > > @@ -1411,7 +1411,7 @@ static void build_i386_pci_hotplug(Aml *table, uint64_t pcihp_addr) > > > > > > aml_append(table, scope); > > > > > > } > > > > > > > > > > > > -static Aml *build_q35_osc_method(void) > > > > > > +static Aml *build_q35_osc_method(AcpiPmInfo *pm) > > > > > > { > > > > > > Aml *if_ctx; > > > > > > Aml *if_ctx2; > > > > > > @@ -1419,6 +1419,7 @@ static Aml *build_q35_osc_method(void) > > > > > > Aml *method; > > > > > > Aml *a_cwd1 = aml_name("CDW1"); > > > > > > Aml *a_ctrl = aml_local(0); > > > > > > + unsigned osc_ctrl; > > > > > > > > > > > > method = aml_method("_OSC", 4, AML_NOTSERIALIZED); > > > > > > aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); > > > > > > @@ -1430,11 +1431,19 @@ static Aml *build_q35_osc_method(void) > > > > > > > > > > > > aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); > > > > > > > > > > > > + /* Always allow native PME, AER (depend on PCIE Capability Control) */ > > > > > > + osc_ctrl = BIT(ACPI_OSC_PME_EN) | BIT(ACPI_OSC_AER_EN) | > > > > > > + BIT(ACPI_OSC_PCIE_CAP_EN); > > > > > > + > > > > > > /* > > > > > > - * Always allow native PME, AER (no dependencies) > > > > > > - * Allow SHPC (PCI bridges can have SHPC controller) > > > > > > + * Guests seem to generally prefer native hot-plug control. > > > > > > + * Enable it only when we do not use ACPI hot-plug. > > > > > > */ > > > > > > - aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl)); > > > > > > + if (!pm->pcihp_bridge_en) { > > > > > > + osc_ctrl |= BIT(ACPI_OSC_NATIVE_HP_EN) | BIT(ACPI_OSC_SHPC_EN); > > > > > > + } > > > > > > > > > > ACPI hotplug works only for coldplugged bridges, and native one is used > > > > > on hotplugged ones. > > > > > Wouldn't that break SHPC/Native hotplug on hotplugged PCI/PCI-E bridge? > > > > > > Wait, what configuration are you talking about exactly? > > Currently on piix4, we have ACPI and native hotplug working simultaneously > > the former works on cold-plugged bridges and if you hotplug another bridge, > > that one will use native method. > > With above hunk it probably will break. > > Ok, I will add a check for piix4. can we have the same behavior for q35 as well? i.e. could-plugged => ACPI hotplug hotplugged ports, bridges, whatnot => native hotplug > > > > > > > > > > + aml_append(if_ctx, aml_and(a_ctrl, aml_int(osc_ctrl), a_ctrl)); > > > > > > > > > > > > if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); > > > > > > /* Unknown revision */ > > > > > > @@ -1514,7 +1523,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > > > > > > aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); > > > > > > aml_append(dev, aml_name_decl("_ADR", aml_int(0))); > > > > > > aml_append(dev, aml_name_decl("_UID", aml_int(1))); > > > > > > - aml_append(dev, build_q35_osc_method()); > > > > > > + aml_append(dev, build_q35_osc_method(pm)); > > > > > > aml_append(sb_scope, dev); > > > > > > aml_append(dsdt, sb_scope); > > > > > > > > > > > > @@ -1590,7 +1599,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > > > > > > if (pci_bus_is_express(bus)) { > > > > > > aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); > > > > > > aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); > > > > > > - aml_append(dev, build_q35_osc_method()); > > > > > > + aml_append(dev, build_q35_osc_method(pm)); > > > > > > } else { > > > > > > aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); > > > > > > } > > > > > > > > > > >
PCIe native hot-plug has numerous problems with racing events and unpredictable guest behaviour (Windows). Switching to ACPI hot-plug for now. Tested on RHEL 8 and Windows 2019. pxb-pcie is not yet supported. v2: * new ioport range for acpiphp [Gerd] * drop find_pci_host() [Igor] * explain magic numbers in _OSC [Igor] * drop build_q35_pci_hotplug() wrapper [Igor] Julia Suvorova (4): hw/acpi/ich9: Trace ich9_gpe_readb()/writeb() hw/i386/acpi-build: Add ACPI PCI hot-plug methods to q35 hw/i386/acpi-build: Turn off support of PCIe native hot-plug and SHPC in _OSC hw/acpi/ich9: Enable ACPI PCI hot-plug hw/i386/acpi-build.h | 12 ++++++++++ include/hw/acpi/ich9.h | 3 +++ include/hw/acpi/pcihp.h | 3 ++- hw/acpi/ich9.c | 52 ++++++++++++++++++++++++++++++++++++++++- hw/acpi/pcihp.c | 15 ++++++++---- hw/acpi/piix4.c | 2 +- hw/i386/acpi-build.c | 48 +++++++++++++++++++++++-------------- hw/i386/pc.c | 1 + hw/acpi/trace-events | 4 ++++ 9 files changed, 114 insertions(+), 26 deletions(-)