[v1,0/4] Allow loading a no MMU kernel

This series allows loading a noMMU kernel using the -kernel option.
Currently if using -kernel QEMU assumes you also have firmware and loads
the kernel at a hardcoded offset. This series changes that so we only
load the kernel at an offset if a firmware (-bios) was loaded.

This series also adds a function to check if the CPU is 32-bit. This is
a step towards running 32-bit and 64-bit CPUs on the 64-bit RISC-V build
by using run time checks instead of compile time checks. We also allow
the user to sepcify a CPU for the sifive_u machine.

Alistair Francis (4):
  hw/riscv: sifive_u: Allow specifying the CPU
  hw/riscv: Return the end address of the loaded firmware
  hw/riscv: Add a riscv_is_32_bit() function
  hw/riscv: Load the kernel after the firmware

 include/hw/riscv/boot.h     | 11 +++++----
 include/hw/riscv/sifive_u.h |  1 +
 hw/riscv/boot.c             | 47 ++++++++++++++++++++++++-------------
 hw/riscv/opentitan.c        |  3 ++-
 hw/riscv/sifive_e.c         |  3 ++-
 hw/riscv/sifive_u.c         | 31 ++++++++++++++++++------
 hw/riscv/spike.c            | 14 ++++++++---
 hw/riscv/virt.c             | 14 ++++++++---
 8 files changed, 89 insertions(+), 35 deletions(-)

Hi Alistair,

On Fri, Oct 2, 2020 at 11:50 PM Alistair Francis
<alistair.francis@wdc.com> wrote:
>

> This series allows loading a noMMU kernel using the -kernel option.

> Currently if using -kernel QEMU assumes you also have firmware and loads

> the kernel at a hardcoded offset. This series changes that so we only

> load the kernel at an offset if a firmware (-bios) was loaded.

>

> This series also adds a function to check if the CPU is 32-bit. This is

> a step towards running 32-bit and 64-bit CPUs on the 64-bit RISC-V build

> by using run time checks instead of compile time checks. We also allow

> the user to sepcify a CPU for the sifive_u machine.


Could you please provide test scenarios for this series? I want to
have a try. Thanks.

>

> Alistair Francis (4):

>   hw/riscv: sifive_u: Allow specifying the CPU

>   hw/riscv: Return the end address of the loaded firmware

>   hw/riscv: Add a riscv_is_32_bit() function

>   hw/riscv: Load the kernel after the firmware

>

>  include/hw/riscv/boot.h     | 11 +++++----

>  include/hw/riscv/sifive_u.h |  1 +

>  hw/riscv/boot.c             | 47 ++++++++++++++++++++++++-------------

>  hw/riscv/opentitan.c        |  3 ++-

>  hw/riscv/sifive_e.c         |  3 ++-

>  hw/riscv/sifive_u.c         | 31 ++++++++++++++++++------

>  hw/riscv/spike.c            | 14 ++++++++---

>  hw/riscv/virt.c             | 14 ++++++++---

>  8 files changed, 89 insertions(+), 35 deletions(-)


Regards,
Bin

On Fri, Oct 9, 2020 at 3:14 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Fri, Oct 2, 2020 at 11:42 PM Alistair Francis
> <alistair.francis@wdc.com> wrote:
>
> It merits some commit message to explain why the return value of
> riscv_load_firmware() was changed from firmware entry address to
> firmware end address.

Done.

Alistair

>
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> >  include/hw/riscv/boot.h |  8 ++++----
> >  hw/riscv/boot.c         | 28 +++++++++++++++++-----------
> >  2 files changed, 21 insertions(+), 15 deletions(-)
> >
>
> Regards,
> Bin

On Fri, Oct 9, 2020 at 2:53 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Alistair,
>
> On Fri, Oct 2, 2020 at 11:50 PM Alistair Francis
> <alistair.francis@wdc.com> wrote:
> >
> > This series allows loading a noMMU kernel using the -kernel option.
> > Currently if using -kernel QEMU assumes you also have firmware and loads
> > the kernel at a hardcoded offset. This series changes that so we only
> > load the kernel at an offset if a firmware (-bios) was loaded.
> >
> > This series also adds a function to check if the CPU is 32-bit. This is
> > a step towards running 32-bit and 64-bit CPUs on the 64-bit RISC-V build
> > by using run time checks instead of compile time checks. We also allow
> > the user to sepcify a CPU for the sifive_u machine.
>
> Could you please provide test scenarios for this series? I want to
> have a try. Thanks.

Yep.

Build a noMMU kernel (you need the latest master commit a78c6f5956a9):
$ CROSS_COMPILE=riscv64-elf- ARCH=riscv make nommu_virt_defconfig
$ CROSS_COMPILE=riscv64-elf- ARCH=riscv make -j

Build a noMMU RISC-V userspace
$ git clonehttps://github.com/damien-lemoal/buildroot.git
$ make kendryte_k210_defconfig
$ make

Run QEMU:
./build/riscv64-softmmu/qemu-system-riscv64 -machine virt -m 64M \
-cpu rv64,mmu=false \
-serial mon:stdio -serial null -nographic \
-append "root=/dev/vda rw highres=off  console=ttyS0 mem=1G ip=dhcp
earlycon=sbi" \
-device virtio-net-device,netdev=net0,mac=52:54:00:12:34:02 -netdev
user,id=net0 \
-object rng-random,filename=/dev/urandom,id=rng0 -device
virtio-rng-device,rng=rng0 \
-smp 1 -d guest_errors \
-kernel ./Image \
-drive id=disk0,file=./nommu-rootfs.ext2,if=none,format=raw -device
virtio-blk-device,drive=disk0 -bios none

Alistair

>
> >
> > Alistair Francis (4):
> >   hw/riscv: sifive_u: Allow specifying the CPU
> >   hw/riscv: Return the end address of the loaded firmware
> >   hw/riscv: Add a riscv_is_32_bit() function
> >   hw/riscv: Load the kernel after the firmware
> >
> >  include/hw/riscv/boot.h     | 11 +++++----
> >  include/hw/riscv/sifive_u.h |  1 +
> >  hw/riscv/boot.c             | 47 ++++++++++++++++++++++++-------------
> >  hw/riscv/opentitan.c        |  3 ++-
> >  hw/riscv/sifive_e.c         |  3 ++-
> >  hw/riscv/sifive_u.c         | 31 ++++++++++++++++++------
> >  hw/riscv/spike.c            | 14 ++++++++---
> >  hw/riscv/virt.c             | 14 ++++++++---
> >  8 files changed, 89 insertions(+), 35 deletions(-)
>
> Regards,
> Bin